[J-u-boot.git] / arch / x86 / lib / mrccache.c

// SPDX-License-Identifier: GPL-2.0
/*
 * From coreboot src/southbridge/intel/bd82x6x/mrccache.c
 *
 * Copyright (C) 2014 Google Inc.
 * Copyright (C) 2015 Bin Meng <[email protected]>
 */

#include <common.h>
#include <dm.h>
#include <errno.h>
#include <fdtdec.h>
#include <log.h>
#include <malloc.h>
#include <net.h>
#include <spi.h>
#include <spi_flash.h>
#include <asm/global_data.h>
#include <asm/mrccache.h>
#include <dm/device-internal.h>
#include <dm/uclass-internal.h>

DECLARE_GLOBAL_DATA_PTR;

static uint mrc_block_size(uint data_size)
{
	uint mrc_size = sizeof(struct mrc_data_container) + data_size;

	return ALIGN(mrc_size, MRC_DATA_ALIGN);
}

static struct mrc_data_container *next_mrc_block(
	struct mrc_data_container *cache)
{
	/* MRC data blocks are aligned within the region */
	u8 *region_ptr = (u8 *)cache;

	region_ptr += mrc_block_size(cache->data_size);

	return (struct mrc_data_container *)region_ptr;
}

static int is_mrc_cache(struct mrc_data_container *cache)
{
	return cache && (cache->signature == MRC_DATA_SIGNATURE);
}

struct mrc_data_container *mrccache_find_current(struct mrc_region *entry)
{
	struct mrc_data_container *cache, *next;
	ulong base_addr, end_addr;
	uint id;

	base_addr = entry->base + entry->offset;
	end_addr = base_addr + entry->length;
	cache = NULL;

	/* Search for the last filled entry in the region */
	for (id = 0, next = (struct mrc_data_container *)base_addr;
	     is_mrc_cache(next);
	     id++) {
		cache = next;
		next = next_mrc_block(next);
		if ((ulong)next >= end_addr)
			break;
	}

	if (id-- == 0) {
		debug("%s: No valid MRC cache found.\n", __func__);
		return NULL;
	}

	/* Verify checksum */
	if (cache->checksum != compute_ip_checksum(cache->data,
						   cache->data_size)) {
		printf("%s: MRC cache checksum mismatch\n", __func__);
		return NULL;
	}

	debug("%s: picked entry %u from cache block\n", __func__, id);

	return cache;
}

/**
 * find_next_mrc_cache() - get next cache entry
 *
 * This moves to the next cache entry in the region, making sure it has enough
 * space to hold data of size @data_size.
 *
 * @entry:	MRC cache flash area
 * @cache:	Entry to start from
 * @data_size:	Required data size of the new entry. Note that we assume that
 *	all cache entries are the same size
 *
 * @return next cache entry if found, NULL if we got to the end
 */
static struct mrc_data_container *find_next_mrc_cache(struct mrc_region *entry,
		struct mrc_data_container *prev, int data_size)
{
	struct mrc_data_container *cache;
	ulong base_addr, end_addr;

	base_addr = entry->base + entry->offset;
	end_addr = base_addr + entry->length;

	/*
	 * We assume that all cache entries are the same size, but let's use
	 * data_size here for clarity.
	 */
	cache = next_mrc_block(prev);
	if ((ulong)cache + mrc_block_size(data_size) > end_addr) {
		/* Crossed the boundary */
		cache = NULL;
		debug("%s: no available entries found\n", __func__);
	} else {
		debug("%s: picked next entry from cache block at %p\n",
		      __func__, cache);
	}

	return cache;
}

/**
 * mrccache_update() - update the MRC cache with a new record
 *
 * This writes a new record to the end of the MRC cache region. If the new
 * record is the same as the latest record then the write is skipped
 *
 * @sf:		SPI flash to write to
 * @entry:	Position and size of MRC cache in SPI flash
 * @cur:	Record to write
 * @return 0 if updated, -EEXIST if the record is the same as the latest
 * record, -EINVAL if the record is not valid, other error if SPI write failed
 */
static int mrccache_update(struct udevice *sf, struct mrc_region *entry,
			   struct mrc_data_container *cur)
{
	struct mrc_data_container *cache;
	ulong offset;
	ulong base_addr;
	int ret;

	if (!is_mrc_cache(cur)) {
		debug("%s: Cache data not valid\n", __func__);
		return -EINVAL;
	}

	/* Find the last used block */
	base_addr = entry->base + entry->offset;
	debug("Updating MRC cache data\n");
	cache = mrccache_find_current(entry);
	if (cache && (cache->data_size == cur->data_size) &&
	    (!memcmp(cache, cur, cache->data_size + sizeof(*cur)))) {
		debug("MRC data in flash is up to date. No update\n");
		return -EEXIST;
	}

	/* Move to the next block, which will be the first unused block */
	if (cache)
		cache = find_next_mrc_cache(entry, cache, cur->data_size);

	/*
	 * If we have got to the end, erase the entire mrc-cache area and start
	 * again at block 0.
	 */
	if (!cache) {
		debug("Erasing the MRC cache region of %x bytes at %x\n",
		      entry->length, entry->offset);

		ret = spi_flash_erase_dm(sf, entry->offset, entry->length);
		if (ret) {
			debug("Failed to erase flash region\n");
			return ret;
		}
		cache = (struct mrc_data_container *)base_addr;
	}

	/* Write the data out */
	offset = (ulong)cache - base_addr + entry->offset;
	debug("Write MRC cache update to flash at %lx\n", offset);
	ret = spi_flash_write_dm(sf, offset, cur->data_size + sizeof(*cur),
				 cur);
	if (ret) {
		debug("Failed to write to SPI flash\n");
		return log_msg_ret("Cannot update mrccache", ret);
	}

	return 0;
}

static void mrccache_setup(struct mrc_output *mrc, void *data)
{
	struct mrc_data_container *cache = data;
	u16 checksum;

	cache->signature = MRC_DATA_SIGNATURE;
	cache->data_size = mrc->len;
	checksum = compute_ip_checksum(mrc->buf, cache->data_size);
	debug("Saving %d bytes for MRC output data, checksum %04x\n",
	      cache->data_size, checksum);
	cache->checksum = checksum;
	cache->reserved = 0;
	memcpy(cache->data, mrc->buf, cache->data_size);

	mrc->cache = cache;
}

int mrccache_reserve(void)
{
	int i;

	for (i = 0; i < MRC_TYPE_COUNT; i++) {
		struct mrc_output *mrc = &gd->arch.mrc[i];

		if (!mrc->len)
			continue;

		/* adjust stack pointer to store pure cache data plus header */
		gd->start_addr_sp -= (mrc->len + MRC_DATA_HEADER_SIZE);
		mrccache_setup(mrc, (void *)gd->start_addr_sp);

		gd->start_addr_sp &= ~0xf;
	}

	return 0;
}

int mrccache_get_region(enum mrc_type_t type, struct udevice **devp,
			struct mrc_region *entry)
{
	struct udevice *dev;
	ofnode mrc_node;
	ulong map_base;
	uint map_size;
	uint offset;
	ofnode node;
	u32 reg[2];
	int ret;

	/*
	 * Find the flash chip within the SPI controller node. Avoid probing
	 * the device here since it may put it into a strange state where the
	 * memory map cannot be read.
	 */
	ret = uclass_find_first_device(UCLASS_SPI_FLASH, &dev);
	if (ret || !dev) {
		/*
		 * Fall back to searching the device tree since driver model
		 * may not be ready yet (e.g. with FSPv1)
		 */
		node = ofnode_by_compatible(ofnode_null(), "jedec,spi-nor");
		if (!ofnode_valid(node))
			return log_msg_ret("Cannot find SPI flash\n", -ENOENT);
		ret = -ENODEV;
	} else {
		ret = dm_spi_get_mmap(dev, &map_base, &map_size, &offset);
		if (!ret)
			entry->base = map_base;
		node = dev_ofnode(dev);
	}

	/*
	 * At this point we have entry->base if ret == 0. If not, then we have
	 * the node and can look for memory-map
	 */
	if (ret) {
		ret = ofnode_read_u32_array(node, "memory-map", reg, 2);
		if (ret)
			return log_msg_ret("Cannot find memory map\n", ret);
		entry->base = reg[0];
	}

	/* Find the place where we put the MRC cache */
	mrc_node = ofnode_find_subnode(node, type == MRC_TYPE_NORMAL ?
				       "rw-mrc-cache" : "rw-var-mrc-cache");
	if (!ofnode_valid(mrc_node))
		return log_msg_ret("Cannot find node", -EPERM);

	ret = ofnode_read_u32_array(mrc_node, "reg", reg, 2);
	if (ret)
		return log_msg_ret("Cannot find address", ret);
	entry->offset = reg[0];
	entry->length = reg[1];

	if (devp)
		*devp = dev;
	debug("MRC cache type %d in '%s', offset %x, len %x, base %x\n",
	      type, dev ? dev->name : ofnode_get_name(node), entry->offset,
	      entry->length, entry->base);

	return 0;
}

static int mrccache_save_type(enum mrc_type_t type)
{
	struct mrc_data_container *cache;
	struct mrc_output *mrc;
	struct mrc_region entry;
	struct udevice *sf;
	int ret;

	mrc = &gd->arch.mrc[type];
	if (!mrc->len)
		return 0;
	log_debug("Saving %#x bytes of MRC output data type %d to SPI flash\n",
		  mrc->len, type);
	ret = mrccache_get_region(type, &sf, &entry);
	if (ret)
		return log_msg_ret("Cannot get region", ret);
	ret = device_probe(sf);
	if (ret)
		return log_msg_ret("Cannot probe device", ret);
	cache = mrc->cache;

	ret = mrccache_update(sf, &entry, cache);
	if (!ret)
		debug("Saved MRC data with checksum %04x\n", cache->checksum);
	else if (ret == -EEXIST)
		debug("MRC data is the same as last time, skipping save\n");

	return 0;
}

int mrccache_save(void)
{
	int i;

	for (i = 0; i < MRC_TYPE_COUNT; i++) {
		int ret;

		ret = mrccache_save_type(i);
		if (ret)
			return ret;
	}

	return 0;
}

int mrccache_spl_save(void)
{
	int i;

	for (i = 0; i < MRC_TYPE_COUNT; i++) {
		struct mrc_output *mrc = &gd->arch.mrc[i];
		void *data;
		int size;

		size = mrc->len + MRC_DATA_HEADER_SIZE;
		data = malloc(size);
		if (!data)
			return log_msg_ret("Allocate MRC cache block", -ENOMEM);
		mrccache_setup(mrc, data);
	}

	return mrccache_save();
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0
191c008a	2	/*
bfa95c53	3	* From coreboot src/southbridge/intel/bd82x6x/mrccache.c
191c008a SG	4	*
191c008a SG	5	* Copyright (C) 2014 Google Inc.
ed800961	6	* Copyright (C) 2015 Bin Meng <[email protected]>
191c008a SG	7	*/
	8
	9	#include <common.h>
ed800961	10	#include <dm.h>
191c008a SG	11	#include <errno.h>
191c008a SG	12	#include <fdtdec.h>
f7ae49fc	13	#include <log.h>
336d4615	14	#include <malloc.h>
191c008a SG	15	#include <net.h>
	16	#include <spi.h>
	17	#include <spi_flash.h>
401d1c4f	18	#include <asm/global_data.h>
f6220f1a	19	#include <asm/mrccache.h>
87f1084a SG	20	#include <dm/device-internal.h>
87f1084a SG	21	#include <dm/uclass-internal.h>
191c008a	22
ed800961 BM	23	DECLARE_GLOBAL_DATA_PTR;
ed800961 BM	24
ca4e4088 SG	25	static uint mrc_block_size(uint data_size)
	26	{
	27	uint mrc_size = sizeof(struct mrc_data_container) + data_size;
	28
	29	return ALIGN(mrc_size, MRC_DATA_ALIGN);
	30	}
	31
191c008a	32	static struct mrc_data_container *next_mrc_block(
bfa95c53	33	struct mrc_data_container *cache)
191c008a SG	34	{
191c008a SG	35	/* MRC data blocks are aligned within the region */
bfa95c53 BM	36	u8 region_ptr = (u8 )cache;
bfa95c53 BM	37
ca4e4088	38	region_ptr += mrc_block_size(cache->data_size);
bfa95c53	39
191c008a SG	40	return (struct mrc_data_container *)region_ptr;
	41	}
	42
	43	static int is_mrc_cache(struct mrc_data_container *cache)
	44	{
	45	return cache && (cache->signature == MRC_DATA_SIGNATURE);
	46	}
	47
4b9f6a66	48	struct mrc_data_container mrccache_find_current(struct mrc_region entry)
191c008a SG	49	{
	50	struct mrc_data_container cache, next;
	51	ulong base_addr, end_addr;
	52	uint id;
	53
4b9f6a66	54	base_addr = entry->base + entry->offset;
191c008a SG	55	end_addr = base_addr + entry->length;
	56	cache = NULL;
	57
	58	/* Search for the last filled entry in the region */
	59	for (id = 0, next = (struct mrc_data_container *)base_addr;
	60	is_mrc_cache(next);
	61	id++) {
	62	cache = next;
	63	next = next_mrc_block(next);
	64	if ((ulong)next >= end_addr)
	65	break;
	66	}
	67
	68	if (id-- == 0) {
	69	debug("%s: No valid MRC cache found.\n", __func__);
	70	return NULL;
	71	}
	72
	73	/* Verify checksum */
	74	if (cache->checksum != compute_ip_checksum(cache->data,
	75	cache->data_size)) {
	76	printf("%s: MRC cache checksum mismatch\n", __func__);
	77	return NULL;
	78	}
	79
	80	debug("%s: picked entry %u from cache block\n", __func__, id);
	81
	82	return cache;
	83	}
	84
	85	/**
	86	* find_next_mrc_cache() - get next cache entry
	87	*
0ad9b6a9 SG	88	* This moves to the next cache entry in the region, making sure it has enough
	89	* space to hold data of size @data_size.
	90	*
191c008a SG	91	* @entry: MRC cache flash area
191c008a SG	92	* @cache: Entry to start from
0ad9b6a9 SG	93	* @data_size: Required data size of the new entry. Note that we assume that
0ad9b6a9 SG	94	* all cache entries are the same size
191c008a SG	95	*
	96	* @return next cache entry if found, NULL if we got to the end
	97	*/
4b9f6a66	98	static struct mrc_data_container find_next_mrc_cache(struct mrc_region entry,
0ad9b6a9	99	struct mrc_data_container *prev, int data_size)
191c008a	100	{
0ad9b6a9	101	struct mrc_data_container *cache;
191c008a SG	102	ulong base_addr, end_addr;
191c008a SG	103
4b9f6a66	104	base_addr = entry->base + entry->offset;
191c008a SG	105	end_addr = base_addr + entry->length;
191c008a SG	106
0ad9b6a9 SG	107	/*
	108	* We assume that all cache entries are the same size, but let's use
	109	* data_size here for clarity.
	110	*/
	111	cache = next_mrc_block(prev);
	112	if ((ulong)cache + mrc_block_size(data_size) > end_addr) {
191c008a SG	113	/* Crossed the boundary */
	114	cache = NULL;
	115	debug("%s: no available entries found\n", __func__);
	116	} else {
	117	debug("%s: picked next entry from cache block at %p\n",
	118	__func__, cache);
	119	}
	120
	121	return cache;
	122	}
	123
fa6cc1de SG	124	/**
	125	* mrccache_update() - update the MRC cache with a new record
	126	*
	127	* This writes a new record to the end of the MRC cache region. If the new
	128	* record is the same as the latest record then the write is skipped
	129	*
	130	* @sf: SPI flash to write to
	131	* @entry: Position and size of MRC cache in SPI flash
	132	* @cur: Record to write
	133	* @return 0 if updated, -EEXIST if the record is the same as the latest
	134	* record, -EINVAL if the record is not valid, other error if SPI write failed
	135	*/
	136	static int mrccache_update(struct udevice sf, struct mrc_region entry,
	137	struct mrc_data_container *cur)
191c008a SG	138	{
	139	struct mrc_data_container *cache;
	140	ulong offset;
	141	ulong base_addr;
	142	int ret;
	143
079b38ba SG	144	if (!is_mrc_cache(cur)) {
079b38ba SG	145	debug("%s: Cache data not valid\n", __func__);
2fe66dbc	146	return -EINVAL;
079b38ba	147	}
2fe66dbc	148
191c008a	149	/* Find the last used block */
4b9f6a66	150	base_addr = entry->base + entry->offset;
191c008a SG	151	debug("Updating MRC cache data\n");
	152	cache = mrccache_find_current(entry);
	153	if (cache && (cache->data_size == cur->data_size) &&
	154	(!memcmp(cache, cur, cache->data_size + sizeof(*cur)))) {
	155	debug("MRC data in flash is up to date. No update\n");
	156	return -EEXIST;
	157	}
	158
	159	/* Move to the next block, which will be the first unused block */
	160	if (cache)
0ad9b6a9	161	cache = find_next_mrc_cache(entry, cache, cur->data_size);
191c008a SG	162
	163	/*
	164	* If we have got to the end, erase the entire mrc-cache area and start
	165	* again at block 0.
	166	*/
	167	if (!cache) {
	168	debug("Erasing the MRC cache region of %x bytes at %x\n",
	169	entry->length, entry->offset);
	170
ba457562	171	ret = spi_flash_erase_dm(sf, entry->offset, entry->length);
191c008a SG	172	if (ret) {
	173	debug("Failed to erase flash region\n");
	174	return ret;
	175	}
	176	cache = (struct mrc_data_container *)base_addr;
	177	}
	178
	179	/* Write the data out */
	180	offset = (ulong)cache - base_addr + entry->offset;
	181	debug("Write MRC cache update to flash at %lx\n", offset);
ba457562 SG	182	ret = spi_flash_write_dm(sf, offset, cur->data_size + sizeof(*cur),
ba457562 SG	183	cur);
191c008a SG	184	if (ret) {
191c008a SG	185	debug("Failed to write to SPI flash\n");
83f288f2	186	return log_msg_ret("Cannot update mrccache", ret);
191c008a SG	187	}
	188
	189	return 0;
	190	}
ed800961	191
515e8174	192	static void mrccache_setup(struct mrc_output mrc, void data)
ed800961	193	{
9a67994e	194	struct mrc_data_container *cache = data;
ed800961 BM	195	u16 checksum;
ed800961 BM	196
ed800961	197	cache->signature = MRC_DATA_SIGNATURE;
515e8174 SG	198	cache->data_size = mrc->len;
515e8174 SG	199	checksum = compute_ip_checksum(mrc->buf, cache->data_size);
ed800961 BM	200	debug("Saving %d bytes for MRC output data, checksum %04x\n",
	201	cache->data_size, checksum);
	202	cache->checksum = checksum;
	203	cache->reserved = 0;
515e8174	204	memcpy(cache->data, mrc->buf, cache->data_size);
ed800961	205
515e8174	206	mrc->cache = cache;
9a67994e SG	207	}
	208
	209	int mrccache_reserve(void)
	210	{
515e8174 SG	211	int i;
	212
	213	for (i = 0; i < MRC_TYPE_COUNT; i++) {
	214	struct mrc_output *mrc = &gd->arch.mrc[i];
9a67994e	215
515e8174 SG	216	if (!mrc->len)
515e8174 SG	217	continue;
ed800961	218
515e8174 SG	219	/* adjust stack pointer to store pure cache data plus header */
	220	gd->start_addr_sp -= (mrc->len + MRC_DATA_HEADER_SIZE);
	221	mrccache_setup(mrc, (void *)gd->start_addr_sp);
	222
	223	gd->start_addr_sp &= ~0xf;
	224	}
ed800961 BM	225
	226	return 0;
	227	}
	228
515e8174 SG	229	int mrccache_get_region(enum mrc_type_t type, struct udevice **devp,
515e8174 SG	230	struct mrc_region *entry)
ed800961	231	{
87f1084a SG	232	struct udevice *dev;
87f1084a SG	233	ofnode mrc_node;
506f2249 SG	234	ulong map_base;
	235	uint map_size;
	236	uint offset;
70c3c911	237	ofnode node;
4b9f6a66	238	u32 reg[2];
ed800961 BM	239	int ret;
ed800961 BM	240
87f1084a SG	241	/*
	242	* Find the flash chip within the SPI controller node. Avoid probing
	243	* the device here since it may put it into a strange state where the
	244	* memory map cannot be read.
	245	*/
	246	ret = uclass_find_first_device(UCLASS_SPI_FLASH, &dev);
70c3c911 SG	247	if (ret \|\| !dev) {
	248	/*
	249	* Fall back to searching the device tree since driver model
	250	* may not be ready yet (e.g. with FSPv1)
	251	*/
	252	node = ofnode_by_compatible(ofnode_null(), "jedec,spi-nor");
	253	if (!ofnode_valid(node))
	254	return log_msg_ret("Cannot find SPI flash\n", -ENOENT);
7149d380	255	ret = -ENODEV;
506f2249	256	} else {
70c3c911 SG	257	ret = dm_spi_get_mmap(dev, &map_base, &map_size, &offset);
	258	if (!ret)
	259	entry->base = map_base;
	260	node = dev_ofnode(dev);
	261	}
	262
	263	/*
	264	* At this point we have entry->base if ret == 0. If not, then we have
	265	* the node and can look for memory-map
	266	*/
	267	if (ret) {
	268	ret = ofnode_read_u32_array(node, "memory-map", reg, 2);
506f2249 SG	269	if (ret)
	270	return log_msg_ret("Cannot find memory map\n", ret);
	271	entry->base = reg[0];
	272	}
4b9f6a66	273
ed800961	274	/* Find the place where we put the MRC cache */
70c3c911 SG	275	mrc_node = ofnode_find_subnode(node, type == MRC_TYPE_NORMAL ?
70c3c911 SG	276	"rw-mrc-cache" : "rw-var-mrc-cache");
87f1084a SG	277	if (!ofnode_valid(mrc_node))
87f1084a SG	278	return log_msg_ret("Cannot find node", -EPERM);
ed800961	279
87f1084a SG	280	ret = ofnode_read_u32_array(mrc_node, "reg", reg, 2);
	281	if (ret)
	282	return log_msg_ret("Cannot find address", ret);
4b9f6a66 BM	283	entry->offset = reg[0];
4b9f6a66 BM	284	entry->length = reg[1];
ed800961	285
87f1084a SG	286	if (devp)
87f1084a SG	287	*devp = dev;
515e8174	288	debug("MRC cache type %d in '%s', offset %x, len %x, base %x\n",
70c3c911 SG	289	type, dev ? dev->name : ofnode_get_name(node), entry->offset,
70c3c911 SG	290	entry->length, entry->base);
ed800961 BM	291
	292	return 0;
	293	}
	294
515e8174	295	static int mrccache_save_type(enum mrc_type_t type)
ed800961	296	{
37a508f8	297	struct mrc_data_container *cache;
515e8174	298	struct mrc_output *mrc;
4b9f6a66	299	struct mrc_region entry;
ed800961 BM	300	struct udevice *sf;
	301	int ret;
	302
515e8174 SG	303	mrc = &gd->arch.mrc[type];
515e8174 SG	304	if (!mrc->len)
ed800961	305	return 0;
515e8174 SG	306	log_debug("Saving %#x bytes of MRC output data type %d to SPI flash\n",
	307	mrc->len, type);
	308	ret = mrccache_get_region(type, &sf, &entry);
87f1084a	309	if (ret)
83f288f2	310	return log_msg_ret("Cannot get region", ret);
87f1084a	311	ret = device_probe(sf);
ed800961	312	if (ret)
83f288f2	313	return log_msg_ret("Cannot probe device", ret);
515e8174 SG	314	cache = mrc->cache;
515e8174 SG	315
37a508f8	316	ret = mrccache_update(sf, &entry, cache);
83f288f2	317	if (!ret)
37a508f8	318	debug("Saved MRC data with checksum %04x\n", cache->checksum);
83f288f2	319	else if (ret == -EEXIST)
8b674418	320	debug("MRC data is the same as last time, skipping save\n");
ed800961	321
83f288f2	322	return 0;
ed800961	323	}
9a67994e	324
515e8174 SG	325	int mrccache_save(void)
	326	{
	327	int i;
	328
	329	for (i = 0; i < MRC_TYPE_COUNT; i++) {
	330	int ret;
	331
	332	ret = mrccache_save_type(i);
	333	if (ret)
	334	return ret;
	335	}
	336
	337	return 0;
	338	}
	339
9a67994e SG	340	int mrccache_spl_save(void)
9a67994e SG	341	{
515e8174 SG	342	int i;
	343
	344	for (i = 0; i < MRC_TYPE_COUNT; i++) {
	345	struct mrc_output *mrc = &gd->arch.mrc[i];
	346	void *data;
	347	int size;
	348
	349	size = mrc->len + MRC_DATA_HEADER_SIZE;
	350	data = malloc(size);
	351	if (!data)
	352	return log_msg_ret("Allocate MRC cache block", -ENOMEM);
	353	mrccache_setup(mrc, data);
	354	}
9a67994e SG	355
	356	return mrccache_save();
	357	}