[J-u-boot.git] / arch / x86 / cpu / start.S

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 *  U-Boot - x86 Startup Code
 *
 * This is always the first code to run from the U-Boot source. To spell it out:
 *
 * 1. When TPL (Tertiary Program Loader) is enabled, the boot flow is
 * TPL->SPL->U-Boot and this file is used for TPL. Then start_from_tpl.S is used
 * for SPL and start_from_spl.S is used for U-Boot proper.
 *
 * 2. When SPL (Secondary Program Loader) is enabled, but not TPL, the boot
 * flow is SPL->U-Boot and this file is used for SPL. Then start_from_spl.S is
 * used for U-Boot proper.
 *
 * 3. When neither TPL nor SPL is used, this file is used for U-Boot proper.
 *
 * (C) Copyright 2008-2011
 * Graeme Russ, <[email protected]>
 *
 * (C) Copyright 2002
 * Daniel Engström, Omicron Ceti AB, <[email protected]>
 */

#include <config.h>
#include <asm/post.h>
#include <asm/processor.h>
#include <asm/processor-flags.h>
#include <generated/generic-asm-offsets.h>
#include <generated/asm-offsets.h>
#include <linux/linkage.h>

.section .text.start
.code32
.globl _start
.type _start, @function
.globl _x86boot_start
_x86boot_start:
	/*
	 * This is the fail-safe 32-bit bootstrap entry point.
	 *
	 * This code is used when booting from another boot loader like
	 * coreboot or EFI. So we repeat some of the same init found in
	 * start16.
	 */
	cli
	cld

	/* Turn off cache (this might require a 486-class CPU) */
	movl	%cr0, %eax
	orl	$(X86_CR0_NW | X86_CR0_CD), %eax
	movl	%eax, %cr0
	wbinvd

	/*
	 * Zero the BIST (Built-In Self Test) value since we don't have it.
	 * It must be 0 or the previous loader would have reported an error.
	 */
	movl	$0, %ebp

	jmp	1f

	/* Add a way for tools to discover the _start entry point */
	.align	4
	.long	0x12345678
_start:
	/* This is the 32-bit cold-reset entry point, coming from start16 */

	/* Save BIST */
	movl	%eax, %ebp
1:

	/* Save table pointer */
	movl	%ecx, %esi

#ifdef CONFIG_X86_LOAD_FROM_32_BIT
	lgdt	gdt_ptr2
#endif

	/* Load the segment registers to match the GDT loaded in start16.S */
	movl	$(X86_GDT_ENTRY_32BIT_DS * X86_GDT_ENTRY_SIZE), %eax
	movw	%ax, %fs
	movw	%ax, %ds
	movw	%ax, %gs
	movw	%ax, %es
	movw	%ax, %ss

	/* Clear the interrupt vectors */
	lidt	blank_idt_ptr

#ifdef CONFIG_USE_EARLY_BOARD_INIT
	/*
	 * Critical early platform init - generally not used, we prefer init
	 * to happen later when we have a console, in case something goes
	 * wrong.
	 */
	jmp	early_board_init
.globl early_board_init_ret
early_board_init_ret:
#endif

	post_code(POST_START)

	/* Initialise Cache-As-RAM */
	jmp	car_init
.globl car_init_ret
car_init_ret:
#ifdef CONFIG_USE_CAR
	/*
	 * We now have CONFIG_SYS_CAR_SIZE bytes of Cache-As-RAM (or SRAM,
	 * or fully initialised SDRAM - we really don't care which)
	 * starting at CONFIG_SYS_CAR_ADDR to be used as a temporary stack
	 * and early malloc() area. The MRC requires some space at the top.
	 *
	 * Stack grows down from top of CAR. We have:
	 *
	 * top-> CONFIG_SYS_CAR_ADDR + CONFIG_SYS_CAR_SIZE
	 *	MRC area
	 *	global_data with x86 global descriptor table
	 *	early malloc area
	 *	stack
	 * bottom-> CONFIG_SYS_CAR_ADDR
	 */
	movl	$(CONFIG_SYS_CAR_ADDR + CONFIG_SYS_CAR_SIZE - 4), %esp
#ifdef CONFIG_DCACHE_RAM_MRC_VAR_SIZE
	subl	$CONFIG_DCACHE_RAM_MRC_VAR_SIZE, %esp
#endif
#else
	/*
	 * Instructions for FSP1, but not FSP2:
	 * U-Boot enters here twice. For the first time it comes from
	 * car_init_done() with esp points to a temporary stack and esi
	 * set to zero. For the second time it comes from fsp_init_done()
	 * with esi holding the HOB list address returned by the FSP.
	 */
#endif
	/* Set up global data */
	mov	%esp, %eax
	call	board_init_f_alloc_reserve
	mov	%eax, %esp
	call	board_init_f_init_reserve

#ifdef CONFIG_DEBUG_UART
	call	debug_uart_init
#endif

	/* Get address of global_data */
	mov	%fs:0, %edx
#if defined(CONFIG_USE_HOB) && !defined(CONFIG_USE_CAR)
	/* Store the HOB list if we have one */
	test	%esi, %esi
	jz	skip_hob
	movl	%esi, GD_HOB_LIST(%edx)

#ifdef CONFIG_HAVE_FSP
	/*
	 * After fsp_init() returns, the stack has already been switched to a
	 * place within system memory as defined by CONFIG_FSP_TEMP_RAM_ADDR.
	 * Enlarge the size of malloc() pool before relocation since we have
	 * plenty of memory now.
	 */
	subl	$CONFIG_FSP_SYS_MALLOC_F_LEN, %esp
	movl	%esp, GD_MALLOC_BASE(%edx)
#endif
skip_hob:
#else
	/* Store table pointer */
	movl	%esi, GD_TABLE(%edx)
#endif
	/* Store BIST */
	movl	%ebp, GD_BIST(%edx)

	/* Set parameter to board_init_f() to boot flags */
	post_code(POST_START_DONE)
	xorl	%eax, %eax

	/* Enter, U-Boot! */
	call	board_init_f

	/* indicate (lack of) progress */
	movw	$0x85, %ax
	jmp	die

.globl board_init_f_r_trampoline
.type board_init_f_r_trampoline, @function
board_init_f_r_trampoline:
	/*
	 * SDRAM has been initialised, U-Boot code has been copied into
	 * RAM, BSS has been cleared and relocation adjustments have been
	 * made. It is now time to jump into the in-RAM copy of U-Boot
	 *
	 * %eax = Address of top of new stack
	 */

	/* Stack grows down from top of SDRAM */
	movl	%eax, %esp

	/* See if we need to disable CAR */
	call	car_uninit

	/* Re-enter U-Boot by calling board_init_f_r() */
	call	board_init_f_r

#ifdef CONFIG_TPL
.globl jump_to_spl
.type jump_to_spl, @function
jump_to_spl:
	/* Reset stack to the top of CAR space */
	movl	$(CONFIG_SYS_CAR_ADDR + CONFIG_SYS_CAR_SIZE - 4), %esp
#ifdef CONFIG_DCACHE_RAM_MRC_VAR_SIZE
	subl	$CONFIG_DCACHE_RAM_MRC_VAR_SIZE, %esp
#endif

	jmp	*%eax
#endif

die:
	hlt
	jmp	die
	hlt

WEAK(car_uninit)
	ret
ENDPROC(car_uninit)

blank_idt_ptr:
	.word	0		/* limit */
	.long	0		/* base */

	.p2align	2	/* force 4-byte alignment */

	/* Add a multiboot header so U-Boot can be loaded by GRUB2 */
multiboot_header:
	/* magic */
	.long	0x1badb002
	/* flags */
	.long	(1 << 16)
	/* checksum */
	.long	-0x1BADB002 - (1 << 16)
	/* header addr */
	.long	multiboot_header - _x86boot_start + CONFIG_SYS_TEXT_BASE
	/* load addr */
	.long	CONFIG_SYS_TEXT_BASE
	/* load end addr */
	.long	0
	/* bss end addr */
	.long	0
	/* entry addr */
	.long	CONFIG_SYS_TEXT_BASE

#ifdef CONFIG_X86_LOAD_FROM_32_BIT
	/*
	 * The following Global Descriptor Table is just enough to get us into
	 * 'Flat Protected Mode' - It will be discarded as soon as the final
	 * GDT is setup in a safe location in RAM
	 */
gdt_ptr2:
	.word	0x1f		/* limit (31 bytes = 4 GDT entries - 1) */
	.long	gdt_rom2	/* base */

	/* Some CPUs are picky about GDT alignment... */
	.align	16
.globl gdt_rom2
gdt_rom2:
	/*
	 * The GDT table ...
	 *
	 *	 Selector	Type
	 *	 0x00		NULL
	 *	 0x08		Unused
	 *	 0x10		32bit code
	 *	 0x18		32bit data/stack
	 */
	/* The NULL Desciptor - Mandatory */
	.word	0x0000		/* limit_low */
	.word	0x0000		/* base_low */
	.byte	0x00		/* base_middle */
	.byte	0x00		/* access */
	.byte	0x00		/* flags + limit_high */
	.byte	0x00		/* base_high */

	/* Unused Desciptor - (matches Linux) */
	.word	0x0000		/* limit_low */
	.word	0x0000		/* base_low */
	.byte	0x00		/* base_middle */
	.byte	0x00		/* access */
	.byte	0x00		/* flags + limit_high */
	.byte	0x00		/* base_high */

	/*
	 * The Code Segment Descriptor:
	 * - Base   = 0x00000000
	 * - Size   = 4GB
	 * - Access = Present, Ring 0, Exec (Code), Readable
	 * - Flags  = 4kB Granularity, 32-bit
	 */
	.word	0xffff		/* limit_low */
	.word	0x0000		/* base_low */
	.byte	0x00		/* base_middle */
	.byte	0x9b		/* access */
	.byte	0xcf		/* flags + limit_high */
	.byte	0x00		/* base_high */

	/*
	 * The Data Segment Descriptor:
	 * - Base   = 0x00000000
	 * - Size   = 4GB
	 * - Access = Present, Ring 0, Non-Exec (Data), Writable
	 * - Flags  = 4kB Granularity, 32-bit
	 */
	.word	0xffff		/* limit_low */
	.word	0x0000		/* base_low */
	.byte	0x00		/* base_middle */
	.byte	0x93		/* access */
	.byte	0xcf		/* flags + limit_high */
	.byte	0x00		/* base_high */
#endif
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
2262cfee	2	/*
fe0c33a5	3	* U-Boot - x86 Startup Code
2262cfee	4	*
08deb6d3 SG	5	* This is always the first code to run from the U-Boot source. To spell it out:
	6	*
	7	* 1. When TPL (Tertiary Program Loader) is enabled, the boot flow is
	8	* TPL->SPL->U-Boot and this file is used for TPL. Then start_from_tpl.S is used
	9	* for SPL and start_from_spl.S is used for U-Boot proper.
	10	*
	11	* 2. When SPL (Secondary Program Loader) is enabled, but not TPL, the boot
	12	* flow is SPL->U-Boot and this file is used for SPL. Then start_from_spl.S is
	13	* used for U-Boot proper.
	14	*
	15	* 3. When neither TPL nor SPL is used, this file is used for U-Boot proper.
	16	*
dbf7115a GR	17	* (C) Copyright 2008-2011
	18	* Graeme Russ, <[email protected]>
	19	*
	20	* (C) Copyright 2002
fa82f871	21	* Daniel Engström, Omicron Ceti AB, <[email protected]>
2262cfee WD	22	*/
2262cfee WD	23
2262cfee	24	#include <config.h>
d1cd0459	25	#include <asm/post.h>
109ad143	26	#include <asm/processor.h>
0c24c9cc	27	#include <asm/processor-flags.h>
9e6c572f	28	#include <generated/generic-asm-offsets.h>
fe0c33a5	29	#include <generated/asm-offsets.h>
3d2be800	30	#include <linux/linkage.h>
2262cfee	31
7e21fbca	32	.section .text.start
2262cfee WD	33	.code32
2262cfee WD	34	.globl _start
8bde7f77	35	.type _start, @function
fea25720 GR	36	.globl _x86boot_start
fea25720 GR	37	_x86boot_start:
077e1958	38	/*
da3a95d6 SG	39	* This is the fail-safe 32-bit bootstrap entry point.
	40	*
	41	* This code is used when booting from another boot loader like
	42	* coreboot or EFI. So we repeat some of the same init found in
	43	* start16.
077e1958 GR	44	*/
	45	cli
	46	cld
	47
2f0e0cd2	48	/* Turn off cache (this might require a 486-class CPU) */
077e1958	49	movl %cr0, %eax
0c24c9cc	50	orl $(X86_CR0_NW \| X86_CR0_CD), %eax
077e1958	51	movl %eax, %cr0
fa97ca16	52	wbinvd
077e1958	53
42fde305 SG	54	/*
	55	* Zero the BIST (Built-In Self Test) value since we don't have it.
	56	* It must be 0 or the previous loader would have reported an error.
	57	*/
	58	movl $0, %ebp
	59
91d82a29	60	jmp 1f
83ec7de3 SG	61
	62	/* Add a way for tools to discover the _start entry point */
	63	.align 4
	64	.long 0x12345678
8bde7f77	65	_start:
8ad01ce3	66	/* This is the 32-bit cold-reset entry point, coming from start16 */
42fde305	67
f67cd51e SG	68	/* Save BIST */
f67cd51e SG	69	movl %eax, %ebp
42fde305 SG	70	1:
	71
	72	/* Save table pointer */
	73	movl %ecx, %esi
077e1958	74
446d4e04	75	#ifdef CONFIG_X86_LOAD_FROM_32_BIT
e5aa8a9b SG	76	lgdt gdt_ptr2
	77	#endif
	78
a0df9249	79	/* Load the segment registers to match the GDT loaded in start16.S */
109ad143	80	movl $(X86_GDT_ENTRY_32BIT_DS * X86_GDT_ENTRY_SIZE), %eax
8ffb2e8f GR	81	movw %ax, %fs
	82	movw %ax, %ds
	83	movw %ax, %gs
	84	movw %ax, %es
	85	movw %ax, %ss
8bde7f77	86
16263087	87	/* Clear the interrupt vectors */
077e1958 GR	88	lidt blank_idt_ptr
077e1958 GR	89
1d01d0c2	90	#ifdef CONFIG_USE_EARLY_BOARD_INIT
da3a95d6 SG	91	/*
	92	* Critical early platform init - generally not used, we prefer init
	93	* to happen later when we have a console, in case something goes
	94	* wrong.
	95	*/
2262cfee	96	jmp early_board_init
88fa0a6e	97	.globl early_board_init_ret
2262cfee	98	early_board_init_ret:
1d01d0c2 AS	99	#endif
1d01d0c2 AS	100
d1cd0459	101	post_code(POST_START)
8bde7f77	102
ed4cba79 GR	103	/* Initialise Cache-As-RAM */
	104	jmp car_init
	105	.globl car_init_ret
	106	car_init_ret:
6172e94c	107	#ifdef CONFIG_USE_CAR
ed4cba79 GR	108	/*
	109	* We now have CONFIG_SYS_CAR_SIZE bytes of Cache-As-RAM (or SRAM,
	110	* or fully initialised SDRAM - we really don't care which)
	111	* starting at CONFIG_SYS_CAR_ADDR to be used as a temporary stack
da3a95d6	112	* and early malloc() area. The MRC requires some space at the top.
76f90f30 SG	113	*
	114	* Stack grows down from top of CAR. We have:
	115	*
	116	* top-> CONFIG_SYS_CAR_ADDR + CONFIG_SYS_CAR_SIZE
65dd74a6	117	* MRC area
f0c7d9c7	118	* global_data with x86 global descriptor table
76f90f30 SG	119	* early malloc area
	120	* stack
	121	* bottom-> CONFIG_SYS_CAR_ADDR
ed4cba79	122	*/
65dd74a6 SG	123	movl $(CONFIG_SYS_CAR_ADDR + CONFIG_SYS_CAR_SIZE - 4), %esp
	124	#ifdef CONFIG_DCACHE_RAM_MRC_VAR_SIZE
	125	subl $CONFIG_DCACHE_RAM_MRC_VAR_SIZE, %esp
	126	#endif
bceb9f0f BM	127	#else
bceb9f0f BM	128	/*
538c9b3d	129	* Instructions for FSP1, but not FSP2:
48aa6c26 BM	130	* U-Boot enters here twice. For the first time it comes from
	131	* car_init_done() with esp points to a temporary stack and esi
	132	* set to zero. For the second time it comes from fsp_init_done()
	133	* with esi holding the HOB list address returned by the FSP.
bceb9f0f BM	134	*/
bceb9f0f BM	135	#endif
f0c7d9c7 SG	136	/* Set up global data */
f0c7d9c7 SG	137	mov %esp, %eax
ecc30663	138	call board_init_f_alloc_reserve
f0c7d9c7	139	mov %eax, %esp
ecc30663	140	call board_init_f_init_reserve
8d61625d	141
60994a02 SG	142	#ifdef CONFIG_DEBUG_UART
	143	call debug_uart_init
	144	#endif
bbbe55f6	145
f0c7d9c7 SG	146	/* Get address of global_data */
f0c7d9c7 SG	147	mov %fs:0, %edx
6172e94c	148	#if defined(CONFIG_USE_HOB) && !defined(CONFIG_USE_CAR)
f0c7d9c7	149	/* Store the HOB list if we have one */
aefaff8e BM	150	test %esi, %esi
aefaff8e BM	151	jz skip_hob
f0c7d9c7	152	movl %esi, GD_HOB_LIST(%edx)
bceb9f0f	153
544293f8	154	#ifdef CONFIG_HAVE_FSP
57b10f59 BM	155	/*
	156	* After fsp_init() returns, the stack has already been switched to a
	157	* place within system memory as defined by CONFIG_FSP_TEMP_RAM_ADDR.
	158	* Enlarge the size of malloc() pool before relocation since we have
	159	* plenty of memory now.
	160	*/
	161	subl $CONFIG_FSP_SYS_MALLOC_F_LEN, %esp
	162	movl %esp, GD_MALLOC_BASE(%edx)
544293f8	163	#endif
aefaff8e	164	skip_hob:
42fde305 SG	165	#else
42fde305 SG	166	/* Store table pointer */
f0c7d9c7	167	movl %esi, GD_TABLE(%edx)
aefaff8e	168	#endif
f0c7d9c7 SG	169	/* Store BIST */
f0c7d9c7 SG	170	movl %ebp, GD_BIST(%edx)
9e6c572f	171
96cd6642	172	/* Set parameter to board_init_f() to boot flags */
d1cd0459	173	post_code(POST_START_DONE)
dbf7115a	174	xorl %eax, %eax
161b3589	175
da3a95d6	176	/* Enter, U-Boot! */
dbf7115a	177	call board_init_f
2262cfee WD	178
2262cfee WD	179	/* indicate (lack of) progress */
8bde7f77	180	movw $0x85, %ax
fb002908 GR	181	jmp die
fb002908 GR	182
f48dd6fc GR	183	.globl board_init_f_r_trampoline
	184	.type board_init_f_r_trampoline, @function
	185	board_init_f_r_trampoline:
fb002908 GR	186	/*
	187	* SDRAM has been initialised, U-Boot code has been copied into
	188	* RAM, BSS has been cleared and relocation adjustments have been
	189	* made. It is now time to jump into the in-RAM copy of U-Boot
	190	*
f48dd6fc	191	* %eax = Address of top of new stack
fb002908 GR	192	*/
fb002908 GR	193
8d61625d	194	/* Stack grows down from top of SDRAM */
fb002908 GR	195	movl %eax, %esp
fb002908 GR	196
f0c7d9c7	197	/* See if we need to disable CAR */
801d70ce	198	call car_uninit
3d2be800	199
da3a95d6	200	/* Re-enter U-Boot by calling board_init_f_r() */
f48dd6fc	201	call board_init_f_r
fb002908	202
49dffb7a SG	203	#ifdef CONFIG_TPL
	204	.globl jump_to_spl
	205	.type jump_to_spl, @function
	206	jump_to_spl:
	207	/* Reset stack to the top of CAR space */
	208	movl $(CONFIG_SYS_CAR_ADDR + CONFIG_SYS_CAR_SIZE - 4), %esp
	209	#ifdef CONFIG_DCACHE_RAM_MRC_VAR_SIZE
	210	subl $CONFIG_DCACHE_RAM_MRC_VAR_SIZE, %esp
	211	#endif
	212
	213	jmp *%eax
	214	#endif
	215
2f0e0cd2 GR	216	die:
2f0e0cd2 GR	217	hlt
2262cfee	218	jmp die
8bde7f77	219	hlt
077e1958	220
3d2be800 BM	221	WEAK(car_uninit)
	222	ret
	223	ENDPROC(car_uninit)
	224
077e1958 GR	225	blank_idt_ptr:
	226	.word 0 /* limit */
	227	.long 0 /* base */
a206cc23 GR	228
	229	.p2align 2 /* force 4-byte alignment */
	230
da3a95d6	231	/* Add a multiboot header so U-Boot can be loaded by GRUB2 */
a206cc23 GR	232	multiboot_header:
a206cc23 GR	233	/* magic */
da3a95d6	234	.long 0x1badb002
a206cc23 GR	235	/* flags */
	236	.long (1 << 16)
	237	/* checksum */
	238	.long -0x1BADB002 - (1 << 16)
	239	/* header addr */
	240	.long multiboot_header - _x86boot_start + CONFIG_SYS_TEXT_BASE
	241	/* load addr */
	242	.long CONFIG_SYS_TEXT_BASE
	243	/* load end addr */
	244	.long 0
	245	/* bss end addr */
	246	.long 0
	247	/* entry addr */
	248	.long CONFIG_SYS_TEXT_BASE
e5aa8a9b	249
446d4e04	250	#ifdef CONFIG_X86_LOAD_FROM_32_BIT
e5aa8a9b SG	251	/*
	252	* The following Global Descriptor Table is just enough to get us into
	253	* 'Flat Protected Mode' - It will be discarded as soon as the final
	254	* GDT is setup in a safe location in RAM
	255	*/
	256	gdt_ptr2:
	257	.word 0x1f /* limit (31 bytes = 4 GDT entries - 1) */
	258	.long gdt_rom2 /* base */
	259
	260	/* Some CPUs are picky about GDT alignment... */
	261	.align 16
	262	.globl gdt_rom2
	263	gdt_rom2:
	264	/*
	265	* The GDT table ...
	266	*
	267	* Selector Type
	268	* 0x00 NULL
	269	* 0x08 Unused
	270	* 0x10 32bit code
	271	* 0x18 32bit data/stack
	272	*/
	273	/* The NULL Desciptor - Mandatory */
	274	.word 0x0000 /* limit_low */
	275	.word 0x0000 /* base_low */
	276	.byte 0x00 /* base_middle */
	277	.byte 0x00 /* access */
	278	.byte 0x00 /* flags + limit_high */
	279	.byte 0x00 /* base_high */
	280
	281	/* Unused Desciptor - (matches Linux) */
	282	.word 0x0000 /* limit_low */
	283	.word 0x0000 /* base_low */
	284	.byte 0x00 /* base_middle */
	285	.byte 0x00 /* access */
	286	.byte 0x00 /* flags + limit_high */
	287	.byte 0x00 /* base_high */
	288
	289	/*
	290	* The Code Segment Descriptor:
	291	* - Base = 0x00000000
	292	* - Size = 4GB
	293	* - Access = Present, Ring 0, Exec (Code), Readable
	294	* - Flags = 4kB Granularity, 32-bit
	295	*/
	296	.word 0xffff /* limit_low */
	297	.word 0x0000 /* base_low */
	298	.byte 0x00 /* base_middle */
	299	.byte 0x9b /* access */
	300	.byte 0xcf /* flags + limit_high */
	301	.byte 0x00 /* base_high */
	302
	303	/*
	304	* The Data Segment Descriptor:
	305	* - Base = 0x00000000
	306	* - Size = 4GB
	307	* - Access = Present, Ring 0, Non-Exec (Data), Writable
	308	* - Flags = 4kB Granularity, 32-bit
	309	*/
	310	.word 0xffff /* limit_low */
	311	.word 0x0000 /* base_low */
	312	.byte 0x00 /* base_middle */
	313	.byte 0x93 /* access */
	314	.byte 0xcf /* flags + limit_high */
315	.byte 0x00 /* base_high */
316	#endif