[J-u-boot.git] / arch / x86 / cpu / call32.S

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * (C) Copyright 2015 Google, Inc
 * Written by Simon Glass <[email protected]>
 */

#include <asm/msr-index.h>
#include <asm/processor-flags.h>

	/*
	 * rdi - 32-bit code segment selector
	 * rsi - target address
	 * rdx - table address (0 if none)
	 */
.code64
.globl cpu_call32
cpu_call32:
	cli

	/* Save table pointer */
	mov	%edx, %ebx

	/*
	 * Debugging option, this outputs characters to the console UART
	 * mov	$0x3f8,%edx
	 * mov	$'a',%al
	 * out	%al,(%dx)
	 */

	pushf
	push	%rdi	/* 32-bit code segment */
	lea	compat(%rip), %rax
	push	%rax
	retfq
.code32
compat:
	/*
	 * We are now in compatibility mode with a default operand size of
	 * 32 bits. First disable paging.
	 */
	movl	%cr0, %eax
	andl	$~X86_CR0_PG, %eax
	movl	%eax, %cr0

	/* Invalidate TLB */
	xorl	%eax, %eax
	movl	%eax, %cr3

	/* Disable Long mode in EFER (Extended Feature Enable Register) */
	movl	$MSR_EFER, %ecx
	rdmsr
	btr	$_EFER_LME, %eax
	wrmsr

	/* Set up table pointer for _x86boot_start */
	mov	%ebx, %ecx

	/* Jump to the required target */
	pushl	%edi	/* 32-bit code segment */
	pushl	%esi	/* 32-bit target address */
	retfl
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
6f92ed8f SG	2	/*
	3	* (C) Copyright 2015 Google, Inc
	4	* Written by Simon Glass <[email protected]>
6f92ed8f SG	5	*/
6f92ed8f SG	6
6f92ed8f SG	7	#include <asm/msr-index.h>
	8	#include <asm/processor-flags.h>
	9
	10	/*
	11	* rdi - 32-bit code segment selector
	12	* rsi - target address
	13	* rdx - table address (0 if none)
	14	*/
	15	.code64
	16	.globl cpu_call32
	17	cpu_call32:
	18	cli
	19
	20	/* Save table pointer */
	21	mov %edx, %ebx
	22
	23	/*
	24	* Debugging option, this outputs characters to the console UART
	25	* mov $0x3f8,%edx
	26	* mov $'a',%al
	27	* out %al,(%dx)
	28	*/
	29
	30	pushf
	31	push %rdi /* 32-bit code segment */
	32	lea compat(%rip), %rax
	33	push %rax
94018591	34	retfq
6f92ed8f SG	35	.code32
	36	compat:
	37	/*
	38	* We are now in compatibility mode with a default operand size of
	39	* 32 bits. First disable paging.
	40	*/
	41	movl %cr0, %eax
	42	andl $~X86_CR0_PG, %eax
	43	movl %eax, %cr0
	44
	45	/* Invalidate TLB */
	46	xorl %eax, %eax
	47	movl %eax, %cr3
	48
	49	/* Disable Long mode in EFER (Extended Feature Enable Register) */
	50	movl $MSR_EFER, %ecx
	51	rdmsr
	52	btr $_EFER_LME, %eax
	53	wrmsr
	54
	55	/* Set up table pointer for _x86boot_start */
	56	mov %ebx, %ecx
	57
	58	/* Jump to the required target */
	59	pushl %edi /* 32-bit code segment */
	60	pushl %esi /* 32-bit target address */
94018591	61	retfl