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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
6c3e61de SB |
2 | /* |
3 | * Copyright (C) 2013 Soren Brinkmann <[email protected]> | |
4 | * Copyright (C) 2013 Xilinx, Inc. All rights reserved. | |
6c3e61de | 5 | */ |
781745bd | 6 | #include <clk.h> |
6c3e61de | 7 | #include <common.h> |
781745bd | 8 | #include <dm.h> |
691d719d | 9 | #include <init.h> |
336d4615 | 10 | #include <malloc.h> |
6c3e61de | 11 | #include <asm/arch/clk.h> |
401d1c4f | 12 | #include <asm/global_data.h> |
6c3e61de | 13 | |
6c3e61de SB |
14 | DECLARE_GLOBAL_DATA_PTR; |
15 | ||
e18c0f66 SH |
16 | static const char * const clk_names[clk_max] = { |
17 | "armpll", "ddrpll", "iopll", | |
18 | "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", | |
19 | "ddr2x", "ddr3x", "dci", | |
20 | "lqspi", "smc", "pcap", "gem0", "gem1", | |
21 | "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", | |
22 | "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma", | |
23 | "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper", | |
24 | "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper", | |
25 | "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", | |
26 | "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", | |
27 | "smc_aper", "swdt", "dbg_trc", "dbg_apb" | |
28 | }; | |
29 | ||
6c3e61de | 30 | /** |
781745bd | 31 | * set_cpu_clk_info() - Setup clock information |
6c3e61de SB |
32 | * |
33 | * This function is called from common code after relocation and sets up the | |
781745bd | 34 | * clock information. |
6c3e61de SB |
35 | */ |
36 | int set_cpu_clk_info(void) | |
37 | { | |
781745bd SH |
38 | struct clk clk; |
39 | struct udevice *dev; | |
40 | ulong rate; | |
41 | int i, ret; | |
42 | ||
43 | ret = uclass_get_device_by_driver(UCLASS_CLK, | |
65e25bea | 44 | DM_DRIVER_GET(zynq_clk), &dev); |
781745bd SH |
45 | if (ret) |
46 | return ret; | |
47 | ||
48 | for (i = 0; i < 2; i++) { | |
49 | clk.id = i ? ddr3x_clk : cpu_6or4x_clk; | |
50 | ret = clk_request(dev, &clk); | |
51 | if (ret < 0) | |
52 | return ret; | |
53 | ||
54 | rate = clk_get_rate(&clk) / 1000000; | |
55 | if (i) | |
56 | gd->bd->bi_ddr_freq = rate; | |
57 | else | |
58 | gd->bd->bi_arm_freq = rate; | |
59 | ||
60 | clk_free(&clk); | |
61 | } | |
96a5d4dc MS |
62 | gd->bd->bi_dsp_freq = 0; |
63 | ||
6c3e61de SB |
64 | return 0; |
65 | } | |
66 | ||
d6c9bbaa SB |
67 | /** |
68 | * soc_clk_dump() - Print clock frequencies | |
69 | * Returns zero on success | |
70 | * | |
71 | * Implementation for the clk dump command. | |
72 | */ | |
73 | int soc_clk_dump(void) | |
74 | { | |
781745bd SH |
75 | struct udevice *dev; |
76 | int i, ret; | |
77 | ||
78 | ret = uclass_get_device_by_driver(UCLASS_CLK, | |
65e25bea | 79 | DM_DRIVER_GET(zynq_clk), &dev); |
781745bd SH |
80 | if (ret) |
81 | return ret; | |
d6c9bbaa SB |
82 | |
83 | printf("clk\t\tfrequency\n"); | |
84 | for (i = 0; i < clk_max; i++) { | |
f96fccba | 85 | const char *name = clk_names[i]; |
781745bd SH |
86 | if (name) { |
87 | struct clk clk; | |
88 | unsigned long rate; | |
89 | ||
90 | clk.id = i; | |
91 | ret = clk_request(dev, &clk); | |
92 | if (ret < 0) | |
93 | return ret; | |
94 | ||
95 | rate = clk_get_rate(&clk); | |
96 | ||
97 | clk_free(&clk); | |
98 | ||
7ad6d9a4 MS |
99 | if ((rate == (unsigned long)-ENOSYS) || |
100 | (rate == (unsigned long)-ENXIO)) | |
781745bd SH |
101 | printf("%10s%20s\n", name, "unknown"); |
102 | else | |
103 | printf("%10s%20lu\n", name, rate); | |
104 | } | |
d6c9bbaa SB |
105 | } |
106 | ||
107 | return 0; | |
108 | } |