[J-u-boot.git] / arch / arm / mach-rmobile / memmap-gen3.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Renesas RCar Gen3 memory map tables
 *
 * Copyright (C) 2017 Marek Vasut <[email protected]>
 */

#include <common.h>
#include <cpu_func.h>
#include <asm/armv8/mmu.h>
#include <asm/global_data.h>

#define GEN3_NR_REGIONS 16

static struct mm_region gen3_mem_map[GEN3_NR_REGIONS] = {
	{
		.virt = 0x0UL,
		.phys = 0x0UL,
		.size = 0x40000000UL,
		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
			 PTE_BLOCK_NON_SHARE |
			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
	}, {
		.virt = 0x40000000UL,
		.phys = 0x40000000UL,
		.size = 0x03F00000UL,
		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
			 PTE_BLOCK_INNER_SHARE
	}, {
		.virt = 0x47E00000UL,
		.phys = 0x47E00000UL,
		.size = 0x78200000UL,
		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
			 PTE_BLOCK_INNER_SHARE
	}, {
		.virt = 0xc0000000UL,
		.phys = 0xc0000000UL,
		.size = 0x40000000UL,
		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
			 PTE_BLOCK_NON_SHARE |
			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
	}, {
		.virt = 0x100000000UL,
		.phys = 0x100000000UL,
		.size = 0xf00000000UL,
		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
			 PTE_BLOCK_INNER_SHARE
	}, {
		/* List terminator */
		0,
	}
};

struct mm_region *mem_map = gen3_mem_map;

DECLARE_GLOBAL_DATA_PTR;

void enable_caches(void)
{
	u64 start, size;
	int bank, i = 0;

	/* Create map for RPC access */
	gen3_mem_map[i].virt = 0x0ULL;
	gen3_mem_map[i].phys = 0x0ULL;
	gen3_mem_map[i].size = 0x40000000ULL;
	gen3_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
				PTE_BLOCK_NON_SHARE |
				PTE_BLOCK_PXN | PTE_BLOCK_UXN;
	i++;

	/* Generate entires for DRAM in 32bit address space */
	for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
		start = gd->bd->bi_dram[bank].start;
		size = gd->bd->bi_dram[bank].size;

		/* Skip empty DRAM banks */
		if (!size)
			continue;

		/* Skip DRAM above 4 GiB */
		if (start >> 32ULL)
			continue;

		/* Mark memory reserved by ATF as cacheable too. */
		if (start == 0x48000000) {
			/* Unmark protection area (0x43F00000 to 0x47DFFFFF) */
			gen3_mem_map[i].virt = 0x40000000ULL;
			gen3_mem_map[i].phys = 0x40000000ULL;
			gen3_mem_map[i].size = 0x03F00000ULL;
			gen3_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
						PTE_BLOCK_INNER_SHARE;
			i++;

			start = 0x47E00000ULL;
			size += 0x00200000ULL;
		}

		gen3_mem_map[i].virt = start;
		gen3_mem_map[i].phys = start;
		gen3_mem_map[i].size = size;
		gen3_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
					PTE_BLOCK_INNER_SHARE;
		i++;
	}

	/* Create map for register access */
	gen3_mem_map[i].virt = 0xc0000000ULL;
	gen3_mem_map[i].phys = 0xc0000000ULL;
	gen3_mem_map[i].size = 0x40000000ULL;
	gen3_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
				PTE_BLOCK_NON_SHARE |
				PTE_BLOCK_PXN | PTE_BLOCK_UXN;
	i++;

	/* Generate entires for DRAM in 64bit address space */
	for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
		start = gd->bd->bi_dram[bank].start;
		size = gd->bd->bi_dram[bank].size;

		/* Skip empty DRAM banks */
		if (!size)
			continue;

		/* Skip DRAM below 4 GiB */
		if (!(start >> 32ULL))
			continue;

		gen3_mem_map[i].virt = start;
		gen3_mem_map[i].phys = start;
		gen3_mem_map[i].size = size;
		gen3_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
					PTE_BLOCK_INNER_SHARE;
		i++;
	}

	/* Zero out the remaining regions. */
	for (; i < GEN3_NR_REGIONS; i++) {
		gen3_mem_map[i].virt = 0;
		gen3_mem_map[i].phys = 0;
		gen3_mem_map[i].size = 0;
		gen3_mem_map[i].attrs = 0;
	}

	if (!icache_status())
		icache_enable();

	dcache_enable();
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
a523af69 MV	2	/*
	3	* Renesas RCar Gen3 memory map tables
	4	*
	5	* Copyright (C) 2017 Marek Vasut <[email protected]>
a523af69 MV	6	*/
	7
	8	#include <common.h>
9edefc27	9	#include <cpu_func.h>
a523af69	10	#include <asm/armv8/mmu.h>
401d1c4f	11	#include <asm/global_data.h>
a523af69	12
e5cb6bd9 MV	13	#define GEN3_NR_REGIONS 16
	14
	15	static struct mm_region gen3_mem_map[GEN3_NR_REGIONS] = {
a523af69 MV	16	{
	17	.virt = 0x0UL,
	18	.phys = 0x0UL,
7beccc52	19	.size = 0x40000000UL,
a523af69 MV	20	.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) \|
	21	PTE_BLOCK_NON_SHARE \|
	22	PTE_BLOCK_PXN \| PTE_BLOCK_UXN
	23	}, {
7beccc52 MV	24	.virt = 0x40000000UL,
7beccc52 MV	25	.phys = 0x40000000UL,
23b9b36a HY	26	.size = 0x03F00000UL,
	27	.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) \|
	28	PTE_BLOCK_INNER_SHARE
	29	}, {
	30	.virt = 0x47E00000UL,
	31	.phys = 0x47E00000UL,
	32	.size = 0x78200000UL,
1154541a MV	33	.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) \|
	34	PTE_BLOCK_INNER_SHARE
	35	}, {
7beccc52 MV	36	.virt = 0xc0000000UL,
	37	.phys = 0xc0000000UL,
	38	.size = 0x40000000UL,
1154541a MV	39	.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) \|
	40	PTE_BLOCK_NON_SHARE \|
	41	PTE_BLOCK_PXN \| PTE_BLOCK_UXN
c1ec3476 MV	42	}, {
	43	.virt = 0x100000000UL,
	44	.phys = 0x100000000UL,
	45	.size = 0xf00000000UL,
	46	.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) \|
	47	PTE_BLOCK_INNER_SHARE
1154541a MV	48	}, {
	49	/* List terminator */
	50	0,
	51	}
	52	};
	53
7beccc52	54	struct mm_region *mem_map = gen3_mem_map;
e5cb6bd9 MV	55
	56	DECLARE_GLOBAL_DATA_PTR;
	57
	58	void enable_caches(void)
	59	{
	60	u64 start, size;
	61	int bank, i = 0;
	62
	63	/* Create map for RPC access */
	64	gen3_mem_map[i].virt = 0x0ULL;
	65	gen3_mem_map[i].phys = 0x0ULL;
	66	gen3_mem_map[i].size = 0x40000000ULL;
	67	gen3_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) \|
	68	PTE_BLOCK_NON_SHARE \|
	69	PTE_BLOCK_PXN \| PTE_BLOCK_UXN;
	70	i++;
	71
	72	/* Generate entires for DRAM in 32bit address space */
	73	for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
	74	start = gd->bd->bi_dram[bank].start;
	75	size = gd->bd->bi_dram[bank].size;
	76
	77	/* Skip empty DRAM banks */
	78	if (!size)
	79	continue;
	80
	81	/* Skip DRAM above 4 GiB */
	82	if (start >> 32ULL)
	83	continue;
	84
	85	/* Mark memory reserved by ATF as cacheable too. */
	86	if (start == 0x48000000) {
10854bcc TK	87	/* Unmark protection area (0x43F00000 to 0x47DFFFFF) */
	88	gen3_mem_map[i].virt = 0x40000000ULL;
	89	gen3_mem_map[i].phys = 0x40000000ULL;
	90	gen3_mem_map[i].size = 0x03F00000ULL;
	91	gen3_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) \|
	92	PTE_BLOCK_INNER_SHARE;
	93	i++;
	94
	95	start = 0x47E00000ULL;
	96	size += 0x00200000ULL;
e5cb6bd9 MV	97	}
	98
	99	gen3_mem_map[i].virt = start;
	100	gen3_mem_map[i].phys = start;
	101	gen3_mem_map[i].size = size;
	102	gen3_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) \|
	103	PTE_BLOCK_INNER_SHARE;
	104	i++;
	105	}
	106
	107	/* Create map for register access */
	108	gen3_mem_map[i].virt = 0xc0000000ULL;
	109	gen3_mem_map[i].phys = 0xc0000000ULL;
	110	gen3_mem_map[i].size = 0x40000000ULL;
	111	gen3_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) \|
	112	PTE_BLOCK_NON_SHARE \|
	113	PTE_BLOCK_PXN \| PTE_BLOCK_UXN;
	114	i++;
	115
	116	/* Generate entires for DRAM in 64bit address space */
	117	for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
	118	start = gd->bd->bi_dram[bank].start;
	119	size = gd->bd->bi_dram[bank].size;
	120
	121	/* Skip empty DRAM banks */
	122	if (!size)
	123	continue;
	124
	125	/* Skip DRAM below 4 GiB */
	126	if (!(start >> 32ULL))
	127	continue;
	128
	129	gen3_mem_map[i].virt = start;
	130	gen3_mem_map[i].phys = start;
	131	gen3_mem_map[i].size = size;
	132	gen3_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) \|
	133	PTE_BLOCK_INNER_SHARE;
	134	i++;
	135	}
	136
	137	/* Zero out the remaining regions. */
	138	for (; i < GEN3_NR_REGIONS; i++) {
	139	gen3_mem_map[i].virt = 0;
	140	gen3_mem_map[i].phys = 0;
	141	gen3_mem_map[i].size = 0;
	142	gen3_mem_map[i].attrs = 0;
	143	}
	144
5055a4e9 TK	145	if (!icache_status())
	146	icache_enable();
	147
e5cb6bd9 MV	148	dcache_enable();
e5cb6bd9 MV	149	}