[J-u-boot.git] / arch / arm / mach-meson / board-axg.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2016 Beniamino Galvani <[email protected]>
 * (C) Copyright 2018 Neil Armstrong <[email protected]>
 */

#include <common.h>
#include <init.h>
#include <net.h>
#include <asm/arch/boot.h>
#include <asm/arch/eth.h>
#include <asm/arch/axg.h>
#include <asm/arch/mem.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/armv8/mmu.h>
#include <linux/sizes.h>
#include <usb.h>
#include <linux/usb/otg.h>
#include <asm/arch/usb-gx.h>
#include <usb/dwc2_udc.h>
#include <clk.h>
#include <phy.h>

DECLARE_GLOBAL_DATA_PTR;

int meson_get_boot_device(void)
{
	return readl(AXG_AO_SEC_GP_CFG0) & AXG_AO_BOOT_DEVICE;
}

/* Configure the reserved memory zones exported by the secure registers
 * into EFI and DTB reserved memory entries.
 */
void meson_init_reserved_memory(void *fdt)
{
	u64 bl31_size, bl31_start;
	u64 bl32_size, bl32_start;
	u32 reg;

	/*
	 * Get ARM Trusted Firmware reserved memory zones in :
	 * - AO_SEC_GP_CFG3: bl32 & bl31 size in KiB, can be 0
	 * - AO_SEC_GP_CFG5: bl31 physical start address, can be NULL
	 * - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL
	 */
	reg = readl(AXG_AO_SEC_GP_CFG3);

	bl31_size = ((reg & AXG_AO_BL31_RSVMEM_SIZE_MASK)
			>> AXG_AO_BL31_RSVMEM_SIZE_SHIFT) * SZ_1K;
	bl32_size = (reg & AXG_AO_BL32_RSVMEM_SIZE_MASK) * SZ_1K;

	bl31_start = readl(AXG_AO_SEC_GP_CFG5);
	bl32_start = readl(AXG_AO_SEC_GP_CFG4);

	/* Add BL31 reserved zone */
	if (bl31_start && bl31_size)
		meson_board_add_reserved_memory(fdt, bl31_start, bl31_size);

	/* Add BL32 reserved zone */
	if (bl32_start && bl32_size)
		meson_board_add_reserved_memory(fdt, bl32_start, bl32_size);
}

phys_size_t get_effective_memsize(void)
{
	/* Size is reported in MiB, convert it in bytes */
	return ((readl(AXG_AO_SEC_GP_CFG0) & AXG_AO_MEM_SIZE_MASK)
			>> AXG_AO_MEM_SIZE_SHIFT) * SZ_1M;
}

static struct mm_region axg_mem_map[] = {
	{
		.virt = 0x0UL,
		.phys = 0x0UL,
		.size = 0x80000000UL,
		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
			 PTE_BLOCK_INNER_SHARE
	}, {
		.virt = 0xf0000000UL,
		.phys = 0xf0000000UL,
		.size = 0x10000000UL,
		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
			 PTE_BLOCK_NON_SHARE |
			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
	}, {
		/* List terminator */
		0,
	}
};

struct mm_region *mem_map = axg_mem_map;

/* Configure the Ethernet MAC with the requested interface mode
 * with some optional flags.
 */
void meson_eth_init(phy_interface_t mode, unsigned int flags)
{
	switch (mode) {
	case PHY_INTERFACE_MODE_RGMII:
	case PHY_INTERFACE_MODE_RGMII_ID:
	case PHY_INTERFACE_MODE_RGMII_RXID:
	case PHY_INTERFACE_MODE_RGMII_TXID:
		/* Set RGMII mode */
		setbits_le32(AXG_ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RGMII |
			     AXG_ETH_REG_0_TX_PHASE(1) |
			     AXG_ETH_REG_0_TX_RATIO(4) |
			     AXG_ETH_REG_0_PHY_CLK_EN |
			     AXG_ETH_REG_0_CLK_EN);
		break;

	case PHY_INTERFACE_MODE_RMII:
		/* Set RMII mode */
		out_le32(AXG_ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RMII |
					AXG_ETH_REG_0_INVERT_RMII_CLK |
					AXG_ETH_REG_0_CLK_EN);
		break;

	default:
		printf("Invalid Ethernet interface mode\n");
		return;
	}

	/* Enable power gate */
	clrbits_le32(AXG_MEM_PD_REG_0, AXG_MEM_PD_REG_0_ETH_MASK);
}

#if CONFIG_IS_ENABLED(USB_DWC3_MESON_GXL) && \
	CONFIG_IS_ENABLED(USB_GADGET_DWC2_OTG)
static struct dwc2_plat_otg_data meson_gx_dwc2_data;

int board_usb_init(int index, enum usb_init_type init)
{
	struct fdtdec_phandle_args args;
	const void *blob = gd->fdt_blob;
	int node, dwc2_node;
	struct udevice *dev, *clk_dev;
	struct clk clk;
	int ret;

	/* find the usb glue node */
	node = fdt_node_offset_by_compatible(blob, -1,
					     "amlogic,meson-gxl-usb-ctrl");
	if (node < 0) {
		debug("Not found usb-control node\n");
		return -ENODEV;
	}

	if (!fdtdec_get_is_enabled(blob, node)) {
		debug("usb is disabled in the device tree\n");
		return -ENODEV;
	}

	ret = uclass_get_device_by_of_offset(UCLASS_SIMPLE_BUS, node, &dev);
	if (ret) {
		debug("Not found usb-control device\n");
		return ret;
	}

	/* find the dwc2 node */
	dwc2_node = fdt_node_offset_by_compatible(blob, node,
						  "amlogic,meson-g12a-usb");
	if (dwc2_node < 0) {
		debug("Not found dwc2 node\n");
		return -ENODEV;
	}

	if (!fdtdec_get_is_enabled(blob, dwc2_node)) {
		debug("dwc2 is disabled in the device tree\n");
		return -ENODEV;
	}

	meson_gx_dwc2_data.regs_otg = fdtdec_get_addr(blob, dwc2_node, "reg");
	if (meson_gx_dwc2_data.regs_otg == FDT_ADDR_T_NONE) {
		debug("usbotg: can't get base address\n");
		return -ENODATA;
	}

	/* Enable clock */
	ret = fdtdec_parse_phandle_with_args(blob, dwc2_node, "clocks",
					     "#clock-cells", 0, 0, &args);
	if (ret) {
		debug("usbotg has no clocks defined in the device tree\n");
		return ret;
	}

	ret = uclass_get_device_by_of_offset(UCLASS_CLK, args.node, &clk_dev);
	if (ret)
		return ret;

	if (args.args_count != 1) {
		debug("Can't find clock ID in the device tree\n");
		return -ENODATA;
	}

	clk.dev = clk_dev;
	clk.id = args.args[0];

	ret = clk_enable(&clk);
	if (ret) {
		debug("Failed to enable usbotg clock\n");
		return ret;
	}

	meson_gx_dwc2_data.rx_fifo_sz = fdtdec_get_int(blob, dwc2_node,
						     "g-rx-fifo-size", 0);
	meson_gx_dwc2_data.np_tx_fifo_sz = fdtdec_get_int(blob, dwc2_node,
							"g-np-tx-fifo-size", 0);
	meson_gx_dwc2_data.tx_fifo_sz = fdtdec_get_int(blob, dwc2_node,
						     "g-tx-fifo-size", 0);

	/* Switch to peripheral mode */
	ret = dwc3_meson_gxl_force_mode(dev, USB_DR_MODE_PERIPHERAL);
	if (ret)
		return ret;

	return dwc2_udc_probe(&meson_gx_dwc2_data);
}

int board_usb_cleanup(int index, enum usb_init_type init)
{
	const void *blob = gd->fdt_blob;
	struct udevice *dev;
	int node;
	int ret;

	/* find the usb glue node */
	node = fdt_node_offset_by_compatible(blob, -1,
					     "amlogic,meson-gxl-usb-ctrl");
	if (node < 0) {
		debug("Not found usb-control node\n");
		return -ENODEV;
	}

	if (!fdtdec_get_is_enabled(blob, node))
		return -ENODEV;

	ret = uclass_get_device_by_of_offset(UCLASS_SIMPLE_BUS, node, &dev);
	if (ret)
		return ret;

	/* Switch to OTG mode */
	ret = dwc3_meson_gxl_force_mode(dev, USB_DR_MODE_HOST);
	if (ret)
		return ret;

	return 0;
}
#endif
Commit	Line	Data
485bba39 NA	1	// SPDX-License-Identifier: GPL-2.0+
	2	/*
	3	* (C) Copyright 2016 Beniamino Galvani <[email protected]>
	4	* (C) Copyright 2018 Neil Armstrong <[email protected]>
	5	*/
	6
	7	#include <common.h>
9b4a205f	8	#include <init.h>
90526e9f	9	#include <net.h>
d96a782d	10	#include <asm/arch/boot.h>
485bba39 NA	11	#include <asm/arch/eth.h>
	12	#include <asm/arch/axg.h>
	13	#include <asm/arch/mem.h>
401d1c4f	14	#include <asm/global_data.h>
485bba39 NA	15	#include <asm/io.h>
	16	#include <asm/armv8/mmu.h>
	17	#include <linux/sizes.h>
e9d29b98 NA	18	#include <usb.h>
	19	#include <linux/usb/otg.h>
	20	#include <asm/arch/usb-gx.h>
	21	#include <usb/dwc2_udc.h>
	22	#include <clk.h>
485bba39 NA	23	#include <phy.h>
	24
	25	DECLARE_GLOBAL_DATA_PTR;
	26
d96a782d NA	27	int meson_get_boot_device(void)
	28	{
	29	return readl(AXG_AO_SEC_GP_CFG0) & AXG_AO_BOOT_DEVICE;
	30	}
	31
485bba39 NA	32	/* Configure the reserved memory zones exported by the secure registers
	33	* into EFI and DTB reserved memory entries.
	34	*/
	35	void meson_init_reserved_memory(void *fdt)
	36	{
	37	u64 bl31_size, bl31_start;
	38	u64 bl32_size, bl32_start;
	39	u32 reg;
	40
	41	/*
	42	* Get ARM Trusted Firmware reserved memory zones in :
	43	* - AO_SEC_GP_CFG3: bl32 & bl31 size in KiB, can be 0
	44	* - AO_SEC_GP_CFG5: bl31 physical start address, can be NULL
	45	* - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL
	46	*/
	47	reg = readl(AXG_AO_SEC_GP_CFG3);
	48
	49	bl31_size = ((reg & AXG_AO_BL31_RSVMEM_SIZE_MASK)
	50	>> AXG_AO_BL31_RSVMEM_SIZE_SHIFT) * SZ_1K;
	51	bl32_size = (reg & AXG_AO_BL32_RSVMEM_SIZE_MASK) * SZ_1K;
	52
	53	bl31_start = readl(AXG_AO_SEC_GP_CFG5);
	54	bl32_start = readl(AXG_AO_SEC_GP_CFG4);
	55
	56	/* Add BL31 reserved zone */
	57	if (bl31_start && bl31_size)
	58	meson_board_add_reserved_memory(fdt, bl31_start, bl31_size);
	59
	60	/* Add BL32 reserved zone */
	61	if (bl32_start && bl32_size)
	62	meson_board_add_reserved_memory(fdt, bl32_start, bl32_size);
	63	}
	64
	65	phys_size_t get_effective_memsize(void)
	66	{
	67	/* Size is reported in MiB, convert it in bytes */
	68	return ((readl(AXG_AO_SEC_GP_CFG0) & AXG_AO_MEM_SIZE_MASK)
	69	>> AXG_AO_MEM_SIZE_SHIFT) * SZ_1M;
	70	}
	71
	72	static struct mm_region axg_mem_map[] = {
	73	{
	74	.virt = 0x0UL,
	75	.phys = 0x0UL,
	76	.size = 0x80000000UL,
	77	.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) \|
	78	PTE_BLOCK_INNER_SHARE
	79	}, {
	80	.virt = 0xf0000000UL,
	81	.phys = 0xf0000000UL,
	82	.size = 0x10000000UL,
	83	.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) \|
	84	PTE_BLOCK_NON_SHARE \|
	85	PTE_BLOCK_PXN \| PTE_BLOCK_UXN
	86	}, {
	87	/* List terminator */
	88	0,
	89	}
	90	};
	91
	92	struct mm_region *mem_map = axg_mem_map;
	93
	94	/* Configure the Ethernet MAC with the requested interface mode
	95	* with some optional flags.
96	*/
97	void meson_eth_init(phy_interface_t mode, unsigned int flags)
98	{
99	switch (mode) {
100	case PHY_INTERFACE_MODE_RGMII:
101	case PHY_INTERFACE_MODE_RGMII_ID:
102	case PHY_INTERFACE_MODE_RGMII_RXID:
103	case PHY_INTERFACE_MODE_RGMII_TXID:
104	/* Set RGMII mode */
105	setbits_le32(AXG_ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RGMII \|
106	AXG_ETH_REG_0_TX_PHASE(1) \|
107	AXG_ETH_REG_0_TX_RATIO(4) \|
108	AXG_ETH_REG_0_PHY_CLK_EN \|
109	AXG_ETH_REG_0_CLK_EN);
110	break;
111
112	case PHY_INTERFACE_MODE_RMII:
113	/* Set RMII mode */
114	out_le32(AXG_ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RMII \|
115	AXG_ETH_REG_0_INVERT_RMII_CLK \|
116	AXG_ETH_REG_0_CLK_EN);
117	break;
118
119	default:
120	printf("Invalid Ethernet interface mode\n");
121	return;
122	}
123
124	/* Enable power gate */
125	clrbits_le32(AXG_MEM_PD_REG_0, AXG_MEM_PD_REG_0_ETH_MASK);
126	}
e9d29b98 NA	127
	128	#if CONFIG_IS_ENABLED(USB_DWC3_MESON_GXL) && \
	129	CONFIG_IS_ENABLED(USB_GADGET_DWC2_OTG)
	130	static struct dwc2_plat_otg_data meson_gx_dwc2_data;
	131
	132	int board_usb_init(int index, enum usb_init_type init)
	133	{
	134	struct fdtdec_phandle_args args;
	135	const void *blob = gd->fdt_blob;
	136	int node, dwc2_node;
	137	struct udevice dev, clk_dev;
	138	struct clk clk;
	139	int ret;
	140
	141	/* find the usb glue node */
	142	node = fdt_node_offset_by_compatible(blob, -1,
	143	"amlogic,meson-gxl-usb-ctrl");
	144	if (node < 0) {
	145	debug("Not found usb-control node\n");
	146	return -ENODEV;
	147	}
	148
	149	if (!fdtdec_get_is_enabled(blob, node)) {
	150	debug("usb is disabled in the device tree\n");
	151	return -ENODEV;
	152	}
	153
	154	ret = uclass_get_device_by_of_offset(UCLASS_SIMPLE_BUS, node, &dev);
	155	if (ret) {
	156	debug("Not found usb-control device\n");
	157	return ret;
	158	}
	159
	160	/* find the dwc2 node */
	161	dwc2_node = fdt_node_offset_by_compatible(blob, node,
	162	"amlogic,meson-g12a-usb");
	163	if (dwc2_node < 0) {
	164	debug("Not found dwc2 node\n");
	165	return -ENODEV;
	166	}
	167
	168	if (!fdtdec_get_is_enabled(blob, dwc2_node)) {
	169	debug("dwc2 is disabled in the device tree\n");
	170	return -ENODEV;
	171	}
	172
	173	meson_gx_dwc2_data.regs_otg = fdtdec_get_addr(blob, dwc2_node, "reg");
	174	if (meson_gx_dwc2_data.regs_otg == FDT_ADDR_T_NONE) {
	175	debug("usbotg: can't get base address\n");
	176	return -ENODATA;
	177	}
	178
	179	/* Enable clock */
	180	ret = fdtdec_parse_phandle_with_args(blob, dwc2_node, "clocks",
	181	"#clock-cells", 0, 0, &args);
	182	if (ret) {
	183	debug("usbotg has no clocks defined in the device tree\n");
	184	return ret;
	185	}
	186
	187	ret = uclass_get_device_by_of_offset(UCLASS_CLK, args.node, &clk_dev);
	188	if (ret)
	189	return ret;
	190
191	if (args.args_count != 1) {
192	debug("Can't find clock ID in the device tree\n");
193	return -ENODATA;
194	}
195
196	clk.dev = clk_dev;
197	clk.id = args.args[0];
198
199	ret = clk_enable(&clk);
200	if (ret) {
201	debug("Failed to enable usbotg clock\n");
202	return ret;
203	}
204
205	meson_gx_dwc2_data.rx_fifo_sz = fdtdec_get_int(blob, dwc2_node,
206	"g-rx-fifo-size", 0);
207	meson_gx_dwc2_data.np_tx_fifo_sz = fdtdec_get_int(blob, dwc2_node,
208	"g-np-tx-fifo-size", 0);
209	meson_gx_dwc2_data.tx_fifo_sz = fdtdec_get_int(blob, dwc2_node,
210	"g-tx-fifo-size", 0);
211
212	/* Switch to peripheral mode */
213	ret = dwc3_meson_gxl_force_mode(dev, USB_DR_MODE_PERIPHERAL);
214	if (ret)
215	return ret;
216
217	return dwc2_udc_probe(&meson_gx_dwc2_data);
218	}
219
220	int board_usb_cleanup(int index, enum usb_init_type init)
221	{
222	const void *blob = gd->fdt_blob;
223	struct udevice *dev;
224	int node;
225	int ret;
226
227	/* find the usb glue node */
228	node = fdt_node_offset_by_compatible(blob, -1,
229	"amlogic,meson-gxl-usb-ctrl");
230	if (node < 0) {
231	debug("Not found usb-control node\n");
232	return -ENODEV;
233	}
234
235	if (!fdtdec_get_is_enabled(blob, node))
236	return -ENODEV;
237
238	ret = uclass_get_device_by_of_offset(UCLASS_SIMPLE_BUS, node, &dev);
239	if (ret)
240	return ret;
241
242	/* Switch to OTG mode */
243	ret = dwc3_meson_gxl_force_mode(dev, USB_DR_MODE_HOST);
244	if (ret)
245	return ret;
246
247	return 0;
248	}
249	#endif