[J-u-boot.git] / arch / arm / cpu / armv7 / sunxi / timer.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2007-2011
 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
 * Tom Cubie <[email protected]>
 */

#include <common.h>
#include <init.h>
#include <time.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/timer.h>
#include <linux/delay.h>

DECLARE_GLOBAL_DATA_PTR;

#define TIMER_MODE   (0x0 << 7)	/* continuous mode */
#define TIMER_DIV    (0x0 << 4)	/* pre scale 1 */
#define TIMER_SRC    (0x1 << 2)	/* osc24m */
#define TIMER_RELOAD (0x1 << 1)	/* reload internal value */
#define TIMER_EN     (0x1 << 0)	/* enable timer */

#define TIMER_CLOCK		(24 * 1000 * 1000)
#define COUNT_TO_USEC(x)	((x) / 24)
#define USEC_TO_COUNT(x)	((x) * 24)
#define TICKS_PER_HZ		(TIMER_CLOCK / CONFIG_SYS_HZ)
#define TICKS_TO_HZ(x)		((x) / TICKS_PER_HZ)

#define TIMER_LOAD_VAL		0xffffffff

#define TIMER_NUM		0	/* we use timer 0 */

/* read the 32-bit timer */
static ulong read_timer(void)
{
	struct sunxi_timer_reg *timers =
		(struct sunxi_timer_reg *)SUNXI_TIMER_BASE;
	struct sunxi_timer *timer = &timers->timer[TIMER_NUM];

	/*
	 * The hardware timer counts down, therefore we invert to
	 * produce an incrementing timer.
	 */
	return ~readl(&timer->val);
}

/* init timer register */
int timer_init(void)
{
	struct sunxi_timer_reg *timers =
		(struct sunxi_timer_reg *)SUNXI_TIMER_BASE;
	struct sunxi_timer *timer = &timers->timer[TIMER_NUM];
	writel(TIMER_LOAD_VAL, &timer->inter);
	writel(TIMER_MODE | TIMER_DIV | TIMER_SRC | TIMER_RELOAD | TIMER_EN,
	       &timer->ctl);

	return 0;
}

/* timer without interrupts */
static ulong get_timer_masked(void)
{
	/* current tick value */
	ulong now = TICKS_TO_HZ(read_timer());

	if (now >= gd->arch.lastinc)	/* normal (non rollover) */
		gd->arch.tbl += (now - gd->arch.lastinc);
	else {
		/* rollover */
		gd->arch.tbl += (TICKS_TO_HZ(TIMER_LOAD_VAL)
				- gd->arch.lastinc) + now;
	}
	gd->arch.lastinc = now;

	return gd->arch.tbl;
}

ulong get_timer(ulong base)
{
	return get_timer_masked() - base;
}

/* delay x useconds */
void __udelay(unsigned long usec)
{
	long tmo = USEC_TO_COUNT(usec);
	ulong now, last = read_timer();

	while (tmo > 0) {
		now = read_timer();
		if (now > last)	/* normal (non rollover) */
			tmo -= now - last;
		else		/* rollover */
			tmo -= TIMER_LOAD_VAL - last + now;
		last = now;
	}
}

/*
 * This function is derived from PowerPC code (read timebase as long long).
 * On ARM it just returns the timer value.
 */
unsigned long long get_ticks(void)
{
	return get_timer(0);
}

/*
 * This function is derived from PowerPC code (timebase clock frequency).
 * On ARM it returns the number of timer ticks per second.
 */
ulong get_tbclk(void)
{
	return CONFIG_SYS_HZ;
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
643cf0ea IC	2	/*
	3	* (C) Copyright 2007-2011
	4	* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
	5	* Tom Cubie <[email protected]>
643cf0ea IC	6	*/
	7
	8	#include <common.h>
691d719d	9	#include <init.h>
1045315d	10	#include <time.h>
401d1c4f	11	#include <asm/global_data.h>
643cf0ea IC	12	#include <asm/io.h>
643cf0ea IC	13	#include <asm/arch/timer.h>
c05ed00a	14	#include <linux/delay.h>
643cf0ea IC	15
	16	DECLARE_GLOBAL_DATA_PTR;
	17
	18	#define TIMER_MODE (0x0 << 7) /* continuous mode */
	19	#define TIMER_DIV (0x0 << 4) /* pre scale 1 */
	20	#define TIMER_SRC (0x1 << 2) /* osc24m */
	21	#define TIMER_RELOAD (0x1 << 1) /* reload internal value */
	22	#define TIMER_EN (0x1 << 0) /* enable timer */
	23
	24	#define TIMER_CLOCK (24 * 1000 * 1000)
	25	#define COUNT_TO_USEC(x) ((x) / 24)
	26	#define USEC_TO_COUNT(x) ((x) * 24)
	27	#define TICKS_PER_HZ (TIMER_CLOCK / CONFIG_SYS_HZ)
	28	#define TICKS_TO_HZ(x) ((x) / TICKS_PER_HZ)
	29
	30	#define TIMER_LOAD_VAL 0xffffffff
	31
	32	#define TIMER_NUM 0 /* we use timer 0 */
	33
	34	/* read the 32-bit timer */
	35	static ulong read_timer(void)
	36	{
	37	struct sunxi_timer_reg *timers =
	38	(struct sunxi_timer_reg *)SUNXI_TIMER_BASE;
	39	struct sunxi_timer *timer = &timers->timer[TIMER_NUM];
	40
	41	/*
	42	* The hardware timer counts down, therefore we invert to
	43	* produce an incrementing timer.
	44	*/
	45	return ~readl(&timer->val);
	46	}
	47
	48	/* init timer register */
	49	int timer_init(void)
	50	{
	51	struct sunxi_timer_reg *timers =
	52	(struct sunxi_timer_reg *)SUNXI_TIMER_BASE;
	53	struct sunxi_timer *timer = &timers->timer[TIMER_NUM];
	54	writel(TIMER_LOAD_VAL, &timer->inter);
	55	writel(TIMER_MODE \| TIMER_DIV \| TIMER_SRC \| TIMER_RELOAD \| TIMER_EN,
	56	&timer->ctl);
	57
	58	return 0;
	59	}
	60
	61	/* timer without interrupts */
6180ea7e	62	static ulong get_timer_masked(void)
643cf0ea IC	63	{
	64	/* current tick value */
	65	ulong now = TICKS_TO_HZ(read_timer());
	66
	67	if (now >= gd->arch.lastinc) /* normal (non rollover) */
	68	gd->arch.tbl += (now - gd->arch.lastinc);
	69	else {
	70	/* rollover */
	71	gd->arch.tbl += (TICKS_TO_HZ(TIMER_LOAD_VAL)
	72	- gd->arch.lastinc) + now;
	73	}
	74	gd->arch.lastinc = now;
	75
	76	return gd->arch.tbl;
	77	}
	78
6180ea7e PD	79	ulong get_timer(ulong base)
	80	{
	81	return get_timer_masked() - base;
	82	}
	83
643cf0ea IC	84	/* delay x useconds */
	85	void __udelay(unsigned long usec)
	86	{
	87	long tmo = USEC_TO_COUNT(usec);
	88	ulong now, last = read_timer();
	89
	90	while (tmo > 0) {
	91	now = read_timer();
	92	if (now > last) /* normal (non rollover) */
	93	tmo -= now - last;
	94	else /* rollover */
	95	tmo -= TIMER_LOAD_VAL - last + now;
	96	last = now;
	97	}
	98	}
	99
	100	/*
	101	* This function is derived from PowerPC code (read timebase as long long).
	102	* On ARM it just returns the timer value.
	103	*/
	104	unsigned long long get_ticks(void)
	105	{
	106	return get_timer(0);
	107	}
	108
	109	/*
	110	* This function is derived from PowerPC code (timebase clock frequency).
	111	* On ARM it returns the number of timer ticks per second.
	112	*/
	113	ulong get_tbclk(void)
	114	{
	115	return CONFIG_SYS_HZ;
	116	}