[J-u-boot.git] / drivers / pci / tsi108_pci.c

/*
 * (C) Copyright 2004 Tundra Semiconductor Corp.
 * Alex Bounine <[email protected]>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * PCI initialisation for the Tsi108 EMU board.
 */

#include <config.h>

#include <common.h>
#include <pci.h>
#include <asm/io.h>
#include <tsi108.h>
#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#include <fdt_support.h>
#endif

struct pci_controller local_hose;

void tsi108_clear_pci_error (void)
{
	u32 err_stat, err_addr, pci_stat;

	/*
	 * Quietly clear errors signalled as result of PCI/X configuration read
	 * requests.
	 */
	/* Read PB Error Log Registers */
	err_stat = *(volatile u32 *)(CONFIG_SYS_TSI108_CSR_BASE +
				     TSI108_PB_REG_OFFSET + PB_ERRCS);
	err_addr = *(volatile u32 *)(CONFIG_SYS_TSI108_CSR_BASE +
				     TSI108_PB_REG_OFFSET + PB_AERR);
	if (err_stat & PB_ERRCS_ES) {
		/* Clear PCI/X bus errors if applicable */
		if ((err_addr & 0xFF000000) == CONFIG_SYS_PCI_CFG_BASE) {
			/* Clear error flag */
			*(u32 *) (CONFIG_SYS_TSI108_CSR_BASE +
				  TSI108_PB_REG_OFFSET + PB_ERRCS) =
			    PB_ERRCS_ES;

			/* Clear read error reported in PB_ISR */
			*(u32 *) (CONFIG_SYS_TSI108_CSR_BASE +
				  TSI108_PB_REG_OFFSET + PB_ISR) =
			    PB_ISR_PBS_RD_ERR;

		/* Clear errors reported by PCI CSR (Normally Master Abort) */
			pci_stat = *(volatile u32 *)(CONFIG_SYS_TSI108_CSR_BASE +
						     TSI108_PCI_REG_OFFSET +
						     PCI_CSR);
			*(volatile u32 *)(CONFIG_SYS_TSI108_CSR_BASE +
					  TSI108_PCI_REG_OFFSET + PCI_CSR) =
			    pci_stat;

			*(volatile u32 *)(CONFIG_SYS_TSI108_CSR_BASE +
					  TSI108_PCI_REG_OFFSET +
					  PCI_IRP_STAT) = PCI_IRP_STAT_P_CSR;
		}
	}

	return;
}

unsigned int __get_pci_config_dword (u32 addr)
{
	unsigned int retval;

	__asm__ __volatile__ ("       lwbrx %0,0,%1\n"
			     "1:     eieio\n"
			     "2:\n"
			     ".section .fixup,\"ax\"\n"
			     "3:     li %0,-1\n"
			     "       b 2b\n"
			     ".section __ex_table,\"a\"\n"
			     "       .align 2\n"
			     "       .long 1b,3b\n"
			     ".section .text.__get_pci_config_dword"
				: "=r"(retval) : "r"(addr));

	return (retval);
}

static int tsi108_read_config_dword (struct pci_controller *hose,
				    pci_dev_t dev, int offset, u32 * value)
{
	dev &= (CONFIG_SYS_PCI_CFG_SIZE - 1);
	dev |= (CONFIG_SYS_PCI_CFG_BASE | (offset & 0xfc));
	*value = __get_pci_config_dword(dev);
	if (0xFFFFFFFF == *value)
		tsi108_clear_pci_error ();
	return 0;
}

static int tsi108_write_config_dword (struct pci_controller *hose,
				     pci_dev_t dev, int offset, u32 value)
{
	dev &= (CONFIG_SYS_PCI_CFG_SIZE - 1);
	dev |= (CONFIG_SYS_PCI_CFG_BASE | (offset & 0xfc));

	out_le32 ((volatile unsigned *)dev, value);

	return 0;
}

void pci_init_board (void)
{
	struct pci_controller *hose = (struct pci_controller *)&local_hose;

	hose->first_busno = 0;
	hose->last_busno = 0xff;

	pci_set_region (hose->regions + 0,
		       CONFIG_SYS_PCI_MEMORY_BUS,
		       CONFIG_SYS_PCI_MEMORY_PHYS,
		       CONFIG_SYS_PCI_MEMORY_SIZE, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);

	/* PCI memory space */
	pci_set_region (hose->regions + 1,
		       CONFIG_SYS_PCI_MEM_BUS,
		       CONFIG_SYS_PCI_MEM_PHYS, CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM);

	/* PCI I/O space */
	pci_set_region (hose->regions + 2,
		       CONFIG_SYS_PCI_IO_BUS,
		       CONFIG_SYS_PCI_IO_PHYS, CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO);

	hose->region_count = 3;

	pci_set_ops (hose,
		    pci_hose_read_config_byte_via_dword,
		    pci_hose_read_config_word_via_dword,
		    tsi108_read_config_dword,
		    pci_hose_write_config_byte_via_dword,
		    pci_hose_write_config_word_via_dword,
		    tsi108_write_config_dword);

	pci_register_hose (hose);

	hose->last_busno = pci_hose_scan (hose);

	debug ("Done PCI initialization\n");
	return;
}

#if defined(CONFIG_OF_LIBFDT)
void ft_pci_setup(void *blob, bd_t *bd)
{
	int nodeoffset;
	int tmp[2];
	const char *path;

	nodeoffset = fdt_path_offset(blob, "/aliases");
	if (nodeoffset >= 0) {
		path = fdt_getprop(blob, nodeoffset, "pci", NULL);
		if (path) {
			tmp[0] = cpu_to_be32(local_hose.first_busno);
			tmp[1] = cpu_to_be32(local_hose.last_busno);
			do_fixup_by_path(blob, path, "bus-range",
				&tmp, sizeof(tmp), 1);
		}
	}
}
#endif /* CONFIG_OF_LIBFDT */
Commit	Line	Data
9226e7d6	1	/*
	2	* (C) Copyright 2004 Tundra Semiconductor Corp.
	3	* Alex Bounine <[email protected]>
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
9226e7d6	6	*/
	7
	8	/*
	9	* PCI initialisation for the Tsi108 EMU board.
	10	*/
	11
	12	#include <config.h>
	13
9226e7d6	14	#include <common.h>
	15	#include <pci.h>
	16	#include <asm/io.h>
	17	#include <tsi108.h>
589c0427 GVB	18	#if defined(CONFIG_OF_LIBFDT)
	19	#include <libfdt.h>
	20	#include <fdt_support.h>
409ecdc0	21	#endif
9226e7d6	22
	23	struct pci_controller local_hose;
	24
ee311214	25	void tsi108_clear_pci_error (void)
9226e7d6	26	{
	27	u32 err_stat, err_addr, pci_stat;
	28
	29	/*
	30	* Quietly clear errors signalled as result of PCI/X configuration read
	31	* requests.
	32	*/
	33	/* Read PB Error Log Registers */
6d0f6bcf	34	err_stat = (volatile u32 )(CONFIG_SYS_TSI108_CSR_BASE +
9226e7d6	35	TSI108_PB_REG_OFFSET + PB_ERRCS);
6d0f6bcf	36	err_addr = (volatile u32 )(CONFIG_SYS_TSI108_CSR_BASE +
9226e7d6	37	TSI108_PB_REG_OFFSET + PB_AERR);
	38	if (err_stat & PB_ERRCS_ES) {
	39	/* Clear PCI/X bus errors if applicable */
6d0f6bcf	40	if ((err_addr & 0xFF000000) == CONFIG_SYS_PCI_CFG_BASE) {
9226e7d6	41	/* Clear error flag */
6d0f6bcf	42	(u32 ) (CONFIG_SYS_TSI108_CSR_BASE +
9226e7d6	43	TSI108_PB_REG_OFFSET + PB_ERRCS) =
	44	PB_ERRCS_ES;
	45
	46	/* Clear read error reported in PB_ISR */
6d0f6bcf	47	(u32 ) (CONFIG_SYS_TSI108_CSR_BASE +
9226e7d6	48	TSI108_PB_REG_OFFSET + PB_ISR) =
	49	PB_ISR_PBS_RD_ERR;
	50
	51	/* Clear errors reported by PCI CSR (Normally Master Abort) */
6d0f6bcf	52	pci_stat = (volatile u32 )(CONFIG_SYS_TSI108_CSR_BASE +
9226e7d6	53	TSI108_PCI_REG_OFFSET +
9226e7d6	54	PCI_CSR);
6d0f6bcf	55	(volatile u32 )(CONFIG_SYS_TSI108_CSR_BASE +
9226e7d6	56	TSI108_PCI_REG_OFFSET + PCI_CSR) =
	57	pci_stat;
	58
6d0f6bcf	59	(volatile u32 )(CONFIG_SYS_TSI108_CSR_BASE +
9226e7d6	60	TSI108_PCI_REG_OFFSET +
	61	PCI_IRP_STAT) = PCI_IRP_STAT_P_CSR;
	62	}
	63	}
	64
	65	return;
	66	}
	67
ee311214	68	unsigned int __get_pci_config_dword (u32 addr)
9226e7d6	69	{
	70	unsigned int retval;
	71
ee311214	72	__asm__ __volatile__ (" lwbrx %0,0,%1\n"
9226e7d6	73	"1: eieio\n"
	74	"2:\n"
	75	".section .fixup,\"ax\"\n"
	76	"3: li %0,-1\n"
	77	" b 2b\n"
	78	".section __ex_table,\"a\"\n"
	79	" .align 2\n"
	80	" .long 1b,3b\n"
e2c2a95e WD	81	".section .text.__get_pci_config_dword"
e2c2a95e WD	82	: "=r"(retval) : "r"(addr));
9226e7d6	83
	84	return (retval);
	85	}
	86
ee311214	87	static int tsi108_read_config_dword (struct pci_controller *hose,
9226e7d6	88	pci_dev_t dev, int offset, u32 * value)
9226e7d6	89	{
6d0f6bcf JCPV	90	dev &= (CONFIG_SYS_PCI_CFG_SIZE - 1);
6d0f6bcf JCPV	91	dev \|= (CONFIG_SYS_PCI_CFG_BASE \| (offset & 0xfc));
9226e7d6	92	*value = __get_pci_config_dword(dev);
9226e7d6	93	if (0xFFFFFFFF == *value)
ee311214	94	tsi108_clear_pci_error ();
9226e7d6	95	return 0;
	96	}
	97
ee311214	98	static int tsi108_write_config_dword (struct pci_controller *hose,
9226e7d6	99	pci_dev_t dev, int offset, u32 value)
9226e7d6	100	{
6d0f6bcf JCPV	101	dev &= (CONFIG_SYS_PCI_CFG_SIZE - 1);
6d0f6bcf JCPV	102	dev \|= (CONFIG_SYS_PCI_CFG_BASE \| (offset & 0xfc));
9226e7d6	103
ee311214	104	out_le32 ((volatile unsigned *)dev, value);
9226e7d6	105
	106	return 0;
	107	}
	108
ee311214	109	void pci_init_board (void)
9226e7d6	110	{
	111	struct pci_controller hose = (struct pci_controller )&local_hose;
	112
	113	hose->first_busno = 0;
	114	hose->last_busno = 0xff;
	115
ee311214	116	pci_set_region (hose->regions + 0,
6d0f6bcf JCPV	117	CONFIG_SYS_PCI_MEMORY_BUS,
6d0f6bcf JCPV	118	CONFIG_SYS_PCI_MEMORY_PHYS,
ff4e66e9	119	CONFIG_SYS_PCI_MEMORY_SIZE, PCI_REGION_MEM \| PCI_REGION_SYS_MEMORY);
9226e7d6	120
9226e7d6	121	/* PCI memory space */
ee311214	122	pci_set_region (hose->regions + 1,
6d0f6bcf JCPV	123	CONFIG_SYS_PCI_MEM_BUS,
6d0f6bcf JCPV	124	CONFIG_SYS_PCI_MEM_PHYS, CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM);
9226e7d6	125
9226e7d6	126	/* PCI I/O space */
ee311214	127	pci_set_region (hose->regions + 2,
6d0f6bcf JCPV	128	CONFIG_SYS_PCI_IO_BUS,
6d0f6bcf JCPV	129	CONFIG_SYS_PCI_IO_PHYS, CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO);
9226e7d6	130
	131	hose->region_count = 3;
	132
ee311214	133	pci_set_ops (hose,
9226e7d6	134	pci_hose_read_config_byte_via_dword,
	135	pci_hose_read_config_word_via_dword,
	136	tsi108_read_config_dword,
	137	pci_hose_write_config_byte_via_dword,
	138	pci_hose_write_config_word_via_dword,
	139	tsi108_write_config_dword);
	140
ee311214	141	pci_register_hose (hose);
9226e7d6	142
ee311214	143	hose->last_busno = pci_hose_scan (hose);
9226e7d6	144
ee311214	145	debug ("Done PCI initialization\n");
9226e7d6	146	return;
	147	}
	148
589c0427 GVB	149	#if defined(CONFIG_OF_LIBFDT)
589c0427 GVB	150	void ft_pci_setup(void blob, bd_t bd)
9226e7d6	151	{
589c0427 GVB	152	int nodeoffset;
	153	int tmp[2];
	154	const char *path;
	155
	156	nodeoffset = fdt_path_offset(blob, "/aliases");
	157	if (nodeoffset >= 0) {
	158	path = fdt_getprop(blob, nodeoffset, "pci", NULL);
	159	if (path) {
	160	tmp[0] = cpu_to_be32(local_hose.first_busno);
	161	tmp[1] = cpu_to_be32(local_hose.last_busno);
	162	do_fixup_by_path(blob, path, "bus-range",
	163	&tmp, sizeof(tmp), 1);
	164	}
9226e7d6	165	}
9226e7d6	166	}
589c0427	167	#endif /* CONFIG_OF_LIBFDT */