[J-u-boot.git] / include / configs / P2041RDB.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright 2011-2012 Freescale Semiconductor, Inc.
 * Copyright 2020-2021 NXP
 */

/*
 * P2041 RDB board configuration file
 * Also supports P2040 RDB
 */
#ifndef __CONFIG_H
#define __CONFIG_H

#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_TEXT_BASE
#define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
#endif

#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
/* Set 1M boot space */
#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
		(0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#endif

/* High Level Configuration Options */

#ifndef CONFIG_RESET_VECTOR_ADDRESS
#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
#endif

#define CFG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS

#ifndef __ASSEMBLY__
#include <linux/stringify.h>
#endif

/*
 * These can be toggled for performance analysis, otherwise use default.
 */
#define CFG_SYS_INIT_L2CSR0		L2CSR0_L2E

#define CFG_POST CFG_SYS_POST_MEMORY	/* test POST memory test */

/*
 *  Config the L3 Cache as L3 SRAM
 */
#define CFG_SYS_INIT_L3_ADDR		CONFIG_RAMBOOT_TEXT_BASE
#ifdef CONFIG_PHYS_64BIT
#define CFG_SYS_INIT_L3_ADDR_PHYS	(0xf00000000ull | \
		CONFIG_RAMBOOT_TEXT_BASE)
#else
#define CFG_SYS_INIT_L3_ADDR_PHYS	CFG_SYS_INIT_L3_ADDR
#endif

#ifdef CONFIG_PHYS_64BIT
#define CFG_SYS_DCSRBAR		0xf0000000
#define CFG_SYS_DCSRBAR_PHYS		0xf00000000ull
#endif

/*
 * DDR Setup
 */
#define CONFIG_VERY_BIG_RAM
#define CFG_SYS_DDR_SDRAM_BASE	0x00000000
#define CFG_SYS_SDRAM_BASE		CFG_SYS_DDR_SDRAM_BASE

#define SPD_EEPROM_ADDRESS	0x52
#define CFG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */

/*
 * Local Bus Definitions
 */

/* Set the local bus clock 1/8 of platform clock */
#define CFG_SYS_LBC_LCRR		LCRR_CLKDIV_8

/*
 * This board doesn't have a promjet connector.
 * However, it uses commone corenet board LAW and TLB.
 * It is necessary to use the same start address with proper offset.
 */
#define CFG_SYS_FLASH_BASE		0xe0000000
#ifdef CONFIG_PHYS_64BIT
#define CFG_SYS_FLASH_BASE_PHYS	0xfe0000000ull
#else
#define CFG_SYS_FLASH_BASE_PHYS	CFG_SYS_FLASH_BASE
#endif

#define CONFIG_FSL_CPLD
#define CPLD_BASE		0xffdf0000	/* CPLD registers */
#ifdef CONFIG_PHYS_64BIT
#define CPLD_BASE_PHYS		0xfffdf0000ull
#else
#define CPLD_BASE_PHYS		CPLD_BASE
#endif

#define PIXIS_LBMAP_SWITCH	7
#define PIXIS_LBMAP_MASK	0xf0
#define PIXIS_LBMAP_SHIFT	4
#define PIXIS_LBMAP_ALTBANK	0x40

/* Nand Flash */
#ifdef CONFIG_NAND_FSL_ELBC
#define CFG_SYS_NAND_BASE		0xffa00000
#ifdef CONFIG_PHYS_64BIT
#define CFG_SYS_NAND_BASE_PHYS	0xfffa00000ull
#else
#define CFG_SYS_NAND_BASE_PHYS	CFG_SYS_NAND_BASE
#endif

#define CFG_SYS_NAND_BASE_LIST     {CFG_SYS_NAND_BASE}

/* NAND flash config */
#define CFG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
			       | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
			       | BR_PS_8	       /* Port Size = 8 bit */ \
			       | BR_MS_FCM	       /* MSEL = FCM */ \
			       | BR_V)		       /* valid */
#define CFG_SYS_NAND_OR_PRELIM  (0xFFFC0000	      /* length 256K */ \
			       | OR_FCM_PGS	       /* Large Page*/ \
			       | OR_FCM_CSCT \
			       | OR_FCM_CST \
			       | OR_FCM_CHT \
			       | OR_FCM_SCY_1 \
			       | OR_FCM_TRLX \
			       | OR_FCM_EHTR)
#endif /* CONFIG_NAND_FSL_ELBC */

#define CFG_SYS_FLASH_BANKS_LIST	{CFG_SYS_FLASH_BASE_PHYS + 0x8000000}

/* define to use L1 as initial stack */
#define CONFIG_L1_INIT_RAM
#define CFG_SYS_INIT_RAM_ADDR	0xffd00000	/* Initial L1 address */
#ifdef CONFIG_PHYS_64BIT
#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW CFG_SYS_INIT_RAM_ADDR
/* The assembler doesn't like typecast */
#define CFG_SYS_INIT_RAM_ADDR_PHYS \
	((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
	  CFG_SYS_INIT_RAM_ADDR_PHYS_LOW)
#else
#define CFG_SYS_INIT_RAM_ADDR_PHYS	CFG_SYS_INIT_RAM_ADDR
#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW CFG_SYS_INIT_RAM_ADDR_PHYS
#endif
#define CFG_SYS_INIT_RAM_SIZE	0x00004000

#define CFG_SYS_INIT_SP_OFFSET	(CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)

/* Serial Port - controlled on board with jumper J8
 * open - index 2
 * shorted - index 1
 */
#define CFG_SYS_NS16550_CLK		(get_bus_freq(0)/2)

#define CFG_SYS_BAUDRATE_TABLE	\
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}

#define CFG_SYS_NS16550_COM1	(CFG_SYS_CCSRBAR+0x11C500)
#define CFG_SYS_NS16550_COM2	(CFG_SYS_CCSRBAR+0x11C600)
#define CFG_SYS_NS16550_COM3	(CFG_SYS_CCSRBAR+0x11D500)
#define CFG_SYS_NS16550_COM4	(CFG_SYS_CCSRBAR+0x11D600)

/* I2C */


/*
 * RapidIO
 */
#define CFG_SYS_SRIO1_MEM_VIRT	0xa0000000
#ifdef CONFIG_PHYS_64BIT
#define CFG_SYS_SRIO1_MEM_PHYS	0xc20000000ull
#else
#define CFG_SYS_SRIO1_MEM_PHYS	0xa0000000
#endif
#define CFG_SYS_SRIO1_MEM_SIZE	0x10000000	/* 256M */

#define CFG_SYS_SRIO2_MEM_VIRT	0xb0000000
#ifdef CONFIG_PHYS_64BIT
#define CFG_SYS_SRIO2_MEM_PHYS	0xc30000000ull
#else
#define CFG_SYS_SRIO2_MEM_PHYS	0xb0000000
#endif
#define CFG_SYS_SRIO2_MEM_SIZE	0x10000000	/* 256M */

/*
 * for slave u-boot IMAGE instored in master memory space,
 * PHYS must be aligned based on the SIZE
 */
#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
#define CFG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000	/* 1M */
#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
/*
 * for slave UCODE and ENV instored in master memory space,
 * PHYS must be aligned based on the SIZE
 */
#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000	/* 256K */

/* slave core release by master*/
#define CFG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
#define CFG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */

/*
 * SRIO_PCIE_BOOT - SLAVE
 */
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
#define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
#define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
		(0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
#endif

/*
 * eSPI - Enhanced SPI
 */

/*
 * General PCI
 * Memory space is mapped 1-1, but I/O space must start from 0.
 */

/* controller 1, direct to uli, tgtid 3, Base address 20000 */
#define CFG_SYS_PCIE1_MEM_VIRT	0x80000000
#define CFG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
#define CFG_SYS_PCIE1_IO_VIRT	0xf8000000
#define CFG_SYS_PCIE1_IO_PHYS	0xff8000000ull

/* controller 2, Slot 2, tgtid 2, Base address 201000 */
#define CFG_SYS_PCIE2_MEM_VIRT	0xa0000000
#define CFG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
#define CFG_SYS_PCIE2_IO_VIRT	0xf8010000
#define CFG_SYS_PCIE2_IO_PHYS	0xff8010000ull

/* controller 3, Slot 1, tgtid 1, Base address 202000 */
#define CFG_SYS_PCIE3_MEM_VIRT	0xc0000000
#define CFG_SYS_PCIE3_MEM_PHYS	0xc40000000ull

/* Qman/Bman */
#define CFG_SYS_BMAN_NUM_PORTALS	10
#define CFG_SYS_BMAN_MEM_BASE	0xf4000000
#ifdef CONFIG_PHYS_64BIT
#define CFG_SYS_BMAN_MEM_PHYS	0xff4000000ull
#else
#define CFG_SYS_BMAN_MEM_PHYS	CFG_SYS_BMAN_MEM_BASE
#endif
#define CFG_SYS_BMAN_MEM_SIZE	0x00200000
#define CFG_SYS_BMAN_SP_CENA_SIZE    0x4000
#define CFG_SYS_BMAN_SP_CINH_SIZE    0x1000
#define CFG_SYS_BMAN_CENA_BASE       CFG_SYS_BMAN_MEM_BASE
#define CFG_SYS_BMAN_CENA_SIZE       (CFG_SYS_BMAN_MEM_SIZE >> 1)
#define CFG_SYS_BMAN_CINH_BASE       (CFG_SYS_BMAN_MEM_BASE + \
					CFG_SYS_BMAN_CENA_SIZE)
#define CFG_SYS_BMAN_CINH_SIZE       (CFG_SYS_BMAN_MEM_SIZE >> 1)
#define CFG_SYS_BMAN_SWP_ISDR_REG	0xE08
#define CFG_SYS_QMAN_NUM_PORTALS	10
#define CFG_SYS_QMAN_MEM_BASE	0xf4200000
#ifdef CONFIG_PHYS_64BIT
#define CFG_SYS_QMAN_MEM_PHYS	0xff4200000ull
#else
#define CFG_SYS_QMAN_MEM_PHYS	CFG_SYS_QMAN_MEM_BASE
#endif
#define CFG_SYS_QMAN_MEM_SIZE	0x00200000
#define CFG_SYS_QMAN_SP_CINH_SIZE    0x1000
#define CFG_SYS_QMAN_CENA_SIZE       (CFG_SYS_QMAN_MEM_SIZE >> 1)
#define CFG_SYS_QMAN_CINH_BASE       (CFG_SYS_QMAN_MEM_BASE + \
					CFG_SYS_QMAN_CENA_SIZE)
#define CFG_SYS_QMAN_CINH_SIZE       (CFG_SYS_QMAN_MEM_SIZE >> 1)
#define CFG_SYS_QMAN_SWP_ISDR_REG	0xE08

#ifdef CONFIG_FMAN_ENET
#define CFG_SYS_FM1_DTSEC1_PHY_ADDR	0x2
#define CFG_SYS_FM1_DTSEC2_PHY_ADDR	0x3
#define CFG_SYS_FM1_DTSEC3_PHY_ADDR	0x4
#define CFG_SYS_FM1_DTSEC4_PHY_ADDR	0x1
#define CFG_SYS_FM1_DTSEC5_PHY_ADDR	0x0

#define CFG_SYS_FM1_DTSEC1_RISER_PHY_ADDR	0x1c
#define CFG_SYS_FM1_DTSEC2_RISER_PHY_ADDR	0x1d
#define CFG_SYS_FM1_DTSEC3_RISER_PHY_ADDR	0x1e
#define CFG_SYS_FM1_DTSEC4_RISER_PHY_ADDR	0x1f

#define CFG_SYS_FM1_10GEC1_PHY_ADDR	0

#define CFG_SYS_TBIPA_VALUE	8
#endif

#ifdef CONFIG_MMC
#define CFG_SYS_FSL_ESDHC_ADDR       CFG_SYS_MPC85xx_ESDHC_ADDR
#endif

/*
 * Miscellaneous configurable options
 */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 64 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory for Linux */

/*
 * Environment Configuration
 */
#define CONFIG_ROOTPATH		"/opt/nfsroot"
#define CONFIG_UBOOTPATH	u-boot.bin

#define __USB_PHY_TYPE	utmi

#define	CONFIG_EXTRA_ENV_SETTINGS				\
	"hwconfig=fsl_ddr:ctlr_intlv=cacheline,"		\
	"bank_intlv=cs0_cs1\0"					\
	"netdev=eth0\0"						\
	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"			\
	"ubootaddr=" __stringify(CONFIG_TEXT_BASE) "\0"		\
	"tftpflash=tftpboot $loadaddr $uboot && "		\
	"protect off $ubootaddr +$filesize && "			\
	"erase $ubootaddr +$filesize && "			\
	"cp.b $loadaddr $ubootaddr $filesize && "		\
	"protect on $ubootaddr +$filesize && "			\
	"cmp.b $loadaddr $ubootaddr $filesize\0"		\
	"consoledev=ttyS0\0"					\
	"usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0"		\
	"usb_dr_mode=host\0"					\
	"ramdiskaddr=2000000\0"					\
	"ramdiskfile=p2041rdb/ramdisk.uboot\0"			\
	"fdtaddr=1e00000\0"					\
	"fdtfile=p2041rdb/p2041rdb.dtb\0"			\
	"bdev=sda3\0"

#include <asm/fsl_secure_boot.h>

#endif	/* __CONFIG_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
4f1d1b7d	2	/*
3d7506fa	3	* Copyright 2011-2012 Freescale Semiconductor, Inc.
a97a071d	4	* Copyright 2020-2021 NXP
4f1d1b7d MH	5	*/
	6
	7	/*
	8	* P2041 RDB board configuration file
3e978f5d	9	* Also supports P2040 RDB
4f1d1b7d MH	10	*/
	11	#ifndef __CONFIG_H
	12	#define __CONFIG_H
	13
4f1d1b7d	14	#ifdef CONFIG_RAMBOOT_PBL
98463903	15	#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_TEXT_BASE
4f1d1b7d MH	16	#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
	17	#endif
	18
461632bd	19	#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
ff65f126	20	/* Set 1M boot space */
a322afc9 TR	21	#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
	22	#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
	23	(0x300000000ull \| CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
ff65f126	24	#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
ff65f126 LG	25	#endif
ff65f126 LG	26
4f1d1b7d	27	/* High Level Configuration Options */
4f1d1b7d	28
4f1d1b7d MH	29	#ifndef CONFIG_RESET_VECTOR_ADDRESS
	30	#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
	31	#endif
	32
cdc5ed8f	33	#define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
4f1d1b7d	34
44d50f0b	35	#ifndef __ASSEMBLY__
1af3c7f4	36	#include <linux/stringify.h>
44d50f0b	37	#endif
4f1d1b7d MH	38
	39	/*
	40	* These can be toggled for performance analysis, otherwise use default.
	41	*/
65cc0e2a	42	#define CFG_SYS_INIT_L2CSR0 L2CSR0_L2E
4f1d1b7d	43
9cebc4ad	44	#define CFG_POST CFG_SYS_POST_MEMORY /* test POST memory test */
4f1d1b7d MH	45
	46	/*
	47	* Config the L3 Cache as L3 SRAM
	48	*/
65cc0e2a	49	#define CFG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
4f1d1b7d	50	#ifdef CONFIG_PHYS_64BIT
65cc0e2a	51	#define CFG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull \| \
4f1d1b7d MH	52	CONFIG_RAMBOOT_TEXT_BASE)
4f1d1b7d MH	53	#else
65cc0e2a	54	#define CFG_SYS_INIT_L3_ADDR_PHYS CFG_SYS_INIT_L3_ADDR
4f1d1b7d	55	#endif
4f1d1b7d	56
4f1d1b7d	57	#ifdef CONFIG_PHYS_64BIT
65cc0e2a TR	58	#define CFG_SYS_DCSRBAR 0xf0000000
65cc0e2a TR	59	#define CFG_SYS_DCSRBAR_PHYS 0xf00000000ull
4f1d1b7d MH	60	#endif
4f1d1b7d MH	61
4f1d1b7d MH	62	/*
	63	* DDR Setup
	64	*/
	65	#define CONFIG_VERY_BIG_RAM
65cc0e2a TR	66	#define CFG_SYS_DDR_SDRAM_BASE 0x00000000
65cc0e2a TR	67	#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
4f1d1b7d	68
4f1d1b7d	69	#define SPD_EEPROM_ADDRESS 0x52
aa6e94de	70	#define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
4f1d1b7d MH	71
	72	/*
	73	* Local Bus Definitions
	74	*/
	75
	76	/* Set the local bus clock 1/8 of platform clock */
65cc0e2a	77	#define CFG_SYS_LBC_LCRR LCRR_CLKDIV_8
4f1d1b7d	78
ca1b0b89 YS	79	/*
	80	* This board doesn't have a promjet connector.
	81	* However, it uses commone corenet board LAW and TLB.
	82	* It is necessary to use the same start address with proper offset.
	83	*/
65cc0e2a	84	#define CFG_SYS_FLASH_BASE 0xe0000000
4f1d1b7d	85	#ifdef CONFIG_PHYS_64BIT
65cc0e2a	86	#define CFG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
4f1d1b7d	87	#else
65cc0e2a	88	#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE
4f1d1b7d MH	89	#endif
4f1d1b7d MH	90
4f1d1b7d MH	91	#define CONFIG_FSL_CPLD
	92	#define CPLD_BASE 0xffdf0000 /* CPLD registers */
	93	#ifdef CONFIG_PHYS_64BIT
	94	#define CPLD_BASE_PHYS 0xfffdf0000ull
	95	#else
	96	#define CPLD_BASE_PHYS CPLD_BASE
	97	#endif
	98
4f1d1b7d MH	99	#define PIXIS_LBMAP_SWITCH 7
	100	#define PIXIS_LBMAP_MASK 0xf0
	101	#define PIXIS_LBMAP_SHIFT 4
	102	#define PIXIS_LBMAP_ALTBANK 0x40
	103
c9b2feaf SX	104	/* Nand Flash */
c9b2feaf SX	105	#ifdef CONFIG_NAND_FSL_ELBC
4e590945	106	#define CFG_SYS_NAND_BASE 0xffa00000
c9b2feaf	107	#ifdef CONFIG_PHYS_64BIT
4e590945	108	#define CFG_SYS_NAND_BASE_PHYS 0xfffa00000ull
c9b2feaf	109	#else
4e590945	110	#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE
c9b2feaf SX	111	#endif
c9b2feaf SX	112
4e590945	113	#define CFG_SYS_NAND_BASE_LIST {CFG_SYS_NAND_BASE}
c9b2feaf SX	114
c9b2feaf SX	115	/* NAND flash config */
4e590945	116	#define CFG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
c9b2feaf SX	117	\| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
	118	\| BR_PS_8 /* Port Size = 8 bit */ \
	119	\| BR_MS_FCM /* MSEL = FCM */ \
	120	\| BR_V) /* valid */
4e590945	121	#define CFG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
c9b2feaf SX	122	\| OR_FCM_PGS /* Large Page*/ \
	123	\| OR_FCM_CSCT \
	124	\| OR_FCM_CST \
	125	\| OR_FCM_CHT \
	126	\| OR_FCM_SCY_1 \
	127	\| OR_FCM_TRLX \
	128	\| OR_FCM_EHTR)
c9b2feaf SX	129	#endif /* CONFIG_NAND_FSL_ELBC */
c9b2feaf SX	130
65cc0e2a	131	#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS + 0x8000000}
4f1d1b7d	132
4f1d1b7d MH	133	/* define to use L1 as initial stack */
4f1d1b7d MH	134	#define CONFIG_L1_INIT_RAM
65cc0e2a	135	#define CFG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
4f1d1b7d	136	#ifdef CONFIG_PHYS_64BIT
65cc0e2a TR	137	#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
65cc0e2a TR	138	#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW CFG_SYS_INIT_RAM_ADDR
4f1d1b7d	139	/* The assembler doesn't like typecast */
65cc0e2a TR	140	#define CFG_SYS_INIT_RAM_ADDR_PHYS \
	141	((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) \| \
	142	CFG_SYS_INIT_RAM_ADDR_PHYS_LOW)
4f1d1b7d	143	#else
65cc0e2a TR	144	#define CFG_SYS_INIT_RAM_ADDR_PHYS CFG_SYS_INIT_RAM_ADDR
	145	#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
	146	#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW CFG_SYS_INIT_RAM_ADDR_PHYS
4f1d1b7d	147	#endif
65cc0e2a	148	#define CFG_SYS_INIT_RAM_SIZE 0x00004000
4f1d1b7d	149
65cc0e2a	150	#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
4f1d1b7d	151
4f1d1b7d MH	152	/* Serial Port - controlled on board with jumper J8
	153	* open - index 2
	154	* shorted - index 1
	155	*/
91092132	156	#define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2)
4f1d1b7d	157
65cc0e2a	158	#define CFG_SYS_BAUDRATE_TABLE \
4f1d1b7d MH	159	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
4f1d1b7d MH	160
65cc0e2a TR	161	#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500)
	162	#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x11C600)
	163	#define CFG_SYS_NS16550_COM3 (CFG_SYS_CCSRBAR+0x11D500)
	164	#define CFG_SYS_NS16550_COM4 (CFG_SYS_CCSRBAR+0x11D600)
4f1d1b7d	165
4f1d1b7d	166	/* I2C */
2f3bb4ab	167
4f1d1b7d MH	168
	169	/*
	170	* RapidIO
	171	*/
a322afc9	172	#define CFG_SYS_SRIO1_MEM_VIRT 0xa0000000
4f1d1b7d	173	#ifdef CONFIG_PHYS_64BIT
a322afc9	174	#define CFG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
4f1d1b7d	175	#else
a322afc9	176	#define CFG_SYS_SRIO1_MEM_PHYS 0xa0000000
4f1d1b7d	177	#endif
a322afc9	178	#define CFG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
4f1d1b7d	179
a322afc9	180	#define CFG_SYS_SRIO2_MEM_VIRT 0xb0000000
4f1d1b7d	181	#ifdef CONFIG_PHYS_64BIT
a322afc9	182	#define CFG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
4f1d1b7d	183	#else
a322afc9	184	#define CFG_SYS_SRIO2_MEM_PHYS 0xb0000000
4f1d1b7d	185	#endif
a322afc9	186	#define CFG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
4f1d1b7d	187
ff65f126 LG	188	/*
	189	* for slave u-boot IMAGE instored in master memory space,
	190	* PHYS must be aligned based on the SIZE
	191	*/
a322afc9 TR	192	#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
	193	#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
	194	#define CFG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
	195	#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
ff65f126 LG	196	/*
	197	* for slave UCODE and ENV instored in master memory space,
	198	* PHYS must be aligned based on the SIZE
	199	*/
a322afc9 TR	200	#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
	201	#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
	202	#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
ff65f126 LG	203
ff65f126 LG	204	/* slave core release by master*/
a322afc9 TR	205	#define CFG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
a322afc9 TR	206	#define CFG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
ff65f126 LG	207
ff65f126 LG	208	/*
461632bd	209	* SRIO_PCIE_BOOT - SLAVE
ff65f126	210	*/
461632bd	211	#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
a322afc9 TR	212	#define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
	213	#define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
	214	(0x300000000ull \| CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
ff65f126 LG	215	#endif
ff65f126 LG	216
4f1d1b7d MH	217	/*
	218	* eSPI - Enhanced SPI
	219	*/
4f1d1b7d MH	220
	221	/*
	222	* General PCI
	223	* Memory space is mapped 1-1, but I/O space must start from 0.
	224	*/
	225
	226	/* controller 1, direct to uli, tgtid 3, Base address 20000 */
ecc8d425 TR	227	#define CFG_SYS_PCIE1_MEM_VIRT 0x80000000
	228	#define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
	229	#define CFG_SYS_PCIE1_IO_VIRT 0xf8000000
	230	#define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull
4f1d1b7d MH	231
4f1d1b7d MH	232	/* controller 2, Slot 2, tgtid 2, Base address 201000 */
ecc8d425 TR	233	#define CFG_SYS_PCIE2_MEM_VIRT 0xa0000000
	234	#define CFG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
	235	#define CFG_SYS_PCIE2_IO_VIRT 0xf8010000
	236	#define CFG_SYS_PCIE2_IO_PHYS 0xff8010000ull
4f1d1b7d MH	237
4f1d1b7d MH	238	/* controller 3, Slot 1, tgtid 1, Base address 202000 */
ecc8d425 TR	239	#define CFG_SYS_PCIE3_MEM_VIRT 0xc0000000
ecc8d425 TR	240	#define CFG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
4f1d1b7d MH	241
4f1d1b7d MH	242	/* Qman/Bman */
65cc0e2a TR	243	#define CFG_SYS_BMAN_NUM_PORTALS 10
65cc0e2a TR	244	#define CFG_SYS_BMAN_MEM_BASE 0xf4000000
4f1d1b7d	245	#ifdef CONFIG_PHYS_64BIT
65cc0e2a	246	#define CFG_SYS_BMAN_MEM_PHYS 0xff4000000ull
4f1d1b7d	247	#else
65cc0e2a	248	#define CFG_SYS_BMAN_MEM_PHYS CFG_SYS_BMAN_MEM_BASE
4f1d1b7d	249	#endif
65cc0e2a TR	250	#define CFG_SYS_BMAN_MEM_SIZE 0x00200000
	251	#define CFG_SYS_BMAN_SP_CENA_SIZE 0x4000
	252	#define CFG_SYS_BMAN_SP_CINH_SIZE 0x1000
	253	#define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE
	254	#define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
	255	#define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \
	256	CFG_SYS_BMAN_CENA_SIZE)
	257	#define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
	258	#define CFG_SYS_BMAN_SWP_ISDR_REG 0xE08
	259	#define CFG_SYS_QMAN_NUM_PORTALS 10
	260	#define CFG_SYS_QMAN_MEM_BASE 0xf4200000
4f1d1b7d	261	#ifdef CONFIG_PHYS_64BIT
65cc0e2a	262	#define CFG_SYS_QMAN_MEM_PHYS 0xff4200000ull
4f1d1b7d	263	#else
65cc0e2a	264	#define CFG_SYS_QMAN_MEM_PHYS CFG_SYS_QMAN_MEM_BASE
4f1d1b7d	265	#endif
65cc0e2a TR	266	#define CFG_SYS_QMAN_MEM_SIZE 0x00200000
	267	#define CFG_SYS_QMAN_SP_CINH_SIZE 0x1000
	268	#define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
	269	#define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \
	270	CFG_SYS_QMAN_CENA_SIZE)
	271	#define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
	272	#define CFG_SYS_QMAN_SWP_ISDR_REG 0xE08
4f1d1b7d	273
4f1d1b7d	274	#ifdef CONFIG_FMAN_ENET
65cc0e2a TR	275	#define CFG_SYS_FM1_DTSEC1_PHY_ADDR 0x2
	276	#define CFG_SYS_FM1_DTSEC2_PHY_ADDR 0x3
	277	#define CFG_SYS_FM1_DTSEC3_PHY_ADDR 0x4
	278	#define CFG_SYS_FM1_DTSEC4_PHY_ADDR 0x1
	279	#define CFG_SYS_FM1_DTSEC5_PHY_ADDR 0x0
4f1d1b7d	280
65cc0e2a TR	281	#define CFG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
	282	#define CFG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
	283	#define CFG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
	284	#define CFG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
4f1d1b7d	285
65cc0e2a	286	#define CFG_SYS_FM1_10GEC1_PHY_ADDR 0
0787ecc0	287
65cc0e2a	288	#define CFG_SYS_TBIPA_VALUE 8
4f1d1b7d MH	289	#endif
4f1d1b7d MH	290
4f1d1b7d	291	#ifdef CONFIG_MMC
6cc04547	292	#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR
4f1d1b7d	293	#endif
737537ef	294
4f1d1b7d MH	295	/*
	296	* Miscellaneous configurable options
	297	*/
4f1d1b7d MH	298
	299	/*
	300	* For booting Linux, the board info and command line data
	301	* have to be in the first 64 MB of memory, since this is
	302	* the maximum mapped by the Linux kernel during initialization.
	303	*/
65cc0e2a	304	#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */
4f1d1b7d	305
4f1d1b7d MH	306	/*
	307	* Environment Configuration
	308	*/
8b3637c6	309	#define CONFIG_ROOTPATH "/opt/nfsroot"
4f1d1b7d MH	310	#define CONFIG_UBOOTPATH u-boot.bin
4f1d1b7d MH	311
4f1d1b7d MH	312	#define __USB_PHY_TYPE utmi
	313
	314	#define CONFIG_EXTRA_ENV_SETTINGS \
	315	"hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
	316	"bank_intlv=cs0_cs1\0" \
	317	"netdev=eth0\0" \
5368c55d	318	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
98463903	319	"ubootaddr=" __stringify(CONFIG_TEXT_BASE) "\0" \
4f1d1b7d MH	320	"tftpflash=tftpboot $loadaddr $uboot && " \
	321	"protect off $ubootaddr +$filesize && " \
	322	"erase $ubootaddr +$filesize && " \
	323	"cp.b $loadaddr $ubootaddr $filesize && " \
	324	"protect on $ubootaddr +$filesize && " \
	325	"cmp.b $loadaddr $ubootaddr $filesize\0" \
	326	"consoledev=ttyS0\0" \
5368c55d	327	"usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
4f1d1b7d MH	328	"usb_dr_mode=host\0" \
	329	"ramdiskaddr=2000000\0" \
	330	"ramdiskfile=p2041rdb/ramdisk.uboot\0" \
b24a4f62	331	"fdtaddr=1e00000\0" \
4f1d1b7d	332	"fdtfile=p2041rdb/p2041rdb.dtb\0" \
3246584d	333	"bdev=sda3\0"
4f1d1b7d	334
4f1d1b7d	335	#include <asm/fsl_secure_boot.h>
4f1d1b7d MH	336
4f1d1b7d MH	337	#endif /* __CONFIG_H */