[J-u-boot.git] / include / configs / T104xRDB.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright 2014 Freescale Semiconductor, Inc.
 * Copyright 2020-2021 NXP
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#include <linux/stringify.h>

/*
 * T104x RDB board configuration file
 */
#include <asm/config_mpc85xx.h>

#ifdef CONFIG_RAMBOOT_PBL
#define RESET_VECTOR_OFFSET		0x27FFC
#define BOOT_PAGE_OFFSET		0x27000

#ifdef CONFIG_MTD_RAW_NAND
#ifdef CONFIG_NXP_ESBC
#define CONFIG_U_BOOT_HDR_SIZE		(16 << 10)
/*
 * HDR would be appended at end of image and copied to DDR along
 * with U-Boot image.
 */
#define CONFIG_SYS_NAND_U_BOOT_SIZE	((768 << 10) + \
					 CONFIG_U_BOOT_HDR_SIZE)
#else
#define CONFIG_SYS_NAND_U_BOOT_SIZE	(768 << 10)
#endif
#define CONFIG_SYS_NAND_U_BOOT_DST	0x30000000
#define CONFIG_SYS_NAND_U_BOOT_START	0x30000000
#endif

#ifdef CONFIG_SPIFLASH
#define	CONFIG_RESET_VECTOR_ADDRESS		0x30000FFC
#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE	(768 << 10)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST		(0x30000000)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_START	(0x30000000)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS	(256 << 10)
#endif

#ifdef CONFIG_SDCARD
#define	CONFIG_RESET_VECTOR_ADDRESS		0x30000FFC
#define CONFIG_SYS_MMC_U_BOOT_SIZE	(768 << 10)
#define CONFIG_SYS_MMC_U_BOOT_DST	(0x30000000)
#define CONFIG_SYS_MMC_U_BOOT_START	(0x30000000)
#define CONFIG_SYS_MMC_U_BOOT_OFFS	(260 << 10)
#endif

#endif

/* High Level Configuration Options */
#define CONFIG_SYS_BOOK3E_HV		/* Category E.HV supported */

#ifndef CONFIG_RESET_VECTOR_ADDRESS
#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
#endif

#define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS

/*
 * These can be toggled for performance analysis, otherwise use default.
 */
#define CONFIG_SYS_CACHE_STASHING
#define CONFIG_SYS_INIT_L2CSR0		L2CSR0_L2E
#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
#endif

/*
 *  Config the L3 Cache as L3 SRAM
 */
#define CONFIG_SYS_INIT_L3_ADDR		0xFFFC0000
/*
 * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence
 * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address
 * (CONFIG_SYS_INIT_L3_VADDR) will be different.
 */
#define CONFIG_SYS_INIT_L3_VADDR	0xFFFC0000
#define CONFIG_SYS_L3_SIZE		256 << 10
#define SPL_ENV_ADDR			(CONFIG_SPL_GD_ADDR + 4 * 1024)

#define CONFIG_SYS_DCSRBAR		0xf0000000
#define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull

/*
 * DDR Setup
 */
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE

#define SPD_EEPROM_ADDRESS	0x51

#define CONFIG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */

/*
 * IFC Definitions
 */
#define CONFIG_SYS_FLASH_BASE	0xe8000000
#define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)

#define CONFIG_SYS_NOR_CSPR_EXT	(0xf)
#define CONFIG_SYS_NOR_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
				CSPR_PORT_SIZE_16 | \
				CSPR_MSEL_NOR | \
				CSPR_V)
#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)

/*
 * TDM Definition
 */
#define T1040_TDM_QUIRK_CCSR_BASE	0xfe000000

/* NOR Flash Timing Params */
#define CONFIG_SYS_NOR_CSOR	CSOR_NAND_TRHZ_80
#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
				FTIM0_NOR_TEADC(0x5) | \
				FTIM0_NOR_TEAHC(0x5))
#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
				FTIM1_NOR_TRAD_NOR(0x1A) |\
				FTIM1_NOR_TSEQRAD_NOR(0x13))
#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
				FTIM2_NOR_TCH(0x4) | \
				FTIM2_NOR_TWPH(0x0E) | \
				FTIM2_NOR_TWP(0x1c))
#define CONFIG_SYS_NOR_FTIM3	0x0

#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */

#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */

#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS}

/* CPLD on IFC */
#define CPLD_LBMAP_MASK			0x3F
#define CPLD_BANK_SEL_MASK		0x07
#define CPLD_BANK_OVERRIDE		0x40
#define CPLD_LBMAP_ALTBANK		0x44 /* BANK OR | BANK 4 */
#define CPLD_LBMAP_DFLTBANK		0x40 /* BANK OR | BANK0 */
#define CPLD_LBMAP_RESET		0xFF
#define CPLD_LBMAP_SHIFT		0x03

#if defined(CONFIG_TARGET_T1042RDB_PI)
#define CPLD_DIU_SEL_DFP		0x80
#elif defined(CONFIG_TARGET_T1042D4RDB)
#define CPLD_DIU_SEL_DFP		0xc0
#endif

#if defined(CONFIG_TARGET_T1040D4RDB)
#define CPLD_INT_MASK_ALL		0xFF
#define CPLD_INT_MASK_THERM		0x80
#define CPLD_INT_MASK_DVI_DFP		0x40
#define CPLD_INT_MASK_QSGMII1		0x20
#define CPLD_INT_MASK_QSGMII2		0x10
#define CPLD_INT_MASK_SGMI1		0x08
#define CPLD_INT_MASK_SGMI2		0x04
#define CPLD_INT_MASK_TDMR1		0x02
#define CPLD_INT_MASK_TDMR2		0x01
#endif

#define CONFIG_SYS_CPLD_BASE	0xffdf0000
#define CONFIG_SYS_CPLD_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_CPLD_BASE)
#define CONFIG_SYS_CSPR2_EXT	(0xf)
#define CONFIG_SYS_CSPR2	(CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
				| CSPR_PORT_SIZE_8 \
				| CSPR_MSEL_GPCM \
				| CSPR_V)
#define CONFIG_SYS_AMASK2	IFC_AMASK(64*1024)
#define CONFIG_SYS_CSOR2	0x0
/* CPLD Timing parameters for IFC CS2 */
#define CONFIG_SYS_CS2_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
					FTIM0_GPCM_TEADC(0x0e) | \
					FTIM0_GPCM_TEAHC(0x0e))
#define CONFIG_SYS_CS2_FTIM1		(FTIM1_GPCM_TACO(0x0e) | \
					FTIM1_GPCM_TRAD(0x1f))
#define CONFIG_SYS_CS2_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
					FTIM2_GPCM_TCH(0x8) | \
					FTIM2_GPCM_TWP(0x1f))
#define CONFIG_SYS_CS2_FTIM3		0x0

/* NAND Flash on IFC */
#define CONFIG_SYS_NAND_BASE		0xff800000
#define CONFIG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_NAND_BASE)

#define CONFIG_SYS_NAND_CSPR_EXT	(0xf)
#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
				| CSPR_V)
#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)

#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
				| CSOR_NAND_RAL_3	/* RAL = 3Byes */ \
				| CSOR_NAND_PGS_4K	/* Page Size = 4K */ \
				| CSOR_NAND_SPRZ_224/* Spare size = 224 */ \
				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/

/* ONFI NAND Flash mode0 Timing Params */
#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
					FTIM0_NAND_TWP(0x18)   | \
					FTIM0_NAND_TWCHT(0x07) | \
					FTIM0_NAND_TWH(0x0a))
#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
					FTIM1_NAND_TWBE(0x39)  | \
					FTIM1_NAND_TRR(0x0e)   | \
					FTIM1_NAND_TRP(0x18))
#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
					FTIM2_NAND_TREH(0x0a) | \
					FTIM2_NAND_TWHRE(0x1e))
#define CONFIG_SYS_NAND_FTIM3		0x0

#define CONFIG_SYS_NAND_DDR_LAW		11
#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE	1

#if defined(CONFIG_MTD_RAW_NAND)
#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR_CSPR_EXT
#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR_CSPR
#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
#else
#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR_CSPR_EXT
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR1		CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK1		CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR1		CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
#endif

#if defined(CONFIG_RAMBOOT_PBL)
#define CONFIG_SYS_RAMBOOT
#endif

#define CONFIG_HWCONFIG

/* define to use L1 as initial stack */
#define CONFIG_L1_INIT_RAM
#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address */
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe03c000
/* The assembler doesn't like typecast */
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
#define CONFIG_SYS_INIT_RAM_SIZE		0x00004000

#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)

#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)

/* Serial Port - controlled on board with jumper J8
 * open - index 2
 * shorted - index 1
 */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)

#define CONFIG_SYS_BAUDRATE_TABLE	\
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x11C500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x11C600)
#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
#define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)

/* I2C bus multiplexer */
#define I2C_MUX_PCA_ADDR                0x70
#define I2C_MUX_CH_DEFAULT      0x8

#if defined(CONFIG_TARGET_T1042RDB_PI)	|| \
	defined(CONFIG_TARGET_T1040D4RDB)	|| \
	defined(CONFIG_TARGET_T1042D4RDB)
/* LDI/DVI Encoder for display */
#define CONFIG_SYS_I2C_LDI_ADDR		0x38
#define CONFIG_SYS_I2C_DVI_ADDR		0x75
#define CONFIG_SYS_I2C_DVI_BUS_NUM	0

/*
 * RTC configuration
 */
#define RTC
#define CONFIG_RTC_DS1337               1
#define CONFIG_SYS_I2C_RTC_ADDR         0x68

/*DVI encoder*/
#define CONFIG_HDMI_ENCODER_I2C_ADDR  0x75
#endif

/*
 * eSPI - Enhanced SPI
 */

/*
 * General PCI
 * Memory space is mapped 1-1, but I/O space must start from 0.
 */

#ifdef CONFIG_PCI
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
#ifdef CONFIG_PCIE1
#define	CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
#define	CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
#define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
#define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
#endif

/* controller 2, Slot 2, tgtid 2, Base address 201000 */
#ifdef CONFIG_PCIE2
#define CONFIG_SYS_PCIE2_MEM_VIRT	0x90000000
#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc10000000ull
#define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
#define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
#endif

/* controller 3, Slot 1, tgtid 1, Base address 202000 */
#ifdef CONFIG_PCIE3
#define CONFIG_SYS_PCIE3_MEM_VIRT	0xa0000000
#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc20000000ull
#define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
#define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
#endif

/* controller 4, Base address 203000 */
#ifdef CONFIG_PCIE4
#define CONFIG_SYS_PCIE4_MEM_VIRT	0xb0000000
#define CONFIG_SYS_PCIE4_MEM_PHYS	0xc30000000ull
#define CONFIG_SYS_PCIE4_IO_VIRT	0xf8030000
#define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
#endif

#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
#endif	/* CONFIG_PCI */

/*
* USB
*/

#ifdef CONFIG_MMC
#define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
#endif

/* Qman/Bman */
#ifndef CONFIG_NOBQFMAN
#define CONFIG_SYS_BMAN_NUM_PORTALS	10
#define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
#define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
#define CONFIG_SYS_BMAN_MEM_SIZE	0x02000000
#define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
#define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
#define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
#define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
					CONFIG_SYS_BMAN_CENA_SIZE)
#define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_BMAN_SWP_ISDR_REG	0xE08
#define CONFIG_SYS_QMAN_NUM_PORTALS	10
#define CONFIG_SYS_QMAN_MEM_BASE	0xf6000000
#define CONFIG_SYS_QMAN_MEM_PHYS	0xff6000000ull
#define CONFIG_SYS_QMAN_MEM_SIZE	0x02000000
#define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
#define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
#define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
#define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
					CONFIG_SYS_QMAN_CENA_SIZE)
#define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_QMAN_SWP_ISDR_REG	0xE08

#define CONFIG_SYS_DPAA_FMAN
#define CONFIG_SYS_DPAA_PME

#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#endif /* CONFIG_NOBQFMAN */

#ifdef CONFIG_FMAN_ENET
#if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB)
#define CONFIG_SYS_SGMII1_PHY_ADDR             0x03
#elif defined(CONFIG_TARGET_T1040D4RDB)
#define CONFIG_SYS_SGMII1_PHY_ADDR             0x01
#elif defined(CONFIG_TARGET_T1042D4RDB)
#define CONFIG_SYS_SGMII1_PHY_ADDR             0x02
#define CONFIG_SYS_SGMII2_PHY_ADDR             0x03
#define CONFIG_SYS_SGMII3_PHY_ADDR             0x01
#endif

#if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
#define CONFIG_SYS_RGMII1_PHY_ADDR             0x04
#define CONFIG_SYS_RGMII2_PHY_ADDR             0x05
#else
#define CONFIG_SYS_RGMII1_PHY_ADDR             0x01
#define CONFIG_SYS_RGMII2_PHY_ADDR             0x02
#endif

/* Enable VSC9953 L2 Switch driver on T1040 SoC */
#if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB)
#define CONFIG_VSC9953
#ifdef CONFIG_TARGET_T1040RDB
#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR	0x04
#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR	0x08
#else
#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR	0x08
#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR	0x0c
#endif
#endif
#endif

/*
 * Environment
 */
#define CONFIG_LOADS_ECHO		/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */

/*
 * Miscellaneous configurable options
 */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 64 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */

/*
 * Dynamic MTD Partition support with mtdparts
 */

/*
 * Environment Configuration
 */
#define CONFIG_ROOTPATH		"/opt/nfsroot"
#define CONFIG_UBOOTPATH	"u-boot.bin"	/* U-Boot image on TFTP server*/

#define __USB_PHY_TYPE	utmi
#define RAMDISKFILE	"t104xrdb/ramdisk.uboot"

#ifdef CONFIG_TARGET_T1040RDB
#define FDTFILE		"t1040rdb/t1040rdb.dtb"
#elif defined(CONFIG_TARGET_T1042RDB_PI)
#define FDTFILE		"t1042rdb_pi/t1042rdb_pi.dtb"
#elif defined(CONFIG_TARGET_T1042RDB)
#define FDTFILE		"t1042rdb/t1042rdb.dtb"
#elif defined(CONFIG_TARGET_T1040D4RDB)
#define FDTFILE		"t1042rdb/t1040d4rdb.dtb"
#elif defined(CONFIG_TARGET_T1042D4RDB)
#define FDTFILE		"t1042rdb/t1042d4rdb.dtb"
#endif

#define	CONFIG_EXTRA_ENV_SETTINGS				\
	"hwconfig=fsl_ddr:bank_intlv=cs0_cs1;"			\
	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
	"usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
	"netdev=eth0\0"						\
	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"	\
	"tftpflash=tftpboot $loadaddr $uboot && "		\
	"protect off $ubootaddr +$filesize && "			\
	"erase $ubootaddr +$filesize && "			\
	"cp.b $loadaddr $ubootaddr $filesize && "		\
	"protect on $ubootaddr +$filesize && "			\
	"cmp.b $loadaddr $ubootaddr $filesize\0"		\
	"consoledev=ttyS0\0"					\
	"ramdiskaddr=2000000\0"					\
	"ramdiskfile=" __stringify(RAMDISKFILE) "\0"		\
	"fdtaddr=1e00000\0"					\
	"fdtfile=" __stringify(FDTFILE) "\0"			\
	"bdev=sda3\0"

#include <asm/fsl_secure_boot.h>

#endif	/* __CONFIG_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
062ef1a6	2	/*
83d290c5	3	* Copyright 2014 Freescale Semiconductor, Inc.
a97a071d	4	* Copyright 2020-2021 NXP
83d290c5	5	*/
062ef1a6 PJ	6
	7	#ifndef __CONFIG_H
	8	#define __CONFIG_H
	9
1af3c7f4 SG	10	#include <linux/stringify.h>
1af3c7f4 SG	11
062ef1a6	12	/*
f4c3917a	13	* T104x RDB board configuration file
062ef1a6	14	*/
9f074e67 PK	15	#include <asm/config_mpc85xx.h>
9f074e67 PK	16
062ef1a6	17	#ifdef CONFIG_RAMBOOT_PBL
18c01445 PK	18	#define RESET_VECTOR_OFFSET 0x27FFC
	19	#define BOOT_PAGE_OFFSET 0x27000
	20
88718be3	21	#ifdef CONFIG_MTD_RAW_NAND
bef18454	22	#ifdef CONFIG_NXP_ESBC
aa36c84e SG	23	#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
	24	/*
	25	* HDR would be appended at end of image and copied to DDR along
	26	* with U-Boot image.
	27	*/
	28	#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \
	29	CONFIG_U_BOOT_HDR_SIZE)
	30	#else
18c01445	31	#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
aa36c84e	32	#endif
ce249d95 TY	33	#define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
ce249d95 TY	34	#define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
18c01445 PK	35	#endif
	36
	37	#ifdef CONFIG_SPIFLASH
ce249d95	38	#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
18c01445	39	#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
ce249d95 TY	40	#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
ce249d95 TY	41	#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
18c01445	42	#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
18c01445 PK	43	#endif
	44
	45	#ifdef CONFIG_SDCARD
ce249d95	46	#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
18c01445	47	#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
ce249d95 TY	48	#define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
ce249d95 TY	49	#define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
18c01445	50	#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
18c01445 PK	51	#endif
18c01445 PK	52
062ef1a6 PJ	53	#endif
	54
	55	/* High Level Configuration Options */
062ef1a6	56	#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
062ef1a6	57
062ef1a6 PJ	58	#ifndef CONFIG_RESET_VECTOR_ADDRESS
	59	#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
	60	#endif
	61
	62	#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
51370d56	63	#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
062ef1a6	64
062ef1a6 PJ	65	/*
	66	* These can be toggled for performance analysis, otherwise use default.
	67	*/
	68	#define CONFIG_SYS_CACHE_STASHING
062ef1a6	69	#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
062ef1a6	70	#ifdef CONFIG_DDR_ECC
062ef1a6 PJ	71	#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
	72	#endif
	73
062ef1a6 PJ	74	/*
	75	* Config the L3 Cache as L3 SRAM
	76	*/
	77	#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
aa36c84e SG	78	/*
	79	* For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence
	80	* Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address
	81	* (CONFIG_SYS_INIT_L3_VADDR) will be different.
	82	*/
	83	#define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000
18c01445	84	#define CONFIG_SYS_L3_SIZE 256 << 10
a09fea1d	85	#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
062ef1a6 PJ	86
	87	#define CONFIG_SYS_DCSRBAR 0xf0000000
	88	#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
	89
	90	/*
	91	* DDR Setup
	92	*/
	93	#define CONFIG_VERY_BIG_RAM
	94	#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
	95	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
	96
062ef1a6 PJ	97	#define SPD_EEPROM_ADDRESS 0x51
	98
	99	#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
	100
	101	/*
	102	* IFC Definitions
	103	*/
	104	#define CONFIG_SYS_FLASH_BASE 0xe8000000
	105	#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull \| CONFIG_SYS_FLASH_BASE)
	106
	107	#define CONFIG_SYS_NOR_CSPR_EXT (0xf)
	108	#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) \| \
	109	CSPR_PORT_SIZE_16 \| \
	110	CSPR_MSEL_NOR \| \
	111	CSPR_V)
	112	#define CONFIG_SYS_NOR_AMASK IFC_AMASK(12810241024)
377ffcfa SS	113
	114	/*
	115	* TDM Definition
	116	*/
	117	#define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000
	118
062ef1a6 PJ	119	/* NOR Flash Timing Params */
	120	#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
	121	#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) \| \
	122	FTIM0_NOR_TEADC(0x5) \| \
	123	FTIM0_NOR_TEAHC(0x5))
	124	#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) \| \
	125	FTIM1_NOR_TRAD_NOR(0x1A) \|\
	126	FTIM1_NOR_TSEQRAD_NOR(0x13))
	127	#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) \| \
	128	FTIM2_NOR_TCH(0x4) \| \
	129	FTIM2_NOR_TWPH(0x0E) \| \
	130	FTIM2_NOR_TWP(0x1c))
	131	#define CONFIG_SYS_NOR_FTIM3 0x0
	132
	133	#define CONFIG_SYS_FLASH_QUIET_TEST
	134	#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
	135
062ef1a6 PJ	136	#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
	137	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	138	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
	139
	140	#define CONFIG_SYS_FLASH_EMPTY_INFO
	141	#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
	142
	143	/* CPLD on IFC */
55153d6c PK	144	#define CPLD_LBMAP_MASK 0x3F
	145	#define CPLD_BANK_SEL_MASK 0x07
	146	#define CPLD_BANK_OVERRIDE 0x40
	147	#define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR \| BANK 4 */
	148	#define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR \| BANK0 */
	149	#define CPLD_LBMAP_RESET 0xFF
	150	#define CPLD_LBMAP_SHIFT 0x03
4b6067ae	151
55ed8ae3	152	#if defined(CONFIG_TARGET_T1042RDB_PI)
cf8ddacf	153	#define CPLD_DIU_SEL_DFP 0x80
319ed24a	154	#elif defined(CONFIG_TARGET_T1042D4RDB)
4b6067ae PJ	155	#define CPLD_DIU_SEL_DFP 0xc0
	156	#endif
	157
a016735c	158	#if defined(CONFIG_TARGET_T1040D4RDB)
4b6067ae PJ	159	#define CPLD_INT_MASK_ALL 0xFF
	160	#define CPLD_INT_MASK_THERM 0x80
	161	#define CPLD_INT_MASK_DVI_DFP 0x40
	162	#define CPLD_INT_MASK_QSGMII1 0x20
	163	#define CPLD_INT_MASK_QSGMII2 0x10
	164	#define CPLD_INT_MASK_SGMI1 0x08
	165	#define CPLD_INT_MASK_SGMI2 0x04
	166	#define CPLD_INT_MASK_TDMR1 0x02
	167	#define CPLD_INT_MASK_TDMR2 0x01
cf8ddacf	168	#endif
55153d6c	169
062ef1a6 PJ	170	#define CONFIG_SYS_CPLD_BASE 0xffdf0000
062ef1a6 PJ	171	#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull \| CONFIG_SYS_CPLD_BASE)
9b444be3	172	#define CONFIG_SYS_CSPR2_EXT (0xf)
062ef1a6 PJ	173	#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
	174	\| CSPR_PORT_SIZE_8 \
	175	\| CSPR_MSEL_GPCM \
	176	\| CSPR_V)
	177	#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
	178	#define CONFIG_SYS_CSOR2 0x0
	179	/* CPLD Timing parameters for IFC CS2 */
	180	#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) \| \
	181	FTIM0_GPCM_TEADC(0x0e) \| \
	182	FTIM0_GPCM_TEAHC(0x0e))
	183	#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) \| \
	184	FTIM1_GPCM_TRAD(0x1f))
	185	#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) \| \
de519163	186	FTIM2_GPCM_TCH(0x8) \| \
062ef1a6 PJ	187	FTIM2_GPCM_TWP(0x1f))
	188	#define CONFIG_SYS_CS2_FTIM3 0x0
	189
	190	/* NAND Flash on IFC */
062ef1a6 PJ	191	#define CONFIG_SYS_NAND_BASE 0xff800000
	192	#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull \| CONFIG_SYS_NAND_BASE)
	193
	194	#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
	195	#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
	196	\| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
	197	\| CSPR_MSEL_NAND /* MSEL = NAND */ \
	198	\| CSPR_V)
	199	#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
	200
	201	#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
	202	\| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
	203	\| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
	204	\| CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
	205	\| CSOR_NAND_PGS_4K /* Page Size = 4K */ \
	206	\| CSOR_NAND_SPRZ_224/* Spare size = 224 */ \
	207	\| CSOR_NAND_PB(64)) /Pages Per Block = 64/
	208
062ef1a6 PJ	209	/* ONFI NAND Flash mode0 Timing Params */
	210	#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) \| \
	211	FTIM0_NAND_TWP(0x18) \| \
	212	FTIM0_NAND_TWCHT(0x07) \| \
	213	FTIM0_NAND_TWH(0x0a))
	214	#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) \| \
	215	FTIM1_NAND_TWBE(0x39) \| \
	216	FTIM1_NAND_TRR(0x0e) \| \
	217	FTIM1_NAND_TRP(0x18))
	218	#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) \| \
	219	FTIM2_NAND_TREH(0x0a) \| \
	220	FTIM2_NAND_TWHRE(0x1e))
	221	#define CONFIG_SYS_NAND_FTIM3 0x0
	222
	223	#define CONFIG_SYS_NAND_DDR_LAW 11
	224	#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
	225	#define CONFIG_SYS_MAX_NAND_DEVICE 1
062ef1a6	226
88718be3	227	#if defined(CONFIG_MTD_RAW_NAND)
062ef1a6 PJ	228	#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
	229	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
	230	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
	231	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
	232	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
	233	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
	234	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
	235	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
	236	#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT
	237	#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
	238	#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
	239	#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
	240	#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
	241	#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
	242	#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
	243	#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
	244	#else
	245	#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
	246	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
	247	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
	248	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
	249	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
	250	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
	251	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
	252	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
	253	#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
	254	#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
	255	#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
	256	#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
	257	#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
	258	#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
	259	#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
	260	#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
	261	#endif
	262
062ef1a6 PJ	263	#if defined(CONFIG_RAMBOOT_PBL)
	264	#define CONFIG_SYS_RAMBOOT
	265	#endif
	266
062ef1a6 PJ	267	#define CONFIG_HWCONFIG
	268
	269	/* define to use L1 as initial stack */
	270	#define CONFIG_L1_INIT_RAM
	271	#define CONFIG_SYS_INIT_RAM_LOCK
	272	#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
	273	#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
b3142e2c	274	#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
062ef1a6 PJ	275	/* The assembler doesn't like typecast */
	276	#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
	277	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) \| \
	278	CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
	279	#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
	280
4c97c8cd	281	#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
062ef1a6	282
9307cbab	283	#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
062ef1a6 PJ	284
	285	/* Serial Port - controlled on board with jumper J8
	286	* open - index 2
	287	* shorted - index 1
	288	*/
062ef1a6 PJ	289	#define CONFIG_SYS_NS16550_SERIAL
	290	#define CONFIG_SYS_NS16550_REG_SIZE 1
	291	#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
	292
	293	#define CONFIG_SYS_BAUDRATE_TABLE \
	294	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
	295
	296	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
	297	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
	298	#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
	299	#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
062ef1a6	300
062ef1a6 PJ	301	/* I2C bus multiplexer */
	302	#define I2C_MUX_PCA_ADDR 0x70
	303	#define I2C_MUX_CH_DEFAULT 0x8
f4c3917a	304
78e56995 YS	305	#if defined(CONFIG_TARGET_T1042RDB_PI) \|\| \
	306	defined(CONFIG_TARGET_T1040D4RDB) \|\| \
	307	defined(CONFIG_TARGET_T1042D4RDB)
cf8ddacf JJ	308	/* LDI/DVI Encoder for display */
	309	#define CONFIG_SYS_I2C_LDI_ADDR 0x38
	310	#define CONFIG_SYS_I2C_DVI_ADDR 0x75
d2e3f7c6	311	#define CONFIG_SYS_I2C_DVI_BUS_NUM 0
cf8ddacf	312
f4c3917a	313	/*
	314	* RTC configuration
	315	*/
	316	#define RTC
	317	#define CONFIG_RTC_DS1337 1
	318	#define CONFIG_SYS_I2C_RTC_ADDR 0x68
062ef1a6	319
f4c3917a	320	/DVI encoder/
	321	#define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75
	322	#endif
062ef1a6 PJ	323
	324	/*
	325	* eSPI - Enhanced SPI
	326	*/
062ef1a6 PJ	327
	328	/*
	329	* General PCI
	330	* Memory space is mapped 1-1, but I/O space must start from 0.
	331	*/
	332
	333	#ifdef CONFIG_PCI
	334	/* controller 1, direct to uli, tgtid 3, Base address 20000 */
	335	#ifdef CONFIG_PCIE1
	336	#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
062ef1a6	337	#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
062ef1a6	338	#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
062ef1a6	339	#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
062ef1a6 PJ	340	#endif
	341
	342	/* controller 2, Slot 2, tgtid 2, Base address 201000 */
	343	#ifdef CONFIG_PCIE2
	344	#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
062ef1a6	345	#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
062ef1a6	346	#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
062ef1a6	347	#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
062ef1a6 PJ	348	#endif
	349
	350	/* controller 3, Slot 1, tgtid 1, Base address 202000 */
	351	#ifdef CONFIG_PCIE3
	352	#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
062ef1a6	353	#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
062ef1a6	354	#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
062ef1a6	355	#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
062ef1a6 PJ	356	#endif
	357
	358	/* controller 4, Base address 203000 */
	359	#ifdef CONFIG_PCIE4
	360	#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
062ef1a6	361	#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
062ef1a6	362	#define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
062ef1a6	363	#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
062ef1a6 PJ	364	#endif
062ef1a6 PJ	365
062ef1a6	366	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
062ef1a6 PJ	367	#endif /* CONFIG_PCI */
062ef1a6 PJ	368
062ef1a6 PJ	369	/*
	370	* USB
	371	*/
062ef1a6	372
062ef1a6	373	#ifdef CONFIG_MMC
062ef1a6	374	#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
062ef1a6 PJ	375	#endif
	376
	377	/* Qman/Bman */
	378	#ifndef CONFIG_NOBQFMAN
2a8b3422	379	#define CONFIG_SYS_BMAN_NUM_PORTALS 10
062ef1a6 PJ	380	#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
	381	#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
	382	#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
3fa66db4 JL	383	#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
	384	#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
	385	#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
	386	#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
	387	#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
	388	CONFIG_SYS_BMAN_CENA_SIZE)
	389	#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
	390	#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
2a8b3422	391	#define CONFIG_SYS_QMAN_NUM_PORTALS 10
062ef1a6 PJ	392	#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
	393	#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
	394	#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
3fa66db4 JL	395	#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
	396	#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
	397	#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
	398	#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
	399	#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
	400	CONFIG_SYS_QMAN_CENA_SIZE)
	401	#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
	402	#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
062ef1a6 PJ	403
	404	#define CONFIG_SYS_DPAA_FMAN
	405	#define CONFIG_SYS_DPAA_PME
	406
062ef1a6 PJ	407	#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
	408	#endif /* CONFIG_NOBQFMAN */
	409
062ef1a6	410	#ifdef CONFIG_FMAN_ENET
0167369c	411	#if defined(CONFIG_TARGET_T1040RDB) \|\| defined(CONFIG_TARGET_T1042RDB)
4b6067ae	412	#define CONFIG_SYS_SGMII1_PHY_ADDR 0x03
a016735c	413	#elif defined(CONFIG_TARGET_T1040D4RDB)
94af6842	414	#define CONFIG_SYS_SGMII1_PHY_ADDR 0x01
319ed24a	415	#elif defined(CONFIG_TARGET_T1042D4RDB)
4b6067ae PJ	416	#define CONFIG_SYS_SGMII1_PHY_ADDR 0x02
	417	#define CONFIG_SYS_SGMII2_PHY_ADDR 0x03
	418	#define CONFIG_SYS_SGMII3_PHY_ADDR 0x01
	419	#endif
	420
78e56995	421	#if defined(CONFIG_TARGET_T1040D4RDB) \|\| defined(CONFIG_TARGET_T1042D4RDB)
4b6067ae PJ	422	#define CONFIG_SYS_RGMII1_PHY_ADDR 0x04
	423	#define CONFIG_SYS_RGMII2_PHY_ADDR 0x05
	424	#else
	425	#define CONFIG_SYS_RGMII1_PHY_ADDR 0x01
	426	#define CONFIG_SYS_RGMII2_PHY_ADDR 0x02
f4c3917a	427	#endif
062ef1a6	428
db4a1767	429	/* Enable VSC9953 L2 Switch driver on T1040 SoC */
6fcddd09	430	#if defined(CONFIG_TARGET_T1040RDB) \|\| defined(CONFIG_TARGET_T1040D4RDB)
db4a1767	431	#define CONFIG_VSC9953
6fcddd09	432	#ifdef CONFIG_TARGET_T1040RDB
db4a1767 CC	433	#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04
db4a1767 CC	434	#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08
4b6067ae PJ	435	#else
	436	#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08
	437	#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c
	438	#endif
db4a1767	439	#endif
062ef1a6 PJ	440	#endif
	441
	442	/*
	443	* Environment
	444	*/
	445	#define CONFIG_LOADS_ECHO /* echo on for serial download */
	446	#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
	447
062ef1a6 PJ	448	/*
	449	* Miscellaneous configurable options
	450	*/
062ef1a6 PJ	451
	452	/*
	453	* For booting Linux, the board info and command line data
	454	* have to be in the first 64 MB of memory, since this is
	455	* the maximum mapped by the Linux kernel during initialization.
	456	*/
	457	#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
	458	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
	459
68b74739 PK	460	/*
	461	* Dynamic MTD Partition support with mtdparts
	462	*/
68b74739	463
062ef1a6 PJ	464	/*
	465	* Environment Configuration
	466	*/
	467	#define CONFIG_ROOTPATH "/opt/nfsroot"
062ef1a6 PJ	468	#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
062ef1a6 PJ	469
062ef1a6	470	#define __USB_PHY_TYPE utmi
363fb32a	471	#define RAMDISKFILE "t104xrdb/ramdisk.uboot"
062ef1a6	472
6fcddd09	473	#ifdef CONFIG_TARGET_T1040RDB
f4c3917a	474	#define FDTFILE "t1040rdb/t1040rdb.dtb"
55ed8ae3	475	#elif defined(CONFIG_TARGET_T1042RDB_PI)
363fb32a	476	#define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb"
0167369c	477	#elif defined(CONFIG_TARGET_T1042RDB)
363fb32a	478	#define FDTFILE "t1042rdb/t1042rdb.dtb"
a016735c	479	#elif defined(CONFIG_TARGET_T1040D4RDB)
4b6067ae	480	#define FDTFILE "t1042rdb/t1040d4rdb.dtb"
319ed24a	481	#elif defined(CONFIG_TARGET_T1042D4RDB)
4b6067ae	482	#define FDTFILE "t1042rdb/t1042d4rdb.dtb"
f4c3917a	483	#endif
f4c3917a	484
062ef1a6	485	#define CONFIG_EXTRA_ENV_SETTINGS \
9b444be3 PJ	486	"hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \
	487	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
	488	"usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
062ef1a6 PJ	489	"netdev=eth0\0" \
	490	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
	491	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
	492	"tftpflash=tftpboot $loadaddr $uboot && " \
	493	"protect off $ubootaddr +$filesize && " \
	494	"erase $ubootaddr +$filesize && " \
	495	"cp.b $loadaddr $ubootaddr $filesize && " \
	496	"protect on $ubootaddr +$filesize && " \
	497	"cmp.b $loadaddr $ubootaddr $filesize\0" \
	498	"consoledev=ttyS0\0" \
	499	"ramdiskaddr=2000000\0" \
f4c3917a	500	"ramdiskfile=" __stringify(RAMDISKFILE) "\0" \
b24a4f62	501	"fdtaddr=1e00000\0" \
f4c3917a	502	"fdtfile=" __stringify(FDTFILE) "\0" \
3246584d	503	"bdev=sda3\0"
062ef1a6	504
062ef1a6	505	#include <asm/fsl_secure_boot.h>
ef6c55a2	506
062ef1a6	507	#endif /* __CONFIG_H */