[J-u-boot.git] / drivers / mmc / bfin_sdh.c

/*
 * Driver for Blackfin on-chip SDH controller
 *
 * Copyright (c) 2008-2009 Analog Devices Inc.
 *
 * Licensed under the GPL-2 or later.
 */

#include <common.h>
#include <malloc.h>
#include <part.h>
#include <mmc.h>

#include <asm/io.h>
#include <asm/errno.h>
#include <asm/byteorder.h>
#include <asm/blackfin.h>
#include <asm/clock.h>
#include <asm/portmux.h>
#include <asm/mach-common/bits/sdh.h>
#include <asm/mach-common/bits/dma.h>

#if defined(__ADSPBF50x__) || defined(__ADSPBF51x__) || defined(__ADSPBF60x__)
# define bfin_read_SDH_CLK_CTL		bfin_read_RSI_CLK_CONTROL
# define bfin_write_SDH_CLK_CTL		bfin_write_RSI_CLK_CONTROL
# define bfin_write_SDH_ARGUMENT	bfin_write_RSI_ARGUMENT
# define bfin_write_SDH_COMMAND		bfin_write_RSI_COMMAND
# define bfin_read_SDH_RESPONSE0	bfin_read_RSI_RESPONSE0
# define bfin_read_SDH_RESPONSE1	bfin_read_RSI_RESPONSE1
# define bfin_read_SDH_RESPONSE2	bfin_read_RSI_RESPONSE2
# define bfin_read_SDH_RESPONSE3	bfin_read_RSI_RESPONSE3
# define bfin_write_SDH_DATA_TIMER	bfin_write_RSI_DATA_TIMER
# define bfin_write_SDH_DATA_LGTH	bfin_write_RSI_DATA_LGTH
# define bfin_read_SDH_DATA_CTL		bfin_read_RSI_DATA_CONTROL
# define bfin_write_SDH_DATA_CTL	bfin_write_RSI_DATA_CONTROL
# define bfin_read_SDH_STATUS		bfin_read_RSI_STATUS
# define bfin_write_SDH_STATUS_CLR 	bfin_write_RSI_STATUSCL
# define bfin_read_SDH_CFG		bfin_read_RSI_CONFIG
# define bfin_write_SDH_CFG		bfin_write_RSI_CONFIG
# if defined(__ADSPBF60x__)
# define bfin_read_SDH_BLK_SIZE		bfin_read_RSI_BLKSZ
# define bfin_write_SDH_BLK_SIZE	bfin_write_RSI_BLKSZ
# define bfin_write_DMA_START_ADDR	bfin_write_DMA10_START_ADDR
# define bfin_write_DMA_X_COUNT		bfin_write_DMA10_X_COUNT
# define bfin_write_DMA_X_MODIFY	bfin_write_DMA10_X_MODIFY
# define bfin_write_DMA_CONFIG		bfin_write_DMA10_CONFIG
# else
# define bfin_read_SDH_PWR_CTL		bfin_read_RSI_PWR_CONTROL
# define bfin_write_SDH_PWR_CTL		bfin_write_RSI_PWR_CONTROL
# define bfin_write_DMA_START_ADDR	bfin_write_DMA4_START_ADDR
# define bfin_write_DMA_X_COUNT		bfin_write_DMA4_X_COUNT
# define bfin_write_DMA_X_MODIFY	bfin_write_DMA4_X_MODIFY
# define bfin_write_DMA_CONFIG		bfin_write_DMA4_CONFIG
# endif
# define PORTMUX_PINS \
	{ P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0 }
#elif defined(__ADSPBF54x__)
# define bfin_write_DMA_START_ADDR	bfin_write_DMA22_START_ADDR
# define bfin_write_DMA_X_COUNT		bfin_write_DMA22_X_COUNT
# define bfin_write_DMA_X_MODIFY	bfin_write_DMA22_X_MODIFY
# define bfin_write_DMA_CONFIG		bfin_write_DMA22_CONFIG
# define PORTMUX_PINS \
	{ P_SD_D0, P_SD_D1, P_SD_D2, P_SD_D3, P_SD_CLK, P_SD_CMD, 0 }
#else
# error no support for this proc yet
#endif

static int
sdh_send_cmd(struct mmc *mmc, struct mmc_cmd *mmc_cmd)
{
	unsigned int status, timeout;
	int cmd = mmc_cmd->cmdidx;
	int flags = mmc_cmd->resp_type;
	int arg = mmc_cmd->cmdarg;
	int ret;
	u16 sdh_cmd;

	sdh_cmd = cmd | CMD_E;
	if (flags & MMC_RSP_PRESENT)
		sdh_cmd |= CMD_RSP;
	if (flags & MMC_RSP_136)
		sdh_cmd |= CMD_L_RSP;
#ifdef RSI_BLKSZ
	sdh_cmd |= CMD_DATA0_BUSY;
#endif

	bfin_write_SDH_ARGUMENT(arg);
	bfin_write_SDH_COMMAND(sdh_cmd);

	/* wait for a while */
	timeout = 0;
	do {
		if (++timeout > 1000000) {
			status = CMD_TIME_OUT;
			break;
		}
		udelay(1);
		status = bfin_read_SDH_STATUS();
	} while (!(status & (CMD_SENT | CMD_RESP_END | CMD_TIME_OUT |
		CMD_CRC_FAIL)));

	if (flags & MMC_RSP_PRESENT) {
		mmc_cmd->response[0] = bfin_read_SDH_RESPONSE0();
		if (flags & MMC_RSP_136) {
			mmc_cmd->response[1] = bfin_read_SDH_RESPONSE1();
			mmc_cmd->response[2] = bfin_read_SDH_RESPONSE2();
			mmc_cmd->response[3] = bfin_read_SDH_RESPONSE3();
		}
	}

	if (status & CMD_TIME_OUT)
		ret = TIMEOUT;
	else if (status & CMD_CRC_FAIL && flags & MMC_RSP_CRC)
		ret = COMM_ERR;
	else
		ret = 0;

	bfin_write_SDH_STATUS_CLR(CMD_SENT_STAT | CMD_RESP_END_STAT |
				CMD_TIMEOUT_STAT | CMD_CRC_FAIL_STAT);
#ifdef RSI_BLKSZ
	/* wait till card ready */
	while (!(bfin_read_RSI_ESTAT() & SD_CARD_READY))
		continue;
	bfin_write_RSI_ESTAT(SD_CARD_READY);
#endif

	return ret;
}

/* set data for single block transfer */
static int sdh_setup_data(struct mmc *mmc, struct mmc_data *data)
{
	u16 data_ctl = 0;
	u16 dma_cfg = 0;
	unsigned long data_size = data->blocksize * data->blocks;

	/* Don't support write yet. */
	if (data->flags & MMC_DATA_WRITE)
		return UNUSABLE_ERR;
#ifndef RSI_BLKSZ
	data_ctl |= ((ffs(data->blocksize) - 1) << 4);
#else
	bfin_write_SDH_BLK_SIZE(data->blocksize);
#endif
	data_ctl |= DTX_DIR;
	bfin_write_SDH_DATA_CTL(data_ctl);
	dma_cfg = WDSIZE_32 | PSIZE_32 | RESTART | WNR | DMAEN;

	bfin_write_SDH_DATA_TIMER(-1);

	blackfin_dcache_flush_invalidate_range(data->dest,
			data->dest + data_size);
	/* configure DMA */
	bfin_write_DMA_START_ADDR(data->dest);
	bfin_write_DMA_X_COUNT(data_size / 4);
	bfin_write_DMA_X_MODIFY(4);
	bfin_write_DMA_CONFIG(dma_cfg);
	bfin_write_SDH_DATA_LGTH(data_size);
	/* kick off transfer */
	bfin_write_SDH_DATA_CTL(bfin_read_SDH_DATA_CTL() | DTX_DMA_E | DTX_E);

	return 0;
}


static int bfin_sdh_request(struct mmc *mmc, struct mmc_cmd *cmd,
		struct mmc_data *data)
{
	u32 status;
	int ret = 0;

	if (data) {
		ret = sdh_setup_data(mmc, data);
		if (ret)
			return ret;
	}

	ret = sdh_send_cmd(mmc, cmd);
	if (ret) {
		bfin_write_SDH_COMMAND(0);
		bfin_write_DMA_CONFIG(0);
		bfin_write_SDH_DATA_CTL(0);
		SSYNC();
		printf("sending CMD%d failed\n", cmd->cmdidx);
		return ret;
	}

	if (data) {
		do {
			udelay(1);
			status = bfin_read_SDH_STATUS();
		} while (!(status & (DAT_END | DAT_TIME_OUT | DAT_CRC_FAIL |
			 RX_OVERRUN)));

		if (status & DAT_TIME_OUT) {
			bfin_write_SDH_STATUS_CLR(DAT_TIMEOUT_STAT);
			ret |= TIMEOUT;
		} else if (status & (DAT_CRC_FAIL | RX_OVERRUN)) {
			bfin_write_SDH_STATUS_CLR(DAT_CRC_FAIL_STAT | RX_OVERRUN_STAT);
			ret |= COMM_ERR;
		} else
			bfin_write_SDH_STATUS_CLR(DAT_BLK_END_STAT | DAT_END_STAT);

		if (ret) {
			printf("tranfering data failed\n");
			return ret;
		}
	}
	return 0;
}

static void sdh_set_clk(unsigned long clk)
{
	unsigned long sys_clk;
	unsigned long clk_div;
	u16 clk_ctl = 0;

	clk_ctl = bfin_read_SDH_CLK_CTL();
	if (clk) {
		/* setting SD_CLK */
		sys_clk = get_sclk();
		bfin_write_SDH_CLK_CTL(clk_ctl & ~CLK_E);
		if (sys_clk % (2 * clk) == 0)
			clk_div = sys_clk / (2 * clk) - 1;
		else
			clk_div = sys_clk / (2 * clk);

		if (clk_div > 0xff)
			clk_div = 0xff;
		clk_ctl |= (clk_div & 0xff);
		clk_ctl |= CLK_E;
		bfin_write_SDH_CLK_CTL(clk_ctl);
	} else
		bfin_write_SDH_CLK_CTL(clk_ctl & ~CLK_E);
}

static void bfin_sdh_set_ios(struct mmc *mmc)
{
	u16 cfg = 0;
	u16 clk_ctl = 0;

	if (mmc->bus_width == 4) {
		cfg = bfin_read_SDH_CFG();
#ifndef RSI_BLKSZ
		cfg &= ~PD_SDDAT3;
#endif
		cfg |= PUP_SDDAT3;
		bfin_write_SDH_CFG(cfg);
		clk_ctl |= WIDE_BUS_4;
	}
	bfin_write_SDH_CLK_CTL(clk_ctl);
	sdh_set_clk(mmc->clock);
}

static int bfin_sdh_init(struct mmc *mmc)
{
	const unsigned short pins[] = PORTMUX_PINS;
	int ret;

	/* Initialize sdh controller */
	ret = peripheral_request_list(pins, "bfin_sdh");
	if (ret < 0)
		return ret;
#if defined(__ADSPBF54x__)
	bfin_write_DMAC1_PERIMUX(bfin_read_DMAC1_PERIMUX() | 0x1);
#endif
	bfin_write_SDH_CFG(bfin_read_SDH_CFG() | CLKS_EN);
	/* Disable card detect pin */
	bfin_write_SDH_CFG((bfin_read_SDH_CFG() & 0x1F) | 0x60);
#ifndef RSI_BLKSZ
	bfin_write_SDH_PWR_CTL(PWR_ON | ROD_CTL);
#else
	bfin_write_SDH_CFG(bfin_read_SDH_CFG() | PWR_ON);
#endif
	return 0;
}

static const struct mmc_ops bfin_mmc_ops = {
	.send_cmd	= bfin_sdh_request,
	.set_ios	= bfin_sdh_set_ios,
	.init		= bfin_sdh_init,
};

static struct mmc_config bfin_mmc_cfg = {
	.name		= "Blackfin SDH",
	.ops		= &bfin_mmc_ops,
	.host_caps	= MMC_MODE_4BIT,
	.voltages	= MMC_VDD_32_33 | MMC_VDD_33_34,
	.b_max		= CONFIG_SYS_MMC_MAX_BLK_COUNT,
};

int bfin_mmc_init(bd_t *bis)
{
	struct mmc *mmc;

	bfin_mmc_cfg.f_max = get_sclk();
	bfin_mmc_cfg.f_min = bfin_mmc_cfg.f_max >> 9;

	mmc = mmc_create(&bfin_mmc_cfg, NULL);
	if (mmc == NULL)
		return -1;

	return 0;
}
Commit	Line	Data
716ebf43 CC	1	/*
	2	* Driver for Blackfin on-chip SDH controller
	3	*
e54c8209	4	* Copyright (c) 2008-2009 Analog Devices Inc.
716ebf43 CC	5	*
	6	* Licensed under the GPL-2 or later.
	7	*/
	8
	9	#include <common.h>
	10	#include <malloc.h>
	11	#include <part.h>
	12	#include <mmc.h>
	13
	14	#include <asm/io.h>
	15	#include <asm/errno.h>
	16	#include <asm/byteorder.h>
	17	#include <asm/blackfin.h>
130fbeb1	18	#include <asm/clock.h>
a87589fc	19	#include <asm/portmux.h>
716ebf43 CC	20	#include <asm/mach-common/bits/sdh.h>
	21	#include <asm/mach-common/bits/dma.h>
	22
187f32fa	23	#if defined(__ADSPBF50x__) \|\| defined(__ADSPBF51x__) \|\| defined(__ADSPBF60x__)
716ebf43 CC	24	# define bfin_read_SDH_CLK_CTL bfin_read_RSI_CLK_CONTROL
	25	# define bfin_write_SDH_CLK_CTL bfin_write_RSI_CLK_CONTROL
	26	# define bfin_write_SDH_ARGUMENT bfin_write_RSI_ARGUMENT
	27	# define bfin_write_SDH_COMMAND bfin_write_RSI_COMMAND
	28	# define bfin_read_SDH_RESPONSE0 bfin_read_RSI_RESPONSE0
	29	# define bfin_read_SDH_RESPONSE1 bfin_read_RSI_RESPONSE1
	30	# define bfin_read_SDH_RESPONSE2 bfin_read_RSI_RESPONSE2
	31	# define bfin_read_SDH_RESPONSE3 bfin_read_RSI_RESPONSE3
	32	# define bfin_write_SDH_DATA_TIMER bfin_write_RSI_DATA_TIMER
	33	# define bfin_write_SDH_DATA_LGTH bfin_write_RSI_DATA_LGTH
	34	# define bfin_read_SDH_DATA_CTL bfin_read_RSI_DATA_CONTROL
	35	# define bfin_write_SDH_DATA_CTL bfin_write_RSI_DATA_CONTROL
	36	# define bfin_read_SDH_STATUS bfin_read_RSI_STATUS
	37	# define bfin_write_SDH_STATUS_CLR bfin_write_RSI_STATUSCL
	38	# define bfin_read_SDH_CFG bfin_read_RSI_CONFIG
	39	# define bfin_write_SDH_CFG bfin_write_RSI_CONFIG
187f32fa SZ	40	# if defined(__ADSPBF60x__)
	41	# define bfin_read_SDH_BLK_SIZE bfin_read_RSI_BLKSZ
	42	# define bfin_write_SDH_BLK_SIZE bfin_write_RSI_BLKSZ
	43	# define bfin_write_DMA_START_ADDR bfin_write_DMA10_START_ADDR
	44	# define bfin_write_DMA_X_COUNT bfin_write_DMA10_X_COUNT
	45	# define bfin_write_DMA_X_MODIFY bfin_write_DMA10_X_MODIFY
	46	# define bfin_write_DMA_CONFIG bfin_write_DMA10_CONFIG
	47	# else
	48	# define bfin_read_SDH_PWR_CTL bfin_read_RSI_PWR_CONTROL
	49	# define bfin_write_SDH_PWR_CTL bfin_write_RSI_PWR_CONTROL
716ebf43 CC	50	# define bfin_write_DMA_START_ADDR bfin_write_DMA4_START_ADDR
	51	# define bfin_write_DMA_X_COUNT bfin_write_DMA4_X_COUNT
	52	# define bfin_write_DMA_X_MODIFY bfin_write_DMA4_X_MODIFY
	53	# define bfin_write_DMA_CONFIG bfin_write_DMA4_CONFIG
187f32fa	54	# endif
a87589fc MF	55	# define PORTMUX_PINS \
a87589fc MF	56	{ P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0 }
716ebf43 CC	57	#elif defined(__ADSPBF54x__)
	58	# define bfin_write_DMA_START_ADDR bfin_write_DMA22_START_ADDR
	59	# define bfin_write_DMA_X_COUNT bfin_write_DMA22_X_COUNT
	60	# define bfin_write_DMA_X_MODIFY bfin_write_DMA22_X_MODIFY
	61	# define bfin_write_DMA_CONFIG bfin_write_DMA22_CONFIG
a87589fc MF	62	# define PORTMUX_PINS \
a87589fc MF	63	{ P_SD_D0, P_SD_D1, P_SD_D2, P_SD_D3, P_SD_CLK, P_SD_CMD, 0 }
716ebf43 CC	64	#else
	65	# error no support for this proc yet
	66	#endif
	67
716ebf43	68	static int
e54c8209	69	sdh_send_cmd(struct mmc mmc, struct mmc_cmd mmc_cmd)
716ebf43	70	{
6815f540	71	unsigned int status, timeout;
e54c8209 CC	72	int cmd = mmc_cmd->cmdidx;
	73	int flags = mmc_cmd->resp_type;
	74	int arg = mmc_cmd->cmdarg;
6815f540 MF	75	int ret;
6815f540 MF	76	u16 sdh_cmd;
716ebf43	77
6815f540	78	sdh_cmd = cmd \| CMD_E;
716ebf43 CC	79	if (flags & MMC_RSP_PRESENT)
716ebf43 CC	80	sdh_cmd \|= CMD_RSP;
716ebf43 CC	81	if (flags & MMC_RSP_136)
716ebf43 CC	82	sdh_cmd \|= CMD_L_RSP;
187f32fa SZ	83	#ifdef RSI_BLKSZ
	84	sdh_cmd \|= CMD_DATA0_BUSY;
	85	#endif
716ebf43 CC	86
716ebf43 CC	87	bfin_write_SDH_ARGUMENT(arg);
6815f540	88	bfin_write_SDH_COMMAND(sdh_cmd);
716ebf43 CC	89
716ebf43 CC	90	/* wait for a while */
6815f540	91	timeout = 0;
716ebf43	92	do {
6815f540 MF	93	if (++timeout > 1000000) {
	94	status = CMD_TIME_OUT;
	95	break;
	96	}
716ebf43 CC	97	udelay(1);
	98	status = bfin_read_SDH_STATUS();
	99	} while (!(status & (CMD_SENT \| CMD_RESP_END \| CMD_TIME_OUT \|
	100	CMD_CRC_FAIL)));
	101
	102	if (flags & MMC_RSP_PRESENT) {
e54c8209	103	mmc_cmd->response[0] = bfin_read_SDH_RESPONSE0();
716ebf43	104	if (flags & MMC_RSP_136) {
e54c8209 CC	105	mmc_cmd->response[1] = bfin_read_SDH_RESPONSE1();
	106	mmc_cmd->response[2] = bfin_read_SDH_RESPONSE2();
	107	mmc_cmd->response[3] = bfin_read_SDH_RESPONSE3();
716ebf43 CC	108	}
	109	}
	110
e54c8209	111	if (status & CMD_TIME_OUT)
6815f540	112	ret = TIMEOUT;
e54c8209	113	else if (status & CMD_CRC_FAIL && flags & MMC_RSP_CRC)
6815f540 MF	114	ret = COMM_ERR;
	115	else
	116	ret = 0;
e54c8209	117
716ebf43 CC	118	bfin_write_SDH_STATUS_CLR(CMD_SENT_STAT \| CMD_RESP_END_STAT \|
716ebf43 CC	119	CMD_TIMEOUT_STAT \| CMD_CRC_FAIL_STAT);
187f32fa SZ	120	#ifdef RSI_BLKSZ
	121	/* wait till card ready */
	122	while (!(bfin_read_RSI_ESTAT() & SD_CARD_READY))
	123	continue;
	124	bfin_write_RSI_ESTAT(SD_CARD_READY);
	125	#endif
6815f540	126
716ebf43 CC	127	return ret;
	128	}
	129
e54c8209 CC	130	/* set data for single block transfer */
e54c8209 CC	131	static int sdh_setup_data(struct mmc mmc, struct mmc_data data)
716ebf43	132	{
e54c8209 CC	133	u16 data_ctl = 0;
e54c8209 CC	134	u16 dma_cfg = 0;
21a50374	135	unsigned long data_size = data->blocksize * data->blocks;
716ebf43	136
e54c8209 CC	137	/* Don't support write yet. */
	138	if (data->flags & MMC_DATA_WRITE)
	139	return UNUSABLE_ERR;
187f32fa	140	#ifndef RSI_BLKSZ
282a82e8	141	data_ctl \|= ((ffs(data->blocksize) - 1) << 4);
187f32fa	142	#else
282a82e8	143	bfin_write_SDH_BLK_SIZE(data->blocksize);
187f32fa	144	#endif
716ebf43 CC	145	data_ctl \|= DTX_DIR;
716ebf43 CC	146	bfin_write_SDH_DATA_CTL(data_ctl);
187f32fa	147	dma_cfg = WDSIZE_32 \| PSIZE_32 \| RESTART \| WNR \| DMAEN;
716ebf43	148
1fd2d792	149	bfin_write_SDH_DATA_TIMER(-1);
716ebf43	150
e54c8209	151	blackfin_dcache_flush_invalidate_range(data->dest,
21a50374	152	data->dest + data_size);
e54c8209 CC	153	/* configure DMA */
e54c8209 CC	154	bfin_write_DMA_START_ADDR(data->dest);
21a50374	155	bfin_write_DMA_X_COUNT(data_size / 4);
e54c8209 CC	156	bfin_write_DMA_X_MODIFY(4);
e54c8209 CC	157	bfin_write_DMA_CONFIG(dma_cfg);
21a50374	158	bfin_write_SDH_DATA_LGTH(data_size);
e54c8209 CC	159	/* kick off transfer */
e54c8209 CC	160	bfin_write_SDH_DATA_CTL(bfin_read_SDH_DATA_CTL() \| DTX_DMA_E \| DTX_E);
716ebf43	161
187f32fa	162	return 0;
716ebf43 CC	163	}
716ebf43 CC	164
e54c8209 CC	165
	166	static int bfin_sdh_request(struct mmc mmc, struct mmc_cmd cmd,
	167	struct mmc_data *data)
716ebf43	168	{
e54c8209 CC	169	u32 status;
e54c8209 CC	170	int ret = 0;
716ebf43	171
187f32fa SZ	172	if (data) {
	173	ret = sdh_setup_data(mmc, data);
	174	if (ret)
	175	return ret;
	176	}
	177
e54c8209 CC	178	ret = sdh_send_cmd(mmc, cmd);
e54c8209 CC	179	if (ret) {
187f32fa SZ	180	bfin_write_SDH_COMMAND(0);
	181	bfin_write_DMA_CONFIG(0);
	182	bfin_write_SDH_DATA_CTL(0);
	183	SSYNC();
e54c8209 CC	184	printf("sending CMD%d failed\n", cmd->cmdidx);
	185	return ret;
	186	}
187f32fa	187
e54c8209	188	if (data) {
716ebf43 CC	189	do {
	190	udelay(1);
	191	status = bfin_read_SDH_STATUS();
282a82e8 SZ	192	} while (!(status & (DAT_END \| DAT_TIME_OUT \| DAT_CRC_FAIL \|
282a82e8 SZ	193	RX_OVERRUN)));
716ebf43	194
e54c8209 CC	195	if (status & DAT_TIME_OUT) {
	196	bfin_write_SDH_STATUS_CLR(DAT_TIMEOUT_STAT);
	197	ret \|= TIMEOUT;
	198	} else if (status & (DAT_CRC_FAIL \| RX_OVERRUN)) {
	199	bfin_write_SDH_STATUS_CLR(DAT_CRC_FAIL_STAT \| RX_OVERRUN_STAT);
	200	ret \|= COMM_ERR;
	201	} else
716ebf43	202	bfin_write_SDH_STATUS_CLR(DAT_BLK_END_STAT \| DAT_END_STAT);
e54c8209 CC	203
	204	if (ret) {
	205	printf("tranfering data failed\n");
	206	return ret;
716ebf43 CC	207	}
716ebf43 CC	208	}
e54c8209	209	return 0;
716ebf43 CC	210	}
716ebf43 CC	211
e54c8209	212	static void sdh_set_clk(unsigned long clk)
716ebf43	213	{
e54c8209 CC	214	unsigned long sys_clk;
	215	unsigned long clk_div;
	216	u16 clk_ctl = 0;
	217
	218	clk_ctl = bfin_read_SDH_CLK_CTL();
	219	if (clk) {
	220	/* setting SD_CLK */
	221	sys_clk = get_sclk();
	222	bfin_write_SDH_CLK_CTL(clk_ctl & ~CLK_E);
	223	if (sys_clk % (2 * clk) == 0)
	224	clk_div = sys_clk / (2 * clk) - 1;
	225	else
	226	clk_div = sys_clk / (2 * clk);
	227
	228	if (clk_div > 0xff)
	229	clk_div = 0xff;
	230	clk_ctl \|= (clk_div & 0xff);
	231	clk_ctl \|= CLK_E;
	232	bfin_write_SDH_CLK_CTL(clk_ctl);
	233	} else
	234	bfin_write_SDH_CLK_CTL(clk_ctl & ~CLK_E);
716ebf43 CC	235	}
716ebf43 CC	236
e54c8209	237	static void bfin_sdh_set_ios(struct mmc *mmc)
716ebf43	238	{
e54c8209 CC	239	u16 cfg = 0;
	240	u16 clk_ctl = 0;
	241
0b2da7e2	242	if (mmc->bus_width == 4) {
e54c8209	243	cfg = bfin_read_SDH_CFG();
187f32fa SZ	244	#ifndef RSI_BLKSZ
	245	cfg &= ~PD_SDDAT3;
	246	#endif
	247	cfg \|= PUP_SDDAT3;
e54c8209	248	bfin_write_SDH_CFG(cfg);
187f32fa	249	clk_ctl \|= WIDE_BUS_4;
716ebf43	250	}
e54c8209 CC	251	bfin_write_SDH_CLK_CTL(clk_ctl);
e54c8209 CC	252	sdh_set_clk(mmc->clock);
716ebf43 CC	253	}
716ebf43 CC	254
e54c8209	255	static int bfin_sdh_init(struct mmc *mmc)
716ebf43	256	{
a87589fc	257	const unsigned short pins[] = PORTMUX_PINS;
187f32fa	258	int ret;
a87589fc MF	259
a87589fc MF	260	/* Initialize sdh controller */
187f32fa SZ	261	ret = peripheral_request_list(pins, "bfin_sdh");
	262	if (ret < 0)
	263	return ret;
716ebf43 CC	264	#if defined(__ADSPBF54x__)
716ebf43 CC	265	bfin_write_DMAC1_PERIMUX(bfin_read_DMAC1_PERIMUX() \| 0x1);
716ebf43 CC	266	#endif
	267	bfin_write_SDH_CFG(bfin_read_SDH_CFG() \| CLKS_EN);
	268	/* Disable card detect pin */
	269	bfin_write_SDH_CFG((bfin_read_SDH_CFG() & 0x1F) \| 0x60);
187f32fa SZ	270	#ifndef RSI_BLKSZ
	271	bfin_write_SDH_PWR_CTL(PWR_ON \| ROD_CTL);
	272	#else
	273	bfin_write_SDH_CFG(bfin_read_SDH_CFG() \| PWR_ON);
	274	#endif
716ebf43 CC	275	return 0;
	276	}
	277
ab769f22 PA	278	static const struct mmc_ops bfin_mmc_ops = {
	279	.send_cmd = bfin_sdh_request,
	280	.set_ios = bfin_sdh_set_ios,
	281	.init = bfin_sdh_init,
	282	};
e54c8209	283
93bfd616 PA	284	static struct mmc_config bfin_mmc_cfg = {
	285	.name = "Blackfin SDH",
	286	.ops = &bfin_mmc_ops,
	287	.host_caps = MMC_MODE_4BIT,
	288	.voltages = MMC_VDD_32_33 \| MMC_VDD_33_34,
	289	.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
	290	};
	291
e54c8209	292	int bfin_mmc_init(bd_t *bis)
716ebf43	293	{
93bfd616	294	struct mmc *mmc;
e54c8209	295
93bfd616 PA	296	bfin_mmc_cfg.f_max = get_sclk();
93bfd616 PA	297	bfin_mmc_cfg.f_min = bfin_mmc_cfg.f_max >> 9;
8feafcc4	298
93bfd616 PA	299	mmc = mmc_create(&bfin_mmc_cfg, NULL);
	300	if (mmc == NULL)
	301	return -1;
e54c8209	302
716ebf43 CC	303	return 0;
716ebf43 CC	304	}