[J-u-boot.git] / drivers / pci / pci_auto_old.c

/*
 * PCI autoconfiguration library (legacy version, do not change)
 *
 * Author: Matt Porter <[email protected]>
 *
 * Copyright 2000 MontaVista Software Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <errno.h>
#include <pci.h>

/*
 * Do not change this file. Instead, convert your board to use CONFIG_DM_PCI
 * and change pci_auto.c.
 */

/* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
#ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE
#define CONFIG_SYS_PCI_CACHE_LINE_SIZE	8
#endif

/*
 *
 */

void pciauto_setup_device(struct pci_controller *hose,
			  pci_dev_t dev, int bars_num,
			  struct pci_region *mem,
			  struct pci_region *prefetch,
			  struct pci_region *io)
{
	u32 bar_response;
	pci_size_t bar_size;
	u16 cmdstat = 0;
	int bar, bar_nr = 0;
#ifndef CONFIG_PCI_ENUM_ONLY
	u8 header_type;
	int rom_addr;
	pci_addr_t bar_value;
	struct pci_region *bar_res;
	int found_mem64 = 0;
#endif
	u16 class;

	pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
	cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER;

	for (bar = PCI_BASE_ADDRESS_0;
		bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) {
		/* Tickle the BAR and get the response */
#ifndef CONFIG_PCI_ENUM_ONLY
		pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
#endif
		pci_hose_read_config_dword(hose, dev, bar, &bar_response);

		/* If BAR is not implemented go to the next BAR */
		if (!bar_response)
			continue;

#ifndef CONFIG_PCI_ENUM_ONLY
		found_mem64 = 0;
#endif

		/* Check the BAR type and set our address mask */
		if (bar_response & PCI_BASE_ADDRESS_SPACE) {
			bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK))
				   & 0xffff) + 1;
#ifndef CONFIG_PCI_ENUM_ONLY
			bar_res = io;
#endif

			debug("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ",
			      bar_nr, (unsigned long long)bar_size);
		} else {
			if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
			     PCI_BASE_ADDRESS_MEM_TYPE_64) {
				u32 bar_response_upper;
				u64 bar64;

#ifndef CONFIG_PCI_ENUM_ONLY
				pci_hose_write_config_dword(hose, dev, bar + 4,
					0xffffffff);
#endif
				pci_hose_read_config_dword(hose, dev, bar + 4,
					&bar_response_upper);

				bar64 = ((u64)bar_response_upper << 32) | bar_response;

				bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
#ifndef CONFIG_PCI_ENUM_ONLY
				found_mem64 = 1;
#endif
			} else {
				bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
			}
#ifndef CONFIG_PCI_ENUM_ONLY
			if (prefetch && (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH))
				bar_res = prefetch;
			else
				bar_res = mem;

			debug("PCI Autoconfig: BAR %d, %s, size=0x%llx, ",
			      bar_nr, bar_res == prefetch ? "Prf" : "Mem",
			      (unsigned long long)bar_size);
#endif
		}

#ifndef CONFIG_PCI_ENUM_ONLY
		if (pciauto_region_allocate(bar_res, bar_size, &bar_value) == 0) {
			/* Write it out and update our limit */
			pci_hose_write_config_dword(hose, dev, bar, (u32)bar_value);

			if (found_mem64) {
				bar += 4;
#ifdef CONFIG_SYS_PCI_64BIT
				pci_hose_write_config_dword(hose, dev, bar, (u32)(bar_value>>32));
#else
				/*
				 * If we are a 64-bit decoder then increment to the
				 * upper 32 bits of the bar and force it to locate
				 * in the lower 4GB of memory.
				 */
				pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
#endif
			}

		}
#endif
		cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
			PCI_COMMAND_IO : PCI_COMMAND_MEMORY;

		debug("\n");

		bar_nr++;
	}

#ifndef CONFIG_PCI_ENUM_ONLY
	/* Configure the expansion ROM address */
	pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
	header_type &= 0x7f;
	if (header_type != PCI_HEADER_TYPE_CARDBUS) {
		rom_addr = (header_type == PCI_HEADER_TYPE_NORMAL) ?
			   PCI_ROM_ADDRESS : PCI_ROM_ADDRESS1;
		pci_hose_write_config_dword(hose, dev, rom_addr, 0xfffffffe);
		pci_hose_read_config_dword(hose, dev, rom_addr, &bar_response);
		if (bar_response) {
			bar_size = -(bar_response & ~1);
			debug("PCI Autoconfig: ROM, size=%#x, ",
			      (unsigned int)bar_size);
			if (pciauto_region_allocate(mem, bar_size,
						    &bar_value) == 0) {
				pci_hose_write_config_dword(hose, dev, rom_addr,
							    bar_value);
			}
			cmdstat |= PCI_COMMAND_MEMORY;
			debug("\n");
		}
	}
#endif

	/* PCI_COMMAND_IO must be set for VGA device */
	pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
	if (class == PCI_CLASS_DISPLAY_VGA)
		cmdstat |= PCI_COMMAND_IO;

	pci_hose_write_config_word(hose, dev, PCI_COMMAND, cmdstat);
	pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE,
		CONFIG_SYS_PCI_CACHE_LINE_SIZE);
	pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
}

void pciauto_prescan_setup_bridge(struct pci_controller *hose,
					 pci_dev_t dev, int sub_bus)
{
	struct pci_region *pci_mem;
	struct pci_region *pci_prefetch;
	struct pci_region *pci_io;
	u16 cmdstat, prefechable_64;

	pci_mem = hose->pci_mem;
	pci_prefetch = hose->pci_prefetch;
	pci_io = hose->pci_io;

	pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
	pci_hose_read_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
				&prefechable_64);
	prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;

	/* Configure bus number registers */
	pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS,
				   PCI_BUS(dev) - hose->first_busno);
	pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS,
				   sub_bus - hose->first_busno);
	pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff);

	if (pci_mem) {
		/* Round memory allocator to 1MB boundary */
		pciauto_region_align(pci_mem, 0x100000);

		/* Set up memory and I/O filter limits, assume 32-bit I/O space */
		pci_hose_write_config_word(hose, dev, PCI_MEMORY_BASE,
					(pci_mem->bus_lower & 0xfff00000) >> 16);

		cmdstat |= PCI_COMMAND_MEMORY;
	}

	if (pci_prefetch) {
		/* Round memory allocator to 1MB boundary */
		pciauto_region_align(pci_prefetch, 0x100000);

		/* Set up memory and I/O filter limits, assume 32-bit I/O space */
		pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
					(pci_prefetch->bus_lower & 0xfff00000) >> 16);
		if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
#ifdef CONFIG_SYS_PCI_64BIT
			pci_hose_write_config_dword(hose, dev,
					PCI_PREF_BASE_UPPER32,
					pci_prefetch->bus_lower >> 32);
#else
			pci_hose_write_config_dword(hose, dev,
					PCI_PREF_BASE_UPPER32,
					0x0);
#endif

		cmdstat |= PCI_COMMAND_MEMORY;
	} else {
		/* We don't support prefetchable memory for now, so disable */
		pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000);
		pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x0);
		if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) {
			pci_hose_write_config_word(hose, dev, PCI_PREF_BASE_UPPER32, 0x0);
			pci_hose_write_config_word(hose, dev, PCI_PREF_LIMIT_UPPER32, 0x0);
		}
	}

	if (pci_io) {
		/* Round I/O allocator to 4KB boundary */
		pciauto_region_align(pci_io, 0x1000);

		pci_hose_write_config_byte(hose, dev, PCI_IO_BASE,
					(pci_io->bus_lower & 0x0000f000) >> 8);
		pci_hose_write_config_word(hose, dev, PCI_IO_BASE_UPPER16,
					(pci_io->bus_lower & 0xffff0000) >> 16);

		cmdstat |= PCI_COMMAND_IO;
	}

	/* Enable memory and I/O accesses, enable bus master */
	pci_hose_write_config_word(hose, dev, PCI_COMMAND,
					cmdstat | PCI_COMMAND_MASTER);
}

void pciauto_postscan_setup_bridge(struct pci_controller *hose,
					  pci_dev_t dev, int sub_bus)
{
	struct pci_region *pci_mem;
	struct pci_region *pci_prefetch;
	struct pci_region *pci_io;

	pci_mem = hose->pci_mem;
	pci_prefetch = hose->pci_prefetch;
	pci_io = hose->pci_io;

	/* Configure bus number registers */
	pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS,
				   sub_bus - hose->first_busno);

	if (pci_mem) {
		/* Round memory allocator to 1MB boundary */
		pciauto_region_align(pci_mem, 0x100000);

		pci_hose_write_config_word(hose, dev, PCI_MEMORY_LIMIT,
				(pci_mem->bus_lower - 1) >> 16);
	}

	if (pci_prefetch) {
		u16 prefechable_64;

		pci_hose_read_config_word(hose, dev,
					PCI_PREF_MEMORY_LIMIT,
					&prefechable_64);
		prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;

		/* Round memory allocator to 1MB boundary */
		pciauto_region_align(pci_prefetch, 0x100000);

		pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT,
				(pci_prefetch->bus_lower - 1) >> 16);
		if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
#ifdef CONFIG_SYS_PCI_64BIT
			pci_hose_write_config_dword(hose, dev,
					PCI_PREF_LIMIT_UPPER32,
					(pci_prefetch->bus_lower - 1) >> 32);
#else
			pci_hose_write_config_dword(hose, dev,
					PCI_PREF_LIMIT_UPPER32,
					0x0);
#endif
	}

	if (pci_io) {
		/* Round I/O allocator to 4KB boundary */
		pciauto_region_align(pci_io, 0x1000);

		pci_hose_write_config_byte(hose, dev, PCI_IO_LIMIT,
				((pci_io->bus_lower - 1) & 0x0000f000) >> 8);
		pci_hose_write_config_word(hose, dev, PCI_IO_LIMIT_UPPER16,
				((pci_io->bus_lower - 1) & 0xffff0000) >> 16);
	}
}


/*
 * HJF: Changed this to return int. I think this is required
 * to get the correct result when scanning bridges
 */
int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
{
	struct pci_region *pci_mem;
	struct pci_region *pci_prefetch;
	struct pci_region *pci_io;
	unsigned int sub_bus = PCI_BUS(dev);
	unsigned short class;
	int n;

	pci_mem = hose->pci_mem;
	pci_prefetch = hose->pci_prefetch;
	pci_io = hose->pci_io;

	pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);

	switch (class) {
	case PCI_CLASS_BRIDGE_PCI:
		debug("PCI Autoconfig: Found P2P bridge, device %d\n",
		      PCI_DEV(dev));

		pciauto_setup_device(hose, dev, 2, pci_mem,
				     pci_prefetch, pci_io);

		/* Passing in current_busno allows for sibling P2P bridges */
		hose->current_busno++;
		pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
		/*
		 * need to figure out if this is a subordinate bridge on the bus
		 * to be able to properly set the pri/sec/sub bridge registers.
		 */
		n = pci_hose_scan_bus(hose, hose->current_busno);

		/* figure out the deepest we've gone for this leg */
		sub_bus = max((unsigned int)n, sub_bus);
		pciauto_postscan_setup_bridge(hose, dev, sub_bus);

		sub_bus = hose->current_busno;
		break;

	case PCI_CLASS_BRIDGE_CARDBUS:
		/*
		 * just do a minimal setup of the bridge,
		 * let the OS take care of the rest
		 */
		pciauto_setup_device(hose, dev, 0, pci_mem,
				     pci_prefetch, pci_io);

		debug("PCI Autoconfig: Found P2CardBus bridge, device %d\n",
		      PCI_DEV(dev));

		hose->current_busno++;
		break;

#if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE)
	case PCI_CLASS_BRIDGE_OTHER:
		debug("PCI Autoconfig: Skipping bridge device %d\n",
		      PCI_DEV(dev));
		break;
#endif
#if defined(CONFIG_MPC834x) && !defined(CONFIG_VME8349)
	case PCI_CLASS_BRIDGE_OTHER:
		/*
		 * The host/PCI bridge 1 seems broken in 8349 - it presents
		 * itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_
		 * device claiming resources io/mem/irq.. we only allow for
		 * the PIMMR window to be allocated (BAR0 - 1MB size)
		 */
		debug("PCI Autoconfig: Broken bridge found, only minimal config\n");
		pciauto_setup_device(hose, dev, 0, hose->pci_mem,
			hose->pci_prefetch, hose->pci_io);
		break;
#endif

	case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
		debug("PCI AutoConfig: Found PowerPC device\n");

	default:
		pciauto_setup_device(hose, dev, 6, pci_mem,
				     pci_prefetch, pci_io);
		break;
	}

	return sub_bus;
}
Commit	Line	Data
c609719b	1	/*
2b81e8a3	2	* PCI autoconfiguration library (legacy version, do not change)
c609719b WD	3	*
	4	* Author: Matt Porter <[email protected]>
	5	*
	6	* Copyright 2000 MontaVista Software Inc.
	7	*
1a459660	8	* SPDX-License-Identifier: GPL-2.0+
c609719b WD	9	*/
	10
	11	#include <common.h>
4a2708a0	12	#include <errno.h>
c609719b WD	13	#include <pci.h>
c609719b WD	14
2b81e8a3 SG	15	/*
	16	* Do not change this file. Instead, convert your board to use CONFIG_DM_PCI
	17	* and change pci_auto.c.
	18	*/
	19
6d0f6bcf JCPV	20	/* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
	21	#ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE
	22	#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8
81b73dec GJ	23	#endif
81b73dec GJ	24
c609719b WD	25	/*
	26	*
	27	*/
	28
	29	void pciauto_setup_device(struct pci_controller *hose,
	30	pci_dev_t dev, int bars_num,
	31	struct pci_region *mem,
a179012e	32	struct pci_region *prefetch,
c609719b WD	33	struct pci_region *io)
c609719b WD	34	{
cf5787f2	35	u32 bar_response;
30e76d5e	36	pci_size_t bar_size;
af778c6d	37	u16 cmdstat = 0;
c609719b	38	int bar, bar_nr = 0;
53292ad9	39	#ifndef CONFIG_PCI_ENUM_ONLY
6c89663c BM	40	u8 header_type;
6c89663c BM	41	int rom_addr;
69fd2d3b AS	42	pci_addr_t bar_value;
69fd2d3b AS	43	struct pci_region *bar_res;
c609719b	44	int found_mem64 = 0;
69fd2d3b	45	#endif
cdf9f085	46	u16 class;
c609719b	47
af778c6d	48	pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
c609719b WD	49	cmdstat = (cmdstat & ~(PCI_COMMAND_IO \| PCI_COMMAND_MEMORY)) \| PCI_COMMAND_MASTER;
c609719b WD	50
cb2bf931 AS	51	for (bar = PCI_BASE_ADDRESS_0;
cb2bf931 AS	52	bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) {
c609719b	53	/* Tickle the BAR and get the response */
69fd2d3b	54	#ifndef CONFIG_PCI_ENUM_ONLY
c609719b	55	pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
69fd2d3b	56	#endif
c609719b WD	57	pci_hose_read_config_dword(hose, dev, bar, &bar_response);
	58
	59	/* If BAR is not implemented go to the next BAR */
	60	if (!bar_response)
	61	continue;
	62
69fd2d3b	63	#ifndef CONFIG_PCI_ENUM_ONLY
c609719b	64	found_mem64 = 0;
69fd2d3b	65	#endif
c609719b WD	66
c609719b WD	67	/* Check the BAR type and set our address mask */
3c74e32a	68	if (bar_response & PCI_BASE_ADDRESS_SPACE) {
bd22c2b9 JZR	69	bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK))
bd22c2b9 JZR	70	& 0xffff) + 1;
69fd2d3b	71	#ifndef CONFIG_PCI_ENUM_ONLY
c609719b	72	bar_res = io;
69fd2d3b	73	#endif
c609719b	74
da4b159b SG	75	debug("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ",
da4b159b SG	76	bar_nr, (unsigned long long)bar_size);
3c74e32a	77	} else {
cb2bf931	78	if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
30e76d5e KG	79	PCI_BASE_ADDRESS_MEM_TYPE_64) {
	80	u32 bar_response_upper;
	81	u64 bar64;
69fd2d3b AS	82
69fd2d3b AS	83	#ifndef CONFIG_PCI_ENUM_ONLY
cb2bf931 AS	84	pci_hose_write_config_dword(hose, dev, bar + 4,
cb2bf931 AS	85	0xffffffff);
69fd2d3b	86	#endif
cb2bf931 AS	87	pci_hose_read_config_dword(hose, dev, bar + 4,
cb2bf931 AS	88	&bar_response_upper);
30e76d5e KG	89
30e76d5e KG	90	bar64 = ((u64)bar_response_upper << 32) \| bar_response;
c609719b	91
30e76d5e	92	bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
69fd2d3b	93	#ifndef CONFIG_PCI_ENUM_ONLY
30e76d5e	94	found_mem64 = 1;
69fd2d3b	95	#endif
30e76d5e KG	96	} else {
	97	bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
	98	}
69fd2d3b	99	#ifndef CONFIG_PCI_ENUM_ONLY
a179012e KG	100	if (prefetch && (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH))
	101	bar_res = prefetch;
	102	else
	103	bar_res = mem;
c609719b	104
4bad2e73 SG	105	debug("PCI Autoconfig: BAR %d, %s, size=0x%llx, ",
	106	bar_nr, bar_res == prefetch ? "Prf" : "Mem",
	107	(unsigned long long)bar_size);
11131467	108	#endif
c609719b WD	109	}
c609719b WD	110
69fd2d3b	111	#ifndef CONFIG_PCI_ENUM_ONLY
3c74e32a	112	if (pciauto_region_allocate(bar_res, bar_size, &bar_value) == 0) {
c609719b	113	/* Write it out and update our limit */
30e76d5e	114	pci_hose_write_config_dword(hose, dev, bar, (u32)bar_value);
c609719b	115
3c74e32a	116	if (found_mem64) {
c609719b	117	bar += 4;
30e76d5e KG	118	#ifdef CONFIG_SYS_PCI_64BIT
	119	pci_hose_write_config_dword(hose, dev, bar, (u32)(bar_value>>32));
	120	#else
	121	/*
	122	* If we are a 64-bit decoder then increment to the
	123	* upper 32 bits of the bar and force it to locate
	124	* in the lower 4GB of memory.
	125	*/
c609719b	126	pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
30e76d5e	127	#endif
c609719b WD	128	}
c609719b WD	129
c609719b	130	}
69fd2d3b AS	131	#endif
	132	cmdstat \|= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
	133	PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
c609719b	134
da4b159b	135	debug("\n");
c609719b WD	136
	137	bar_nr++;
	138	}
	139
53292ad9	140	#ifndef CONFIG_PCI_ENUM_ONLY
6c89663c BM	141	/* Configure the expansion ROM address */
6c89663c BM	142	pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
7445435f	143	header_type &= 0x7f;
6c89663c BM	144	if (header_type != PCI_HEADER_TYPE_CARDBUS) {
	145	rom_addr = (header_type == PCI_HEADER_TYPE_NORMAL) ?
	146	PCI_ROM_ADDRESS : PCI_ROM_ADDRESS1;
	147	pci_hose_write_config_dword(hose, dev, rom_addr, 0xfffffffe);
	148	pci_hose_read_config_dword(hose, dev, rom_addr, &bar_response);
	149	if (bar_response) {
	150	bar_size = -(bar_response & ~1);
da4b159b SG	151	debug("PCI Autoconfig: ROM, size=%#x, ",
da4b159b SG	152	(unsigned int)bar_size);
6c89663c BM	153	if (pciauto_region_allocate(mem, bar_size,
	154	&bar_value) == 0) {
	155	pci_hose_write_config_dword(hose, dev, rom_addr,
	156	bar_value);
	157	}
	158	cmdstat \|= PCI_COMMAND_MEMORY;
da4b159b	159	debug("\n");
6c89663c BM	160	}
6c89663c BM	161	}
53292ad9	162	#endif
6c89663c	163
cdf9f085 BM	164	/* PCI_COMMAND_IO must be set for VGA device */
	165	pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
	166	if (class == PCI_CLASS_DISPLAY_VGA)
	167	cmdstat \|= PCI_COMMAND_IO;
	168
af778c6d	169	pci_hose_write_config_word(hose, dev, PCI_COMMAND, cmdstat);
81b73dec	170	pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE,
6d0f6bcf	171	CONFIG_SYS_PCI_CACHE_LINE_SIZE);
c609719b WD	172	pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
	173	}
	174
ba5feb12	175	void pciauto_prescan_setup_bridge(struct pci_controller *hose,
c609719b WD	176	pci_dev_t dev, int sub_bus)
c609719b WD	177	{
d11d9ef1 BM	178	struct pci_region *pci_mem;
	179	struct pci_region *pci_prefetch;
	180	struct pci_region *pci_io;
6eefd527	181	u16 cmdstat, prefechable_64;
c609719b	182
d11d9ef1 BM	183	pci_mem = hose->pci_mem;
	184	pci_prefetch = hose->pci_prefetch;
	185	pci_io = hose->pci_io;
d11d9ef1	186
af778c6d	187	pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
6eefd527 DF	188	pci_hose_read_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
	189	&prefechable_64);
	190	prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
c609719b WD	191
c609719b WD	192	/* Configure bus number registers */
e8b85f3b ES	193	pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS,
	194	PCI_BUS(dev) - hose->first_busno);
	195	pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS,
	196	sub_bus - hose->first_busno);
c609719b WD	197	pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff);
c609719b WD	198
3c74e32a	199	if (pci_mem) {
c609719b WD	200	/* Round memory allocator to 1MB boundary */
	201	pciauto_region_align(pci_mem, 0x100000);
	202
	203	/* Set up memory and I/O filter limits, assume 32-bit I/O space */
	204	pci_hose_write_config_word(hose, dev, PCI_MEMORY_BASE,
	205	(pci_mem->bus_lower & 0xfff00000) >> 16);
	206
	207	cmdstat \|= PCI_COMMAND_MEMORY;
	208	}
	209
a179012e KG	210	if (pci_prefetch) {
	211	/* Round memory allocator to 1MB boundary */
	212	pciauto_region_align(pci_prefetch, 0x100000);
	213
	214	/* Set up memory and I/O filter limits, assume 32-bit I/O space */
	215	pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
	216	(pci_prefetch->bus_lower & 0xfff00000) >> 16);
6eefd527 DF	217	if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
	218	#ifdef CONFIG_SYS_PCI_64BIT
	219	pci_hose_write_config_dword(hose, dev,
	220	PCI_PREF_BASE_UPPER32,
	221	pci_prefetch->bus_lower >> 32);
	222	#else
	223	pci_hose_write_config_dword(hose, dev,
	224	PCI_PREF_BASE_UPPER32,
	225	0x0);
	226	#endif
a179012e KG	227
	228	cmdstat \|= PCI_COMMAND_MEMORY;
	229	} else {
	230	/* We don't support prefetchable memory for now, so disable */
	231	pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000);
a4e11558	232	pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x0);
6eefd527 DF	233	if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) {
	234	pci_hose_write_config_word(hose, dev, PCI_PREF_BASE_UPPER32, 0x0);
	235	pci_hose_write_config_word(hose, dev, PCI_PREF_LIMIT_UPPER32, 0x0);
	236	}
a179012e KG	237	}
a179012e KG	238
3c74e32a	239	if (pci_io) {
c609719b WD	240	/* Round I/O allocator to 4KB boundary */
	241	pciauto_region_align(pci_io, 0x1000);
	242
	243	pci_hose_write_config_byte(hose, dev, PCI_IO_BASE,
	244	(pci_io->bus_lower & 0x0000f000) >> 8);
	245	pci_hose_write_config_word(hose, dev, PCI_IO_BASE_UPPER16,
	246	(pci_io->bus_lower & 0xffff0000) >> 16);
	247
	248	cmdstat \|= PCI_COMMAND_IO;
	249	}
	250
c609719b	251	/* Enable memory and I/O accesses, enable bus master */
af778c6d AS	252	pci_hose_write_config_word(hose, dev, PCI_COMMAND,
af778c6d AS	253	cmdstat \| PCI_COMMAND_MASTER);
c609719b WD	254	}
c609719b WD	255
ba5feb12	256	void pciauto_postscan_setup_bridge(struct pci_controller *hose,
c609719b WD	257	pci_dev_t dev, int sub_bus)
c609719b WD	258	{
d11d9ef1 BM	259	struct pci_region *pci_mem;
	260	struct pci_region *pci_prefetch;
	261	struct pci_region *pci_io;
	262
d11d9ef1 BM	263	pci_mem = hose->pci_mem;
	264	pci_prefetch = hose->pci_prefetch;
	265	pci_io = hose->pci_io;
c609719b WD	266
c609719b WD	267	/* Configure bus number registers */
e8b85f3b ES	268	pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS,
e8b85f3b ES	269	sub_bus - hose->first_busno);
c609719b	270
3c74e32a	271	if (pci_mem) {
c609719b WD	272	/* Round memory allocator to 1MB boundary */
	273	pciauto_region_align(pci_mem, 0x100000);
	274
	275	pci_hose_write_config_word(hose, dev, PCI_MEMORY_LIMIT,
cb2bf931	276	(pci_mem->bus_lower - 1) >> 16);
c609719b WD	277	}
c609719b WD	278
a179012e	279	if (pci_prefetch) {
6eefd527 DF	280	u16 prefechable_64;
	281
	282	pci_hose_read_config_word(hose, dev,
	283	PCI_PREF_MEMORY_LIMIT,
	284	&prefechable_64);
	285	prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
	286
a179012e KG	287	/* Round memory allocator to 1MB boundary */
	288	pciauto_region_align(pci_prefetch, 0x100000);
	289
	290	pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT,
cb2bf931	291	(pci_prefetch->bus_lower - 1) >> 16);
6eefd527 DF	292	if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
	293	#ifdef CONFIG_SYS_PCI_64BIT
	294	pci_hose_write_config_dword(hose, dev,
	295	PCI_PREF_LIMIT_UPPER32,
	296	(pci_prefetch->bus_lower - 1) >> 32);
	297	#else
	298	pci_hose_write_config_dword(hose, dev,
	299	PCI_PREF_LIMIT_UPPER32,
	300	0x0);
	301	#endif
a179012e KG	302	}
a179012e KG	303
3c74e32a	304	if (pci_io) {
c609719b WD	305	/* Round I/O allocator to 4KB boundary */
	306	pciauto_region_align(pci_io, 0x1000);
	307
	308	pci_hose_write_config_byte(hose, dev, PCI_IO_LIMIT,
cb2bf931	309	((pci_io->bus_lower - 1) & 0x0000f000) >> 8);
c609719b	310	pci_hose_write_config_word(hose, dev, PCI_IO_LIMIT_UPPER16,
cb2bf931	311	((pci_io->bus_lower - 1) & 0xffff0000) >> 16);
c609719b WD	312	}
	313	}
	314
c609719b	315
cb2bf931 AS	316	/*
cb2bf931 AS	317	* HJF: Changed this to return int. I think this is required
c7de829c WD	318	* to get the correct result when scanning bridges
	319	*/
	320	int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
c609719b	321	{
d11d9ef1 BM	322	struct pci_region *pci_mem;
	323	struct pci_region *pci_prefetch;
	324	struct pci_region *pci_io;
c7de829c	325	unsigned int sub_bus = PCI_BUS(dev);
c609719b	326	unsigned short class;
5653fc33	327	int n;
c609719b	328
d11d9ef1 BM	329	pci_mem = hose->pci_mem;
	330	pci_prefetch = hose->pci_prefetch;
	331	pci_io = hose->pci_io;
d11d9ef1	332
c609719b WD	333	pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
c609719b WD	334
cb2bf931	335	switch (class) {
c609719b	336	case PCI_CLASS_BRIDGE_PCI:
da4b159b SG	337	debug("PCI Autoconfig: Found P2P bridge, device %d\n",
da4b159b SG	338	PCI_DEV(dev));
ff3e077b	339
d11d9ef1 BM	340	pciauto_setup_device(hose, dev, 2, pci_mem,
d11d9ef1 BM	341	pci_prefetch, pci_io);
c609719b	342
3c74e32a	343	/* Passing in current_busno allows for sibling P2P bridges */
ff3e077b	344	hose->current_busno++;
5653fc33	345	pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
cd37d9e6	346	/*
3c74e32a	347	* need to figure out if this is a subordinate bridge on the bus
5653fc33 WD	348	* to be able to properly set the pri/sec/sub bridge registers.
	349	*/
	350	n = pci_hose_scan_bus(hose, hose->current_busno);
	351
3c74e32a	352	/* figure out the deepest we've gone for this leg */
b4141195	353	sub_bus = max((unsigned int)n, sub_bus);
db2f721f	354	pciauto_postscan_setup_bridge(hose, dev, sub_bus);
5653fc33	355
db2f721f	356	sub_bus = hose->current_busno;
c609719b WD	357	break;
c609719b WD	358
1cb8e980	359	case PCI_CLASS_BRIDGE_CARDBUS:
cb2bf931 AS	360	/*
	361	* just do a minimal setup of the bridge,
	362	* let the OS take care of the rest
	363	*/
d11d9ef1 BM	364	pciauto_setup_device(hose, dev, 0, pci_mem,
d11d9ef1 BM	365	pci_prefetch, pci_io);
1cb8e980	366
da4b159b SG	367	debug("PCI Autoconfig: Found P2CardBus bridge, device %d\n",
da4b159b SG	368	PCI_DEV(dev));
1cb8e980 WD	369
	370	hose->current_busno++;
	371	break;
	372
f33fca22	373	#if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE)
e0ac62d7	374	case PCI_CLASS_BRIDGE_OTHER:
da4b159b SG	375	debug("PCI Autoconfig: Skipping bridge device %d\n",
da4b159b SG	376	PCI_DEV(dev));
e0ac62d7 WD	377	break;
e0ac62d7 WD	378	#endif
c2e49f70	379	#if defined(CONFIG_MPC834x) && !defined(CONFIG_VME8349)
6902df56 RJ	380	case PCI_CLASS_BRIDGE_OTHER:
	381	/*
	382	* The host/PCI bridge 1 seems broken in 8349 - it presents
	383	* itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_
	384	* device claiming resources io/mem/irq.. we only allow for
	385	* the PIMMR window to be allocated (BAR0 - 1MB size)
	386	*/
da4b159b	387	debug("PCI Autoconfig: Broken bridge found, only minimal config\n");
cb2bf931 AS	388	pciauto_setup_device(hose, dev, 0, hose->pci_mem,
cb2bf931 AS	389	hose->pci_prefetch, hose->pci_io);
6902df56 RJ	390	break;
6902df56 RJ	391	#endif
69fd2d3b AS	392
69fd2d3b AS	393	case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
da4b159b	394	debug("PCI AutoConfig: Found PowerPC device\n");
69fd2d3b	395
c609719b	396	default:
d11d9ef1 BM	397	pciauto_setup_device(hose, dev, 6, pci_mem,
d11d9ef1 BM	398	pci_prefetch, pci_io);
c609719b WD	399	break;
c609719b WD	400	}
c7de829c WD	401
c7de829c WD	402	return sub_bus;
c609719b	403	}