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Fix some checkpatch warnings in calls to debug()
[J-u-boot.git] / drivers / net / sni_ave.c
CommitLineData
a8927795
KH		 1// SPDX-License-Identifier: GPL-2.0+
2/**
3 * sni_ave.c - Socionext UniPhier AVE ethernet driver
4 * Copyright 2016-2018 Socionext inc.
5 */
6
7#include <clk.h>
1eb69ae4 8#include <cpu_func.h>
a8927795
KH		 9#include <dm.h>
10#include <fdt_support.h>
336d4615 11#include <malloc.h>
a8927795
KH		 12#include <miiphy.h>
13#include <net.h>
14#include <regmap.h>
15#include <reset.h>
16#include <syscon.h>
90526e9f 17#include <asm/cache.h>
336d4615
SG		 18#include <dm/device_compat.h>
19#include <linux/err.h>
20#include <linux/io.h>
21#include <linux/iopoll.h>
a8927795
KH		 22
23#define AVE_GRST_DELAY_MSEC 40
24#define AVE_MIN_XMITSIZE 60
25#define AVE_SEND_TIMEOUT_COUNT 1000
26#define AVE_MDIO_TIMEOUT_USEC 10000
27#define AVE_HALT_TIMEOUT_USEC 10000
28
29/* General Register Group */
30#define AVE_IDR 0x000 /* ID */
31#define AVE_VR 0x004 /* Version */
32#define AVE_GRR 0x008 /* Global Reset */
33#define AVE_CFGR 0x00c /* Configuration */
34
35/* Interrupt Register Group */
36#define AVE_GIMR 0x100 /* Global Interrupt Mask */
37#define AVE_GISR 0x104 /* Global Interrupt Status */
38
39/* MAC Register Group */
40#define AVE_TXCR 0x200 /* TX Setup */
41#define AVE_RXCR 0x204 /* RX Setup */
42#define AVE_RXMAC1R 0x208 /* MAC address (lower) */
43#define AVE_RXMAC2R 0x20c /* MAC address (upper) */
44#define AVE_MDIOCTR 0x214 /* MDIO Control */
45#define AVE_MDIOAR 0x218 /* MDIO Address */
46#define AVE_MDIOWDR 0x21c /* MDIO Data */
47#define AVE_MDIOSR 0x220 /* MDIO Status */
48#define AVE_MDIORDR 0x224 /* MDIO Rd Data */
49
50/* Descriptor Control Register Group */
51#define AVE_DESCC 0x300 /* Descriptor Control */
52#define AVE_TXDC 0x304 /* TX Descriptor Configuration */
53#define AVE_RXDC 0x308 /* RX Descriptor Ring0 Configuration */
54#define AVE_IIRQC 0x34c /* Interval IRQ Control */
55
56/* 64bit descriptor memory */
57#define AVE_DESC_SIZE_64 12 /* Descriptor Size */
58#define AVE_TXDM_64 0x1000 /* Tx Descriptor Memory */
59#define AVE_RXDM_64 0x1c00 /* Rx Descriptor Memory */
60
61/* 32bit descriptor memory */
62#define AVE_DESC_SIZE_32 8 /* Descriptor Size */
63#define AVE_TXDM_32 0x1000 /* Tx Descriptor Memory */
64#define AVE_RXDM_32 0x1800 /* Rx Descriptor Memory */
65
66/* RMII Bridge Register Group */
67#define AVE_RSTCTRL 0x8028 /* Reset control */
68#define AVE_RSTCTRL_RMIIRST BIT(16)
69#define AVE_LINKSEL 0x8034 /* Link speed setting */
70#define AVE_LINKSEL_100M BIT(0)
71
72/* AVE_GRR */
73#define AVE_GRR_PHYRST BIT(4) /* Reset external PHY */
74#define AVE_GRR_GRST BIT(0) /* Reset all MAC */
75
76/* AVE_CFGR */
77#define AVE_CFGR_MII BIT(27) /* Func mode (1:MII/RMII, 0:RGMII) */
78
79/* AVE_GISR (common with GIMR) */
80#define AVE_GIMR_CLR 0
81#define AVE_GISR_CLR GENMASK(31, 0)
82
83/* AVE_TXCR */
84#define AVE_TXCR_FLOCTR BIT(18) /* Flow control */
85#define AVE_TXCR_TXSPD_1G BIT(17)
86#define AVE_TXCR_TXSPD_100 BIT(16)
87
88/* AVE_RXCR */
89#define AVE_RXCR_RXEN BIT(30) /* Rx enable */
90#define AVE_RXCR_FDUPEN BIT(22) /* Interface mode */
91#define AVE_RXCR_FLOCTR BIT(21) /* Flow control */
92
93/* AVE_MDIOCTR */
94#define AVE_MDIOCTR_RREQ BIT(3) /* Read request */
95#define AVE_MDIOCTR_WREQ BIT(2) /* Write request */
96
97/* AVE_MDIOSR */
98#define AVE_MDIOSR_STS BIT(0) /* access status */
99
100/* AVE_DESCC */
101#define AVE_DESCC_RXDSTPSTS BIT(20)
102#define AVE_DESCC_RD0 BIT(8) /* Enable Rx descriptor Ring0 */
103#define AVE_DESCC_RXDSTP BIT(4) /* Pause Rx descriptor */
104#define AVE_DESCC_TD BIT(0) /* Enable Tx descriptor */
105
106/* AVE_TXDC/RXDC */
107#define AVE_DESC_SIZE(priv, num) \
108 ((num) * ((priv)->data->is_desc_64bit ? AVE_DESC_SIZE_64 : \
109 AVE_DESC_SIZE_32))
110
111/* Command status for descriptor */
112#define AVE_STS_OWN BIT(31) /* Descriptor ownership */
113#define AVE_STS_OK BIT(27) /* Normal transmit */
114#define AVE_STS_1ST BIT(26) /* Head of buffer chain */
115#define AVE_STS_LAST BIT(25) /* Tail of buffer chain */
116#define AVE_STS_PKTLEN_TX_MASK GENMASK(15, 0)
117#define AVE_STS_PKTLEN_RX_MASK GENMASK(10, 0)
118
119#define AVE_DESC_OFS_CMDSTS 0
120#define AVE_DESC_OFS_ADDRL 4
121#define AVE_DESC_OFS_ADDRU 8
122
123/* Parameter for ethernet frame */
124#define AVE_RXCR_MTU 1518
125
126/* SG */
127#define SG_ETPINMODE 0x540
128#define SG_ETPINMODE_EXTPHY BIT(1) /* for LD11 */
129#define SG_ETPINMODE_RMII(ins) BIT(ins)
130
131#define AVE_MAX_CLKS 4
132#define AVE_MAX_RSTS 2
133
134enum desc_id {
135 AVE_DESCID_TX,
136 AVE_DESCID_RX,
137};
138
139struct ave_private {
140 phys_addr_t iobase;
141 unsigned int nclks;
142 struct clk clk[AVE_MAX_CLKS];
143 unsigned int nrsts;
144 struct reset_ctl rst[AVE_MAX_RSTS];
145 struct regmap *regmap;
146 unsigned int regmap_arg;
147
148 struct mii_dev *bus;
149 struct phy_device *phydev;
150 int phy_mode;
151 int max_speed;
152
153 int rx_pos;
154 int rx_siz;
155 int rx_off;
156 int tx_num;
157
158 u8 tx_adj_packetbuf[PKTSIZE_ALIGN + PKTALIGN];
159 void *tx_adj_buf;
160
161 const struct ave_soc_data *data;
162};
163
164struct ave_soc_data {
165 bool is_desc_64bit;
166 const char *clock_names[AVE_MAX_CLKS];
167 const char *reset_names[AVE_MAX_RSTS];
168 int (*get_pinmode)(struct ave_private *priv);
169};
170
171static u32 ave_desc_read(struct ave_private *priv, enum desc_id id, int entry,
172 int offset)
173{
174 int desc_size;
175 u32 addr;
176
177 if (priv->data->is_desc_64bit) {
178 desc_size = AVE_DESC_SIZE_64;
179 addr = (id == AVE_DESCID_TX) ? AVE_TXDM_64 : AVE_RXDM_64;
180 } else {
181 desc_size = AVE_DESC_SIZE_32;
182 addr = (id == AVE_DESCID_TX) ? AVE_TXDM_32 : AVE_RXDM_32;
183 }
184
185 addr += entry * desc_size + offset;
186
187 return readl(priv->iobase + addr);
188}
189
190static u32 ave_desc_read_cmdsts(struct ave_private *priv, enum desc_id id,
191 int entry)
192{
193 return ave_desc_read(priv, id, entry, AVE_DESC_OFS_CMDSTS);
194}
195
196static void ave_desc_write(struct ave_private *priv, enum desc_id id,
197 int entry, int offset, u32 val)
198{
199 int desc_size;
200 u32 addr;
201
202 if (priv->data->is_desc_64bit) {
203 desc_size = AVE_DESC_SIZE_64;
204 addr = (id == AVE_DESCID_TX) ? AVE_TXDM_64 : AVE_RXDM_64;
205 } else {
206 desc_size = AVE_DESC_SIZE_32;
207 addr = (id == AVE_DESCID_TX) ? AVE_TXDM_32 : AVE_RXDM_32;
208 }
209
210 addr += entry * desc_size + offset;
211 writel(val, priv->iobase + addr);
212}
213
214static void ave_desc_write_cmdsts(struct ave_private *priv, enum desc_id id,
215 int entry, u32 val)
216{
217 ave_desc_write(priv, id, entry, AVE_DESC_OFS_CMDSTS, val);
218}
219
220static void ave_desc_write_addr(struct ave_private *priv, enum desc_id id,
221 int entry, uintptr_t paddr)
222{
223 ave_desc_write(priv, id, entry,
224 AVE_DESC_OFS_ADDRL, lower_32_bits(paddr));
225 if (priv->data->is_desc_64bit)
226 ave_desc_write(priv, id, entry,
227 AVE_DESC_OFS_ADDRU, upper_32_bits(paddr));
228}
229
230static void ave_cache_invalidate(uintptr_t vaddr, int len)
231{
232 invalidate_dcache_range(rounddown(vaddr, ARCH_DMA_MINALIGN),
233 roundup(vaddr + len, ARCH_DMA_MINALIGN));
234}
235
236static void ave_cache_flush(uintptr_t vaddr, int len)
237{
238 flush_dcache_range(rounddown(vaddr, ARCH_DMA_MINALIGN),
239 roundup(vaddr + len, ARCH_DMA_MINALIGN));
240}
241
242static int ave_mdiobus_read(struct mii_dev *bus,
243 int phyid, int devad, int regnum)
244{
245 struct ave_private *priv = bus->priv;
246 u32 mdioctl, mdiosr;
247 int ret;
248
249 /* write address */
250 writel((phyid << 8) | regnum, priv->iobase + AVE_MDIOAR);
251
252 /* read request */
253 mdioctl = readl(priv->iobase + AVE_MDIOCTR);
254 writel(mdioctl | AVE_MDIOCTR_RREQ, priv->iobase + AVE_MDIOCTR);
255
256 ret = readl_poll_timeout(priv->iobase + AVE_MDIOSR, mdiosr,
257 !(mdiosr & AVE_MDIOSR_STS),
258 AVE_MDIO_TIMEOUT_USEC);
259 if (ret) {
260 pr_err("%s: failed to read from mdio (phy:%d reg:%x)\n",
261 priv->phydev->dev->name, phyid, regnum);
262 return ret;
263 }
264
265 return readl(priv->iobase + AVE_MDIORDR) & GENMASK(15, 0);
266}
267
268static int ave_mdiobus_write(struct mii_dev *bus,
269 int phyid, int devad, int regnum, u16 val)
270{
271 struct ave_private *priv = bus->priv;
272 u32 mdioctl, mdiosr;
273 int ret;
274
275 /* write address */
276 writel((phyid << 8) | regnum, priv->iobase + AVE_MDIOAR);
277
278 /* write data */
279 writel(val, priv->iobase + AVE_MDIOWDR);
280
281 /* write request */
282 mdioctl = readl(priv->iobase + AVE_MDIOCTR);
283 writel((mdioctl | AVE_MDIOCTR_WREQ) & ~AVE_MDIOCTR_RREQ,
284 priv->iobase + AVE_MDIOCTR);
285
286 ret = readl_poll_timeout(priv->iobase + AVE_MDIOSR, mdiosr,
287 !(mdiosr & AVE_MDIOSR_STS),
288 AVE_MDIO_TIMEOUT_USEC);
289 if (ret)
290 pr_err("%s: failed to write to mdio (phy:%d reg:%x)\n",
291 priv->phydev->dev->name, phyid, regnum);
292
293 return ret;
294}
295
296static int ave_adjust_link(struct ave_private *priv)
297{
298 struct phy_device *phydev = priv->phydev;
299 struct eth_pdata *pdata = dev_get_platdata(phydev->dev);
300 u32 val, txcr, rxcr, rxcr_org;
301 u16 rmt_adv = 0, lcl_adv = 0;
302 u8 cap;
303
304 /* set RGMII speed */
305 val = readl(priv->iobase + AVE_TXCR);
306 val &= ~(AVE_TXCR_TXSPD_100 | AVE_TXCR_TXSPD_1G);
307
308 if (phy_interface_is_rgmii(phydev) && phydev->speed == SPEED_1000)
309 val |= AVE_TXCR_TXSPD_1G;
310 else if (phydev->speed == SPEED_100)
311 val |= AVE_TXCR_TXSPD_100;
312
313 writel(val, priv->iobase + AVE_TXCR);
314
315 /* set RMII speed (100M/10M only) */
316 if (!phy_interface_is_rgmii(phydev)) {
317 val = readl(priv->iobase + AVE_LINKSEL);
318 if (phydev->speed == SPEED_10)
319 val &= ~AVE_LINKSEL_100M;
320 else
321 val |= AVE_LINKSEL_100M;
322 writel(val, priv->iobase + AVE_LINKSEL);
323 }
324
325 /* check current RXCR/TXCR */
326 rxcr = readl(priv->iobase + AVE_RXCR);
327 txcr = readl(priv->iobase + AVE_TXCR);
328 rxcr_org = rxcr;
329
330 if (phydev->duplex) {
331 rxcr |= AVE_RXCR_FDUPEN;
332
333 if (phydev->pause)
334 rmt_adv |= LPA_PAUSE_CAP;
335 if (phydev->asym_pause)
336 rmt_adv |= LPA_PAUSE_ASYM;
337 if (phydev->advertising & ADVERTISED_Pause)
338 lcl_adv |= ADVERTISE_PAUSE_CAP;
339 if (phydev->advertising & ADVERTISED_Asym_Pause)
340 lcl_adv |= ADVERTISE_PAUSE_ASYM;
341
342 cap = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
343 if (cap & FLOW_CTRL_TX)
344 txcr |= AVE_TXCR_FLOCTR;
345 else
346 txcr &= ~AVE_TXCR_FLOCTR;
347 if (cap & FLOW_CTRL_RX)
348 rxcr |= AVE_RXCR_FLOCTR;
349 else
350 rxcr &= ~AVE_RXCR_FLOCTR;
351 } else {
352 rxcr &= ~AVE_RXCR_FDUPEN;
353 rxcr &= ~AVE_RXCR_FLOCTR;
354 txcr &= ~AVE_TXCR_FLOCTR;
355 }
356
357 if (rxcr_org != rxcr) {
358 /* disable Rx mac */
359 writel(rxcr & ~AVE_RXCR_RXEN, priv->iobase + AVE_RXCR);
360 /* change and enable TX/Rx mac */
361 writel(txcr, priv->iobase + AVE_TXCR);
362 writel(rxcr, priv->iobase + AVE_RXCR);
363 }
364
365 pr_notice("%s: phy:%s speed:%d mac:%pM\n",
366 phydev->dev->name, phydev->drv->name, phydev->speed,
367 pdata->enetaddr);
368
369 return phydev->link;
370}
371
372static int ave_mdiobus_init(struct ave_private *priv, const char *name)
373{
374 struct mii_dev *bus = mdio_alloc();
375
376 if (!bus)
377 return -ENOMEM;
378
379 bus->read = ave_mdiobus_read;
380 bus->write = ave_mdiobus_write;
381 snprintf(bus->name, sizeof(bus->name), "%s", name);
382 bus->priv = priv;
383
384 return mdio_register(bus);
385}
386
387static int ave_phy_init(struct ave_private *priv, void *dev)
388{
389 struct phy_device *phydev;
390 int mask = GENMASK(31, 0), ret;
391
392 phydev = phy_find_by_mask(priv->bus, mask, priv->phy_mode);
393 if (!phydev)
394 return -ENODEV;
395
396 phy_connect_dev(phydev, dev);
397
398 phydev->supported &= PHY_GBIT_FEATURES;
399 if (priv->max_speed) {
400 ret = phy_set_supported(phydev, priv->max_speed);
401 if (ret)
402 return ret;
403 }
404 phydev->advertising = phydev->supported;
405
406 priv->phydev = phydev;
407 phy_config(phydev);
408
409 return 0;
410}
411
412static void ave_stop(struct udevice *dev)
413{
414 struct ave_private *priv = dev_get_priv(dev);
415 u32 val;
416 int ret;
417
418 val = readl(priv->iobase + AVE_GRR);
419 if (val)
420 return;
421
422 val = readl(priv->iobase + AVE_RXCR);
423 val &= ~AVE_RXCR_RXEN;
424 writel(val, priv->iobase + AVE_RXCR);
425
426 writel(0, priv->iobase + AVE_DESCC);
427 ret = readl_poll_timeout(priv->iobase + AVE_DESCC, val, !val,
428 AVE_HALT_TIMEOUT_USEC);
429 if (ret)
430 pr_warn("%s: halt timeout\n", priv->phydev->dev->name);
431
432 writel(AVE_GRR_GRST, priv->iobase + AVE_GRR);
433
434 phy_shutdown(priv->phydev);
435}
436
437static void ave_reset(struct ave_private *priv)
438{
439 u32 val;
440
441 /* reset RMII register */
442 val = readl(priv->iobase + AVE_RSTCTRL);
443 val &= ~AVE_RSTCTRL_RMIIRST;
444 writel(val, priv->iobase + AVE_RSTCTRL);
445
446 /* assert reset */
447 writel(AVE_GRR_GRST | AVE_GRR_PHYRST, priv->iobase + AVE_GRR);
448 mdelay(AVE_GRST_DELAY_MSEC);
449
450 /* 1st, negate PHY reset only */
451 writel(AVE_GRR_GRST, priv->iobase + AVE_GRR);
452 mdelay(AVE_GRST_DELAY_MSEC);
453
454 /* negate reset */
455 writel(0, priv->iobase + AVE_GRR);
456 mdelay(AVE_GRST_DELAY_MSEC);
457
458 /* negate RMII register */
459 val = readl(priv->iobase + AVE_RSTCTRL);
460 val |= AVE_RSTCTRL_RMIIRST;
461 writel(val, priv->iobase + AVE_RSTCTRL);
462}
463
464static int ave_start(struct udevice *dev)
465{
466 struct ave_private *priv = dev_get_priv(dev);
467 uintptr_t paddr;
468 u32 val;
469 int i;
470
471 ave_reset(priv);
472
473 priv->rx_pos = 0;
474 priv->rx_off = 2; /* RX data has 2byte offsets */
475 priv->tx_num = 0;
476 priv->tx_adj_buf =
477 (void *)roundup((uintptr_t)&priv->tx_adj_packetbuf[0],
478 PKTALIGN);
479 priv->rx_siz = (PKTSIZE_ALIGN - priv->rx_off);
480
481 val = 0;
482 if (priv->phy_mode != PHY_INTERFACE_MODE_RGMII)
483 val |= AVE_CFGR_MII;
484 writel(val, priv->iobase + AVE_CFGR);
485
486 /* use one descriptor for Tx */
487 writel(AVE_DESC_SIZE(priv, 1) << 16, priv->iobase + AVE_TXDC);
488 ave_desc_write_cmdsts(priv, AVE_DESCID_TX, 0, 0);
489 ave_desc_write_addr(priv, AVE_DESCID_TX, 0, 0);
490
491 /* use PKTBUFSRX descriptors for Rx */
492 writel(AVE_DESC_SIZE(priv, PKTBUFSRX) << 16, priv->iobase + AVE_RXDC);
493 for (i = 0; i < PKTBUFSRX; i++) {
494 paddr = (uintptr_t)net_rx_packets[i];
495 ave_cache_flush(paddr, priv->rx_siz + priv->rx_off);
496 ave_desc_write_addr(priv, AVE_DESCID_RX, i, paddr);
497 ave_desc_write_cmdsts(priv, AVE_DESCID_RX, i, priv->rx_siz);
498 }
499
500 writel(AVE_GISR_CLR, priv->iobase + AVE_GISR);
501 writel(AVE_GIMR_CLR, priv->iobase + AVE_GIMR);
502
503 writel(AVE_RXCR_RXEN | AVE_RXCR_FDUPEN | AVE_RXCR_FLOCTR | AVE_RXCR_MTU,
504 priv->iobase + AVE_RXCR);
505 writel(AVE_DESCC_RD0 | AVE_DESCC_TD, priv->iobase + AVE_DESCC);
506
507 phy_startup(priv->phydev);
508 ave_adjust_link(priv);
509
510 return 0;
511}
512
513static int ave_write_hwaddr(struct udevice *dev)
514{
515 struct ave_private *priv = dev_get_priv(dev);
516 struct eth_pdata *pdata = dev_get_platdata(dev);
517 u8 *mac = pdata->enetaddr;
518
519 writel(mac[0] | mac[1] << 8 | mac[2] << 16 | mac[3] << 24,
520 priv->iobase + AVE_RXMAC1R);
521 writel(mac[4] | mac[5] << 8, priv->iobase + AVE_RXMAC2R);
522
523 return 0;
524}
525
526static int ave_send(struct udevice *dev, void *packet, int length)
527{
528 struct ave_private *priv = dev_get_priv(dev);
529 u32 val;
530 void *ptr = packet;
531 int count;
532
533 /* adjust alignment for descriptor */
534 if ((uintptr_t)ptr & 0x3) {
535 memcpy(priv->tx_adj_buf, (const void *)ptr, length);
536 ptr = priv->tx_adj_buf;
537 }
538
539 /* padding for minimum length */
540 if (length < AVE_MIN_XMITSIZE) {
541 memset(ptr + length, 0, AVE_MIN_XMITSIZE - length);
542 length = AVE_MIN_XMITSIZE;
543 }
544
545 /* check ownership and wait for previous xmit done */
546 count = AVE_SEND_TIMEOUT_COUNT;
547 do {
548 val = ave_desc_read_cmdsts(priv, AVE_DESCID_TX, 0);
549 } while ((val & AVE_STS_OWN) && --count);
550 if (!count)
551 return -ETIMEDOUT;
552
553 ave_cache_flush((uintptr_t)ptr, length);
554 ave_desc_write_addr(priv, AVE_DESCID_TX, 0, (uintptr_t)ptr);
555
556 val = AVE_STS_OWN | AVE_STS_1ST | AVE_STS_LAST |
557 (length & AVE_STS_PKTLEN_TX_MASK);
558 ave_desc_write_cmdsts(priv, AVE_DESCID_TX, 0, val);
559 priv->tx_num++;
560
561 count = AVE_SEND_TIMEOUT_COUNT;
562 do {
563 val = ave_desc_read_cmdsts(priv, AVE_DESCID_TX, 0);
564 } while ((val & AVE_STS_OWN) && --count);
565 if (!count)
566 return -ETIMEDOUT;
567
568 if (!(val & AVE_STS_OK))
569 pr_warn("%s: bad send packet status:%08x\n",
570 priv->phydev->dev->name, le32_to_cpu(val));
571
572 return 0;
573}
574
575static int ave_recv(struct udevice *dev, int flags, uchar **packetp)
576{
577 struct ave_private *priv = dev_get_priv(dev);
578 uchar *ptr;
579 int length = 0;
580 u32 cmdsts;
581
582 while (1) {
583 cmdsts = ave_desc_read_cmdsts(priv, AVE_DESCID_RX,
584 priv->rx_pos);
585 if (!(cmdsts & AVE_STS_OWN))
586 /* hardware ownership, no received packets */
587 return -EAGAIN;
588
589 ptr = net_rx_packets[priv->rx_pos] + priv->rx_off;
590 if (cmdsts & AVE_STS_OK)
591 break;
592
593 pr_warn("%s: bad packet[%d] status:%08x ptr:%p\n",
594 priv->phydev->dev->name, priv->rx_pos,
595 le32_to_cpu(cmdsts), ptr);
596 }
597
598 length = cmdsts & AVE_STS_PKTLEN_RX_MASK;
599
600 /* invalidate after DMA is done */
601 ave_cache_invalidate((uintptr_t)ptr, length);
602 *packetp = ptr;
603
604 return length;
605}
606
607static int ave_free_packet(struct udevice *dev, uchar *packet, int length)
608{
609 struct ave_private *priv = dev_get_priv(dev);
610
611 ave_cache_flush((uintptr_t)net_rx_packets[priv->rx_pos],
612 priv->rx_siz + priv->rx_off);
613
614 ave_desc_write_cmdsts(priv, AVE_DESCID_RX,
615 priv->rx_pos, priv->rx_siz);
616
617 if (++priv->rx_pos >= PKTBUFSRX)
618 priv->rx_pos = 0;
619
620 return 0;
621}
622
623static int ave_pro4_get_pinmode(struct ave_private *priv)
624{
625 u32 reg, mask, val = 0;
626
627 if (priv->regmap_arg > 0)
628 return -EINVAL;
629
630 mask = SG_ETPINMODE_RMII(0);
631
632 switch (priv->phy_mode) {
633 case PHY_INTERFACE_MODE_RMII:
634 val = SG_ETPINMODE_RMII(0);
635 break;
636 case PHY_INTERFACE_MODE_MII:
637 case PHY_INTERFACE_MODE_RGMII:
638 break;
639 default:
640 return -EINVAL;
641 }
642
643 regmap_read(priv->regmap, SG_ETPINMODE, &reg);
644 reg &= ~mask;
645 reg |= val;
646 regmap_write(priv->regmap, SG_ETPINMODE, reg);
647
648 return 0;
649}
650
651static int ave_ld11_get_pinmode(struct ave_private *priv)
652{
653 u32 reg, mask, val = 0;
654
655 if (priv->regmap_arg > 0)
656 return -EINVAL;
657
658 mask = SG_ETPINMODE_EXTPHY | SG_ETPINMODE_RMII(0);
659
660 switch (priv->phy_mode) {
661 case PHY_INTERFACE_MODE_INTERNAL:
662 break;
663 case PHY_INTERFACE_MODE_RMII:
664 val = SG_ETPINMODE_EXTPHY | SG_ETPINMODE_RMII(0);
665 break;
666 default:
667 return -EINVAL;
668 }
669
670 regmap_read(priv->regmap, SG_ETPINMODE, &reg);
671 reg &= ~mask;
672 reg |= val;
673 regmap_write(priv->regmap, SG_ETPINMODE, reg);
674
675 return 0;
676}
677
678static int ave_ld20_get_pinmode(struct ave_private *priv)
679{
680 u32 reg, mask, val = 0;
681
682 if (priv->regmap_arg > 0)
683 return -EINVAL;
684
685 mask = SG_ETPINMODE_RMII(0);
686
687 switch (priv->phy_mode) {
688 case PHY_INTERFACE_MODE_RMII:
689 val = SG_ETPINMODE_RMII(0);
690 break;
691 case PHY_INTERFACE_MODE_RGMII:
692 break;
693 default:
694 return -EINVAL;
695 }
696
697 regmap_read(priv->regmap, SG_ETPINMODE, &reg);
698 reg &= ~mask;
699 reg |= val;
700 regmap_write(priv->regmap, SG_ETPINMODE, reg);
701
702 return 0;
703}
704
705static int ave_pxs3_get_pinmode(struct ave_private *priv)
706{
707 u32 reg, mask, val = 0;
708
709 if (priv->regmap_arg > 1)
710 return -EINVAL;
711
712 mask = SG_ETPINMODE_RMII(priv->regmap_arg);
713
714 switch (priv->phy_mode) {
715 case PHY_INTERFACE_MODE_RMII:
716 val = SG_ETPINMODE_RMII(priv->regmap_arg);
717 break;
718 case PHY_INTERFACE_MODE_RGMII:
719 break;
720 default:
721 return -EINVAL;
722 }
723
724 regmap_read(priv->regmap, SG_ETPINMODE, &reg);
725 reg &= ~mask;
726 reg |= val;
727 regmap_write(priv->regmap, SG_ETPINMODE, reg);
728
729 return 0;
730}
731
732static int ave_ofdata_to_platdata(struct udevice *dev)
733{
734 struct eth_pdata *pdata = dev_get_platdata(dev);
735 struct ave_private *priv = dev_get_priv(dev);
736 struct ofnode_phandle_args args;
737 const char *phy_mode;
738 const u32 *valp;
739 int ret, nc, nr;
740 const char *name;
741
742 priv->data = (const struct ave_soc_data *)dev_get_driver_data(dev);
743 if (!priv->data)
744 return -EINVAL;
745
746 pdata->iobase = devfdt_get_addr(dev);
747 pdata->phy_interface = -1;
748 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
749 NULL);
750 if (phy_mode)
751 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
752 if (pdata->phy_interface == -1) {
753 dev_err(dev, "Invalid PHY interface '%s'\n", phy_mode);
754 return -EINVAL;
755 }
756
757 pdata->max_speed = 0;
758 valp = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed",
759 NULL);
760 if (valp)
761 pdata->max_speed = fdt32_to_cpu(*valp);
762
763 for (nc = 0; nc < AVE_MAX_CLKS; nc++) {
764 name = priv->data->clock_names[nc];
765 if (!name)
766 break;
767 ret = clk_get_by_name(dev, name, &priv->clk[nc]);
768 if (ret) {
769 dev_err(dev, "Failed to get clocks property: %d\n",
770 ret);
771 goto out_clk_free;
772 }
773 priv->nclks++;
774 }
775
776 for (nr = 0; nr < AVE_MAX_RSTS; nr++) {
777 name = priv->data->reset_names[nr];
778 if (!name)
779 break;
780 ret = reset_get_by_name(dev, name, &priv->rst[nr]);
781 if (ret) {
782 dev_err(dev, "Failed to get resets property: %d\n",
783 ret);
784 goto out_reset_free;
785 }
786 priv->nrsts++;
787 }
788
789 ret = dev_read_phandle_with_args(dev, "socionext,syscon-phy-mode",
790 NULL, 1, 0, &args);
791 if (ret) {
792 dev_err(dev, "Failed to get syscon-phy-mode property: %d\n",
793 ret);
794 goto out_reset_free;
795 }
796
797 priv->regmap = syscon_node_to_regmap(args.node);
798 if (IS_ERR(priv->regmap)) {
799 ret = PTR_ERR(priv->regmap);
800 dev_err(dev, "can't get syscon: %d\n", ret);
801 goto out_reset_free;
802 }
803
804 if (args.args_count != 1) {
805 ret = -EINVAL;
806 dev_err(dev, "Invalid argument of syscon-phy-mode\n");
807 goto out_reset_free;
808 }
809
810 priv->regmap_arg = args.args[0];
811
812 return 0;
813
814out_reset_free:
815 while (--nr >= 0)
816 reset_free(&priv->rst[nr]);
817out_clk_free:
818 while (--nc >= 0)
819 clk_free(&priv->clk[nc]);
820
821 return ret;
822}
823
824static int ave_probe(struct udevice *dev)
825{
826 struct eth_pdata *pdata = dev_get_platdata(dev);
827 struct ave_private *priv = dev_get_priv(dev);
828 int ret, nc, nr;
829
830 priv->data = (const struct ave_soc_data *)dev_get_driver_data(dev);
831 if (!priv->data)
832 return -EINVAL;
833
834 priv->iobase = pdata->iobase;
835 priv->phy_mode = pdata->phy_interface;
836 priv->max_speed = pdata->max_speed;
837
838 ret = priv->data->get_pinmode(priv);
839 if (ret) {
840 dev_err(dev, "Invalid phy-mode\n");
841 return -EINVAL;
842 }
843
844 for (nc = 0; nc < priv->nclks; nc++) {
845 ret = clk_enable(&priv->clk[nc]);
846 if (ret) {
847 dev_err(dev, "Failed to enable clk: %d\n", ret);
848 goto out_clk_release;
849 }
850 }
851
852 for (nr = 0; nr < priv->nrsts; nr++) {
853 ret = reset_deassert(&priv->rst[nr]);
854 if (ret) {
855 dev_err(dev, "Failed to deassert reset: %d\n", ret);
856 goto out_reset_release;
857 }
858 }
859
860 ave_reset(priv);
861
862 ret = ave_mdiobus_init(priv, dev->name);
863 if (ret) {
864 dev_err(dev, "Failed to initialize mdiobus: %d\n", ret);
865 goto out_reset_release;
866 }
867
868 priv->bus = miiphy_get_dev_by_name(dev->name);
869
870 ret = ave_phy_init(priv, dev);
871 if (ret) {
872 dev_err(dev, "Failed to initialize phy: %d\n", ret);
873 goto out_mdiobus_release;
874 }
875
876 return 0;
877
878out_mdiobus_release:
879 mdio_unregister(priv->bus);
880 mdio_free(priv->bus);
881out_reset_release:
882 reset_release_all(priv->rst, nr);
883out_clk_release:
884 clk_release_all(priv->clk, nc);
885
886 return ret;
887}
888
889static int ave_remove(struct udevice *dev)
890{
891 struct ave_private *priv = dev_get_priv(dev);
892
893 free(priv->phydev);
894 mdio_unregister(priv->bus);
895 mdio_free(priv->bus);
896 reset_release_all(priv->rst, priv->nrsts);
897 clk_release_all(priv->clk, priv->nclks);
898
899 return 0;
900}
901
902static const struct eth_ops ave_ops = {
903 .start = ave_start,
904 .stop = ave_stop,
905 .send = ave_send,
906 .recv = ave_recv,
907 .free_pkt = ave_free_packet,
908 .write_hwaddr = ave_write_hwaddr,
909};
910
911static const struct ave_soc_data ave_pro4_data = {
912 .is_desc_64bit = false,
913 .clock_names = {
914 "gio", "ether", "ether-gb", "ether-phy",
915 },
916 .reset_names = {
917 "gio", "ether",
918 },
919 .get_pinmode = ave_pro4_get_pinmode,
920};
921
922static const struct ave_soc_data ave_pxs2_data = {
923 .is_desc_64bit = false,
924 .clock_names = {
925 "ether",
926 },
927 .reset_names = {
928 "ether",
929 },
930 .get_pinmode = ave_pro4_get_pinmode,
931};
932
933static const struct ave_soc_data ave_ld11_data = {
934 .is_desc_64bit = false,
935 .clock_names = {
936 "ether",
937 },
938 .reset_names = {
939 "ether",
940 },
941 .get_pinmode = ave_ld11_get_pinmode,
942};
943
944static const struct ave_soc_data ave_ld20_data = {
945 .is_desc_64bit = true,
946 .clock_names = {
947 "ether",
948 },
949 .reset_names = {
950 "ether",
951 },
952 .get_pinmode = ave_ld20_get_pinmode,
953};
954
955static const struct ave_soc_data ave_pxs3_data = {
956 .is_desc_64bit = false,
957 .clock_names = {
958 "ether",
959 },
960 .reset_names = {
961 "ether",
962 },
963 .get_pinmode = ave_pxs3_get_pinmode,
964};
965
966static const struct udevice_id ave_ids[] = {
967 {
968 .compatible = "socionext,uniphier-pro4-ave4",
969 .data = (ulong)&ave_pro4_data,
970 },
971 {
972 .compatible = "socionext,uniphier-pxs2-ave4",
973 .data = (ulong)&ave_pxs2_data,
974 },
975 {
976 .compatible = "socionext,uniphier-ld11-ave4",
977 .data = (ulong)&ave_ld11_data,
978 },
979 {
980 .compatible = "socionext,uniphier-ld20-ave4",
981 .data = (ulong)&ave_ld20_data,
982 },
983 {
984 .compatible = "socionext,uniphier-pxs3-ave4",
985 .data = (ulong)&ave_pxs3_data,
986 },
987 { /* Sentinel */ }
988};
989
990U_BOOT_DRIVER(ave) = {
991 .name = "ave",
992 .id = UCLASS_ETH,
993 .of_match = ave_ids,
994 .probe = ave_probe,
995 .remove = ave_remove,
996 .ofdata_to_platdata = ave_ofdata_to_platdata,
997 .ops = &ave_ops,
998 .priv_auto_alloc_size = sizeof(struct ave_private),
999 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
1000};
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