[J-u-boot.git] / arch / arm / mach-rockchip / sdram.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
 */

#include <common.h>
#include <dm.h>
#include <init.h>
#include <ram.h>
#include <asm/io.h>
#include <asm/arch-rockchip/sdram.h>
#include <dm/uclass-internal.h>

DECLARE_GLOBAL_DATA_PTR;

#define TRUST_PARAMETER_OFFSET    (34 * 1024 * 1024)

struct tos_parameter_t {
	u32 version;
	u32 checksum;
	struct {
		char name[8];
		s64 phy_addr;
		u32 size;
		u32 flags;
	} tee_mem;
	struct {
		char name[8];
		s64 phy_addr;
		u32 size;
		u32 flags;
	} drm_mem;
	s64 reserve[8];
};

int dram_init_banksize(void)
{
	size_t top = min((unsigned long)(gd->ram_size + CONFIG_SYS_SDRAM_BASE),
			 gd->ram_top);

#ifdef CONFIG_ARM64
	/* Reserve 0x200000 for ATF bl31 */
	gd->bd->bi_dram[0].start = 0x200000;
	gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;
#else
#ifdef CONFIG_SPL_OPTEE
	struct tos_parameter_t *tos_parameter;

	tos_parameter = (struct tos_parameter_t *)(CONFIG_SYS_SDRAM_BASE +
			TRUST_PARAMETER_OFFSET);

	if (tos_parameter->tee_mem.flags == 1) {
		gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
		gd->bd->bi_dram[0].size = tos_parameter->tee_mem.phy_addr
					- CONFIG_SYS_SDRAM_BASE;
		gd->bd->bi_dram[1].start = tos_parameter->tee_mem.phy_addr +
					tos_parameter->tee_mem.size;
		gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
					+ top - gd->bd->bi_dram[1].start;
	} else {
		gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
		gd->bd->bi_dram[0].size = 0x8400000;
		/* Reserve 32M for OPTEE with TA */
		gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE
					+ gd->bd->bi_dram[0].size + 0x2000000;
		gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
					+ top - gd->bd->bi_dram[1].start;
	}
#else
	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
	gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;
#endif
#endif

	return 0;
}

size_t rockchip_sdram_size(phys_addr_t reg)
{
	u32 rank, cs0_col, bk, cs0_row, cs1_row, bw, row_3_4;
	size_t chipsize_mb = 0;
	size_t size_mb = 0;
	u32 ch;
	u32 cs1_col = 0;
	u32 bg = 0;
	u32 dbw, dram_type;
	u32 sys_reg2 = readl(reg);
	u32 sys_reg3 = readl(reg + 4);
	u32 ch_num = 1 + ((sys_reg2 >> SYS_REG_NUM_CH_SHIFT)
		       & SYS_REG_NUM_CH_MASK);

	dram_type = (sys_reg2 >> SYS_REG_DDRTYPE_SHIFT) & SYS_REG_DDRTYPE_MASK;
	debug("%s %x %x\n", __func__, (u32)reg, sys_reg2);
	for (ch = 0; ch < ch_num; ch++) {
		rank = 1 + (sys_reg2 >> SYS_REG_RANK_SHIFT(ch) &
			SYS_REG_RANK_MASK);
		cs0_col = 9 + (sys_reg2 >> SYS_REG_COL_SHIFT(ch) &
			  SYS_REG_COL_MASK);
		cs1_col = cs0_col;
		bk = 3 - ((sys_reg2 >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK);
		if ((sys_reg3 >> SYS_REG_VERSION_SHIFT &
		     SYS_REG_VERSION_MASK) == 0x2) {
			cs1_col = 9 + (sys_reg3 >> SYS_REG_CS1_COL_SHIFT(ch) &
				  SYS_REG_CS1_COL_MASK);
			if (((sys_reg3 >> SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) &
			    SYS_REG_EXTEND_CS0_ROW_MASK) << 2) + (sys_reg2 >>
			    SYS_REG_CS0_ROW_SHIFT(ch) &
			    SYS_REG_CS0_ROW_MASK) == 7)
				cs0_row = 12;
			else
				cs0_row = 13 + (sys_reg2 >>
					  SYS_REG_CS0_ROW_SHIFT(ch) &
					  SYS_REG_CS0_ROW_MASK) +
					  ((sys_reg3 >>
					  SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) &
					  SYS_REG_EXTEND_CS0_ROW_MASK) << 2);
			if (((sys_reg3 >> SYS_REG_EXTEND_CS1_ROW_SHIFT(ch) &
			    SYS_REG_EXTEND_CS1_ROW_MASK) << 2) + (sys_reg2 >>
			    SYS_REG_CS1_ROW_SHIFT(ch) &
			    SYS_REG_CS1_ROW_MASK) == 7)
				cs1_row = 12;
			else
				cs1_row = 13 + (sys_reg2 >>
					  SYS_REG_CS1_ROW_SHIFT(ch) &
					  SYS_REG_CS1_ROW_MASK) +
					  ((sys_reg3 >>
					  SYS_REG_EXTEND_CS1_ROW_SHIFT(ch) &
					  SYS_REG_EXTEND_CS1_ROW_MASK) << 2);
		} else {
			cs0_row = 13 + (sys_reg2 >> SYS_REG_CS0_ROW_SHIFT(ch) &
				SYS_REG_CS0_ROW_MASK);
			cs1_row = 13 + (sys_reg2 >> SYS_REG_CS1_ROW_SHIFT(ch) &
				SYS_REG_CS1_ROW_MASK);
		}
		bw = (2 >> ((sys_reg2 >> SYS_REG_BW_SHIFT(ch)) &
			SYS_REG_BW_MASK));
		row_3_4 = sys_reg2 >> SYS_REG_ROW_3_4_SHIFT(ch) &
			SYS_REG_ROW_3_4_MASK;
		if (dram_type == DDR4) {
			dbw = (sys_reg2 >> SYS_REG_DBW_SHIFT(ch)) &
				SYS_REG_DBW_MASK;
			bg = (dbw == 2) ? 2 : 1;
		}
		chipsize_mb = (1 << (cs0_row + cs0_col + bk + bg + bw - 20));

		if (rank > 1)
			chipsize_mb += chipsize_mb >> ((cs0_row - cs1_row) +
				       (cs0_col - cs1_col));
		if (row_3_4)
			chipsize_mb = chipsize_mb * 3 / 4;
		size_mb += chipsize_mb;
		if (rank > 1)
			debug("rank %d cs0_col %d cs1_col %d bk %d cs0_row %d\
			       cs1_row %d bw %d row_3_4 %d\n",
			       rank, cs0_col, cs1_col, bk, cs0_row,
			       cs1_row, bw, row_3_4);
		else
			debug("rank %d cs0_col %d bk %d cs0_row %d\
			       bw %d row_3_4 %d\n",
			       rank, cs0_col, bk, cs0_row,
			       bw, row_3_4);
	}

	/*
	 * This is workaround for issue we can't get correct size for 4GB ram
	 * in 32bit system and available before we really need ram space
	 * out of 4GB, eg.enable ARM LAPE(rk3288 supports 8GB ram).
	 * The size of 4GB is '0x1 00000000', and this value will be truncated
	 * to 0 in 32bit system, and system can not get correct ram size.
	 * Rockchip SoCs reserve a blob of space for peripheral near 4GB,
	 * and we are now setting SDRAM_MAX_SIZE as max available space for
	 * ram in 4GB, so we can use this directly to workaround the issue.
	 * TODO:
	 *   1. update correct value for SDRAM_MAX_SIZE as what dram
	 *   controller sees.
	 *   2. update board_get_usable_ram_top() and dram_init_banksize()
	 *   to reserve memory for peripheral space after previous update.
	 */
	if (size_mb > (SDRAM_MAX_SIZE >> 20))
		size_mb = (SDRAM_MAX_SIZE >> 20);

	return (size_t)size_mb << 20;
}

int dram_init(void)
{
	struct ram_info ram;
	struct udevice *dev;
	int ret;

	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
	if (ret) {
		debug("DRAM init failed: %d\n", ret);
		return ret;
	}
	ret = ram_get_info(dev, &ram);
	if (ret) {
		debug("Cannot get DRAM size: %d\n", ret);
		return ret;
	}
	gd->ram_size = ram.size;
	debug("SDRAM base=%lx, size=%lx\n",
	      (unsigned long)ram.base, (unsigned long)ram.size);

	return 0;
}

ulong board_get_usable_ram_top(ulong total_size)
{
	unsigned long top = CONFIG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE;

	return (gd->ram_top > top) ? top : gd->ram_top;
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
6d1970fa KY	2	/*
6d1970fa KY	3	* Copyright (C) 2017 Rockchip Electronics Co., Ltd.
6d1970fa KY	4	*/
	5
	6	#include <common.h>
	7	#include <dm.h>
67c4e9f8	8	#include <init.h>
6d1970fa KY	9	#include <ram.h>
6d1970fa KY	10	#include <asm/io.h>
5d19ddf0	11	#include <asm/arch-rockchip/sdram.h>
6d1970fa KY	12	#include <dm/uclass-internal.h>
	13
	14	DECLARE_GLOBAL_DATA_PTR;
5eb9a78f KY	15
	16	#define TRUST_PARAMETER_OFFSET (34 * 1024 * 1024)
	17
	18	struct tos_parameter_t {
	19	u32 version;
	20	u32 checksum;
	21	struct {
	22	char name[8];
	23	s64 phy_addr;
	24	u32 size;
	25	u32 flags;
	26	} tee_mem;
	27	struct {
	28	char name[8];
	29	s64 phy_addr;
	30	u32 size;
	31	u32 flags;
	32	} drm_mem;
	33	s64 reserve[8];
	34	};
	35
	36	int dram_init_banksize(void)
	37	{
	38	size_t top = min((unsigned long)(gd->ram_size + CONFIG_SYS_SDRAM_BASE),
	39	gd->ram_top);
	40
	41	#ifdef CONFIG_ARM64
	42	/* Reserve 0x200000 for ATF bl31 */
	43	gd->bd->bi_dram[0].start = 0x200000;
	44	gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;
	45	#else
	46	#ifdef CONFIG_SPL_OPTEE
	47	struct tos_parameter_t *tos_parameter;
	48
	49	tos_parameter = (struct tos_parameter_t *)(CONFIG_SYS_SDRAM_BASE +
	50	TRUST_PARAMETER_OFFSET);
	51
	52	if (tos_parameter->tee_mem.flags == 1) {
	53	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
	54	gd->bd->bi_dram[0].size = tos_parameter->tee_mem.phy_addr
	55	- CONFIG_SYS_SDRAM_BASE;
	56	gd->bd->bi_dram[1].start = tos_parameter->tee_mem.phy_addr +
	57	tos_parameter->tee_mem.size;
	58	gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
	59	+ top - gd->bd->bi_dram[1].start;
	60	} else {
	61	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
	62	gd->bd->bi_dram[0].size = 0x8400000;
	63	/* Reserve 32M for OPTEE with TA */
	64	gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE
	65	+ gd->bd->bi_dram[0].size + 0x2000000;
	66	gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
	67	+ top - gd->bd->bi_dram[1].start;
	68	}
	69	#else
	70	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
	71	gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;
	72	#endif
	73	#endif
	74
	75	return 0;
	76	}
	77
6d1970fa KY	78	size_t rockchip_sdram_size(phys_addr_t reg)
6d1970fa KY	79	{
9a46f2a4	80	u32 rank, cs0_col, bk, cs0_row, cs1_row, bw, row_3_4;
6d1970fa KY	81	size_t chipsize_mb = 0;
	82	size_t size_mb = 0;
	83	u32 ch;
9a46f2a4 KY	84	u32 cs1_col = 0;
	85	u32 bg = 0;
	86	u32 dbw, dram_type;
c7becc3a	87	u32 sys_reg2 = readl(reg);
9a46f2a4	88	u32 sys_reg3 = readl(reg + 4);
c7becc3a	89	u32 ch_num = 1 + ((sys_reg2 >> SYS_REG_NUM_CH_SHIFT)
6d1970fa KY	90	& SYS_REG_NUM_CH_MASK);
6d1970fa KY	91
c7becc3a KY	92	dram_type = (sys_reg2 >> SYS_REG_DDRTYPE_SHIFT) & SYS_REG_DDRTYPE_MASK;
c7becc3a KY	93	debug("%s %x %x\n", __func__, (u32)reg, sys_reg2);
6d1970fa	94	for (ch = 0; ch < ch_num; ch++) {
c7becc3a	95	rank = 1 + (sys_reg2 >> SYS_REG_RANK_SHIFT(ch) &
6d1970fa	96	SYS_REG_RANK_MASK);
c7becc3a	97	cs0_col = 9 + (sys_reg2 >> SYS_REG_COL_SHIFT(ch) &
9a46f2a4 KY	98	SYS_REG_COL_MASK);
9a46f2a4 KY	99	cs1_col = cs0_col;
c7becc3a	100	bk = 3 - ((sys_reg2 >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK);
9a46f2a4 KY	101	if ((sys_reg3 >> SYS_REG_VERSION_SHIFT &
	102	SYS_REG_VERSION_MASK) == 0x2) {
	103	cs1_col = 9 + (sys_reg3 >> SYS_REG_CS1_COL_SHIFT(ch) &
	104	SYS_REG_CS1_COL_MASK);
	105	if (((sys_reg3 >> SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) &
c7becc3a	106	SYS_REG_EXTEND_CS0_ROW_MASK) << 2) + (sys_reg2 >>
9a46f2a4 KY	107	SYS_REG_CS0_ROW_SHIFT(ch) &
	108	SYS_REG_CS0_ROW_MASK) == 7)
	109	cs0_row = 12;
	110	else
c7becc3a	111	cs0_row = 13 + (sys_reg2 >>
9a46f2a4 KY	112	SYS_REG_CS0_ROW_SHIFT(ch) &
	113	SYS_REG_CS0_ROW_MASK) +
	114	((sys_reg3 >>
	115	SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) &
	116	SYS_REG_EXTEND_CS0_ROW_MASK) << 2);
	117	if (((sys_reg3 >> SYS_REG_EXTEND_CS1_ROW_SHIFT(ch) &
c7becc3a	118	SYS_REG_EXTEND_CS1_ROW_MASK) << 2) + (sys_reg2 >>
9a46f2a4 KY	119	SYS_REG_CS1_ROW_SHIFT(ch) &
	120	SYS_REG_CS1_ROW_MASK) == 7)
	121	cs1_row = 12;
	122	else
c7becc3a	123	cs1_row = 13 + (sys_reg2 >>
9a46f2a4 KY	124	SYS_REG_CS1_ROW_SHIFT(ch) &
	125	SYS_REG_CS1_ROW_MASK) +
	126	((sys_reg3 >>
	127	SYS_REG_EXTEND_CS1_ROW_SHIFT(ch) &
	128	SYS_REG_EXTEND_CS1_ROW_MASK) << 2);
	129	} else {
c7becc3a	130	cs0_row = 13 + (sys_reg2 >> SYS_REG_CS0_ROW_SHIFT(ch) &
6d1970fa	131	SYS_REG_CS0_ROW_MASK);
c7becc3a	132	cs1_row = 13 + (sys_reg2 >> SYS_REG_CS1_ROW_SHIFT(ch) &
6d1970fa	133	SYS_REG_CS1_ROW_MASK);
9a46f2a4	134	}
c7becc3a	135	bw = (2 >> ((sys_reg2 >> SYS_REG_BW_SHIFT(ch)) &
6d1970fa	136	SYS_REG_BW_MASK));
c7becc3a	137	row_3_4 = sys_reg2 >> SYS_REG_ROW_3_4_SHIFT(ch) &
6d1970fa	138	SYS_REG_ROW_3_4_MASK;
9a46f2a4	139	if (dram_type == DDR4) {
c7becc3a	140	dbw = (sys_reg2 >> SYS_REG_DBW_SHIFT(ch)) &
9a46f2a4 KY	141	SYS_REG_DBW_MASK;
	142	bg = (dbw == 2) ? 2 : 1;
	143	}
	144	chipsize_mb = (1 << (cs0_row + cs0_col + bk + bg + bw - 20));
6d1970fa KY	145
6d1970fa KY	146	if (rank > 1)
9a46f2a4 KY	147	chipsize_mb += chipsize_mb >> ((cs0_row - cs1_row) +
9a46f2a4 KY	148	(cs0_col - cs1_col));
6d1970fa KY	149	if (row_3_4)
	150	chipsize_mb = chipsize_mb * 3 / 4;
	151	size_mb += chipsize_mb;
9a46f2a4 KY	152	if (rank > 1)
	153	debug("rank %d cs0_col %d cs1_col %d bk %d cs0_row %d\
	154	cs1_row %d bw %d row_3_4 %d\n",
	155	rank, cs0_col, cs1_col, bk, cs0_row,
	156	cs1_row, bw, row_3_4);
	157	else
	158	debug("rank %d cs0_col %d bk %d cs0_row %d\
	159	bw %d row_3_4 %d\n",
	160	rank, cs0_col, bk, cs0_row,
	161	bw, row_3_4);
6d1970fa KY	162	}
6d1970fa KY	163
3119ecc4 KY	164	/*
	165	* This is workaround for issue we can't get correct size for 4GB ram
	166	* in 32bit system and available before we really need ram space
	167	* out of 4GB, eg.enable ARM LAPE(rk3288 supports 8GB ram).
	168	* The size of 4GB is '0x1 00000000', and this value will be truncated
	169	* to 0 in 32bit system, and system can not get correct ram size.
	170	* Rockchip SoCs reserve a blob of space for peripheral near 4GB,
	171	* and we are now setting SDRAM_MAX_SIZE as max available space for
	172	* ram in 4GB, so we can use this directly to workaround the issue.
	173	* TODO:
	174	* 1. update correct value for SDRAM_MAX_SIZE as what dram
	175	* controller sees.
	176	* 2. update board_get_usable_ram_top() and dram_init_banksize()
	177	* to reserve memory for peripheral space after previous update.
	178	*/
	179	if (size_mb > (SDRAM_MAX_SIZE >> 20))
	180	size_mb = (SDRAM_MAX_SIZE >> 20);
	181
6d1970fa KY	182	return (size_t)size_mb << 20;
	183	}
	184
	185	int dram_init(void)
	186	{
	187	struct ram_info ram;
	188	struct udevice *dev;
	189	int ret;
	190
	191	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
	192	if (ret) {
	193	debug("DRAM init failed: %d\n", ret);
	194	return ret;
	195	}
	196	ret = ram_get_info(dev, &ram);
	197	if (ret) {
	198	debug("Cannot get DRAM size: %d\n", ret);
	199	return ret;
	200	}
	201	gd->ram_size = ram.size;
	202	debug("SDRAM base=%lx, size=%lx\n",
	203	(unsigned long)ram.base, (unsigned long)ram.size);
	204
	205	return 0;
	206	}
	207
	208	ulong board_get_usable_ram_top(ulong total_size)
	209	{
	210	unsigned long top = CONFIG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE;
	211
	212	return (gd->ram_top > top) ? top : gd->ram_top;
	213	}