[J-u-boot.git] / drivers / serial / serial_mtk.c

// SPDX-License-Identifier: GPL-2.0
/*
 * MediaTek High-speed UART driver
 *
 * Copyright (C) 2018 MediaTek Inc.
 * Author: Weijie Gao <[email protected]>
 */

#include <clk.h>
#include <common.h>
#include <div64.h>
#include <dm.h>
#include <errno.h>
#include <log.h>
#include <serial.h>
#include <watchdog.h>
#include <asm/io.h>
#include <asm/types.h>
#include <linux/err.h>

struct mtk_serial_regs {
	u32 rbr;
	u32 ier;
	u32 fcr;
	u32 lcr;
	u32 mcr;
	u32 lsr;
	u32 msr;
	u32 spr;
	u32 mdr1;
	u32 highspeed;
	u32 sample_count;
	u32 sample_point;
	u32 fracdiv_l;
	u32 fracdiv_m;
	u32 escape_en;
	u32 guard;
	u32 rx_sel;
};

#define thr rbr
#define iir fcr
#define dll rbr
#define dlm ier

#define UART_LCR_WLS_8	0x03		/* 8 bit character length */
#define UART_LCR_DLAB	0x80		/* Divisor latch access bit */

#define UART_LSR_DR	0x01		/* Data ready */
#define UART_LSR_THRE	0x20		/* Xmit holding register empty */
#define UART_LSR_TEMT	0x40		/* Xmitter empty */

#define UART_MCR_DTR	0x01		/* DTR   */
#define UART_MCR_RTS	0x02		/* RTS   */

#define UART_FCR_FIFO_EN	0x01	/* Fifo enable */
#define UART_FCR_RXSR		0x02	/* Receiver soft reset */
#define UART_FCR_TXSR		0x04	/* Transmitter soft reset */

#define UART_MCRVAL (UART_MCR_DTR | \
		     UART_MCR_RTS)

/* Clear & enable FIFOs */
#define UART_FCRVAL (UART_FCR_FIFO_EN | \
		     UART_FCR_RXSR |	\
		     UART_FCR_TXSR)

/* the data is correct if the real baud is within 3%. */
#define BAUD_ALLOW_MAX(baud)	((baud) + (baud) * 3 / 100)
#define BAUD_ALLOW_MIX(baud)	((baud) - (baud) * 3 / 100)

struct mtk_serial_priv {
	struct mtk_serial_regs __iomem *regs;
	u32 clock;
};

static void _mtk_serial_setbrg(struct mtk_serial_priv *priv, int baud)
{
	bool support_clk12m_baud115200;
	u32 quot, samplecount, realbaud;

	if ((baud <= 115200) && (priv->clock == 12000000))
		support_clk12m_baud115200 = true;
	else
		support_clk12m_baud115200 = false;

	if (baud <= 115200) {
		writel(0, &priv->regs->highspeed);
		quot = DIV_ROUND_CLOSEST(priv->clock, 16 * baud);

		if (support_clk12m_baud115200) {
			writel(3, &priv->regs->highspeed);
			quot = DIV_ROUND_CLOSEST(priv->clock, 256 * baud);
			if (quot == 0)
				quot = 1;

			samplecount = DIV_ROUND_CLOSEST(priv->clock,
							quot * baud);
			if (samplecount != 0) {
				realbaud = priv->clock / samplecount / quot;
				if ((realbaud > BAUD_ALLOW_MAX(baud)) ||
				    (realbaud < BAUD_ALLOW_MIX(baud))) {
					pr_info("baud %d can't be handled\n",
						baud);
				}
			} else {
				pr_info("samplecount is 0\n");
			}
		}
	} else if (baud <= 576000) {
		writel(2, &priv->regs->highspeed);

		/* Set to next lower baudrate supported */
		if ((baud == 500000) || (baud == 576000))
			baud = 460800;
		quot = DIV_ROUND_UP(priv->clock, 4 * baud);
	} else {
		writel(3, &priv->regs->highspeed);
		quot = DIV_ROUND_UP(priv->clock, 256 * baud);
	}

	/* set divisor */
	writel(UART_LCR_WLS_8 | UART_LCR_DLAB, &priv->regs->lcr);
	writel(quot & 0xff, &priv->regs->dll);
	writel((quot >> 8) & 0xff, &priv->regs->dlm);
	writel(UART_LCR_WLS_8, &priv->regs->lcr);

	if (baud > 460800) {
		u32 tmp;

		tmp = DIV_ROUND_CLOSEST(priv->clock, quot * baud);
		writel(tmp - 1, &priv->regs->sample_count);
		writel((tmp - 2) >> 1, &priv->regs->sample_point);
	} else {
		writel(0, &priv->regs->sample_count);
		writel(0xff, &priv->regs->sample_point);
	}

	if (support_clk12m_baud115200) {
		writel(samplecount - 1, &priv->regs->sample_count);
		writel((samplecount - 2) >> 1, &priv->regs->sample_point);
	}
}

static int _mtk_serial_putc(struct mtk_serial_priv *priv, const char ch)
{
	if (!(readl(&priv->regs->lsr) & UART_LSR_THRE))
		return -EAGAIN;

	writel(ch, &priv->regs->thr);

	if (ch == '\n')
		WATCHDOG_RESET();

	return 0;
}

static int _mtk_serial_getc(struct mtk_serial_priv *priv)
{
	if (!(readl(&priv->regs->lsr) & UART_LSR_DR))
		return -EAGAIN;

	return readl(&priv->regs->rbr);
}

static int _mtk_serial_pending(struct mtk_serial_priv *priv, bool input)
{
	if (input)
		return (readl(&priv->regs->lsr) & UART_LSR_DR) ? 1 : 0;
	else
		return (readl(&priv->regs->lsr) & UART_LSR_THRE) ? 0 : 1;
}

#if defined(CONFIG_DM_SERIAL) && \
	(!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_DM))
static int mtk_serial_setbrg(struct udevice *dev, int baudrate)
{
	struct mtk_serial_priv *priv = dev_get_priv(dev);

	_mtk_serial_setbrg(priv, baudrate);

	return 0;
}

static int mtk_serial_putc(struct udevice *dev, const char ch)
{
	struct mtk_serial_priv *priv = dev_get_priv(dev);

	return _mtk_serial_putc(priv, ch);
}

static int mtk_serial_getc(struct udevice *dev)
{
	struct mtk_serial_priv *priv = dev_get_priv(dev);

	return _mtk_serial_getc(priv);
}

static int mtk_serial_pending(struct udevice *dev, bool input)
{
	struct mtk_serial_priv *priv = dev_get_priv(dev);

	return _mtk_serial_pending(priv, input);
}

static int mtk_serial_probe(struct udevice *dev)
{
	struct mtk_serial_priv *priv = dev_get_priv(dev);

	/* Disable interrupt */
	writel(0, &priv->regs->ier);

	writel(UART_MCRVAL, &priv->regs->mcr);
	writel(UART_FCRVAL, &priv->regs->fcr);

	return 0;
}

static int mtk_serial_of_to_plat(struct udevice *dev)
{
	struct mtk_serial_priv *priv = dev_get_priv(dev);
	fdt_addr_t addr;
	struct clk clk;
	int err;

	addr = dev_read_addr(dev);
	if (addr == FDT_ADDR_T_NONE)
		return -EINVAL;

	priv->regs = map_physmem(addr, 0, MAP_NOCACHE);

	err = clk_get_by_index(dev, 0, &clk);
	if (!err) {
		err = clk_get_rate(&clk);
		if (!IS_ERR_VALUE(err))
			priv->clock = err;
	} else if (err != -ENOENT && err != -ENODEV && err != -ENOSYS) {
		debug("mtk_serial: failed to get clock\n");
		return err;
	}

	if (!priv->clock)
		priv->clock = dev_read_u32_default(dev, "clock-frequency", 0);

	if (!priv->clock) {
		debug("mtk_serial: clock not defined\n");
		return -EINVAL;
	}

	return 0;
}

static const struct dm_serial_ops mtk_serial_ops = {
	.putc = mtk_serial_putc,
	.pending = mtk_serial_pending,
	.getc = mtk_serial_getc,
	.setbrg = mtk_serial_setbrg,
};

static const struct udevice_id mtk_serial_ids[] = {
	{ .compatible = "mediatek,hsuart" },
	{ .compatible = "mediatek,mt6577-uart" },
	{ }
};

U_BOOT_DRIVER(serial_mtk) = {
	.name = "serial_mtk",
	.id = UCLASS_SERIAL,
	.of_match = mtk_serial_ids,
	.of_to_plat = mtk_serial_of_to_plat,
	.priv_auto	= sizeof(struct mtk_serial_priv),
	.probe = mtk_serial_probe,
	.ops = &mtk_serial_ops,
	.flags = DM_FLAG_PRE_RELOC,
};
#else

DECLARE_GLOBAL_DATA_PTR;

#define DECLARE_HSUART_PRIV(port) \
	static struct mtk_serial_priv mtk_hsuart##port = { \
	.regs = (struct mtk_serial_regs *)CONFIG_SYS_NS16550_COM##port, \
	.clock = CONFIG_SYS_NS16550_CLK \
};

#define DECLARE_HSUART_FUNCTIONS(port) \
	static int mtk_serial##port##_init(void) \
	{ \
		writel(0, &mtk_hsuart##port.regs->ier); \
		writel(UART_MCRVAL, &mtk_hsuart##port.regs->mcr); \
		writel(UART_FCRVAL, &mtk_hsuart##port.regs->fcr); \
		_mtk_serial_setbrg(&mtk_hsuart##port, gd->baudrate); \
		return 0 ; \
	} \
	static void mtk_serial##port##_setbrg(void) \
	{ \
		_mtk_serial_setbrg(&mtk_hsuart##port, gd->baudrate); \
	} \
	static int mtk_serial##port##_getc(void) \
	{ \
		int err; \
		do { \
			err = _mtk_serial_getc(&mtk_hsuart##port); \
			if (err == -EAGAIN) \
				WATCHDOG_RESET(); \
		} while (err == -EAGAIN); \
		return err >= 0 ? err : 0; \
	} \
	static int mtk_serial##port##_tstc(void) \
	{ \
		return _mtk_serial_pending(&mtk_hsuart##port, true); \
	} \
	static void mtk_serial##port##_putc(const char c) \
	{ \
		int err; \
		if (c == '\n') \
			mtk_serial##port##_putc('\r'); \
		do { \
			err = _mtk_serial_putc(&mtk_hsuart##port, c); \
		} while (err == -EAGAIN); \
	} \
	static void mtk_serial##port##_puts(const char *s) \
	{ \
		while (*s) { \
			mtk_serial##port##_putc(*s++); \
		} \
	}

/* Serial device descriptor */
#define INIT_HSUART_STRUCTURE(port, __name) {	\
	.name	= __name,			\
	.start	= mtk_serial##port##_init,	\
	.stop	= NULL,				\
	.setbrg	= mtk_serial##port##_setbrg,	\
	.getc	= mtk_serial##port##_getc,	\
	.tstc	= mtk_serial##port##_tstc,	\
	.putc	= mtk_serial##port##_putc,	\
	.puts	= mtk_serial##port##_puts,	\
}

#define DECLARE_HSUART(port, __name) \
	DECLARE_HSUART_PRIV(port); \
	DECLARE_HSUART_FUNCTIONS(port); \
	struct serial_device mtk_hsuart##port##_device = \
		INIT_HSUART_STRUCTURE(port, __name);

#if !defined(CONFIG_CONS_INDEX)
#elif (CONFIG_CONS_INDEX < 1) || (CONFIG_CONS_INDEX > 6)
#error	"Invalid console index value."
#endif

#if CONFIG_CONS_INDEX == 1 && !defined(CONFIG_SYS_NS16550_COM1)
#error	"Console port 1 defined but not configured."
#elif CONFIG_CONS_INDEX == 2 && !defined(CONFIG_SYS_NS16550_COM2)
#error	"Console port 2 defined but not configured."
#elif CONFIG_CONS_INDEX == 3 && !defined(CONFIG_SYS_NS16550_COM3)
#error	"Console port 3 defined but not configured."
#elif CONFIG_CONS_INDEX == 4 && !defined(CONFIG_SYS_NS16550_COM4)
#error	"Console port 4 defined but not configured."
#elif CONFIG_CONS_INDEX == 5 && !defined(CONFIG_SYS_NS16550_COM5)
#error	"Console port 5 defined but not configured."
#elif CONFIG_CONS_INDEX == 6 && !defined(CONFIG_SYS_NS16550_COM6)
#error	"Console port 6 defined but not configured."
#endif

#if defined(CONFIG_SYS_NS16550_COM1)
DECLARE_HSUART(1, "mtk-hsuart0");
#endif
#if defined(CONFIG_SYS_NS16550_COM2)
DECLARE_HSUART(2, "mtk-hsuart1");
#endif
#if defined(CONFIG_SYS_NS16550_COM3)
DECLARE_HSUART(3, "mtk-hsuart2");
#endif
#if defined(CONFIG_SYS_NS16550_COM4)
DECLARE_HSUART(4, "mtk-hsuart3");
#endif
#if defined(CONFIG_SYS_NS16550_COM5)
DECLARE_HSUART(5, "mtk-hsuart4");
#endif
#if defined(CONFIG_SYS_NS16550_COM6)
DECLARE_HSUART(6, "mtk-hsuart5");
#endif

__weak struct serial_device *default_serial_console(void)
{
#if CONFIG_CONS_INDEX == 1
	return &mtk_hsuart1_device;
#elif CONFIG_CONS_INDEX == 2
	return &mtk_hsuart2_device;
#elif CONFIG_CONS_INDEX == 3
	return &mtk_hsuart3_device;
#elif CONFIG_CONS_INDEX == 4
	return &mtk_hsuart4_device;
#elif CONFIG_CONS_INDEX == 5
	return &mtk_hsuart5_device;
#elif CONFIG_CONS_INDEX == 6
	return &mtk_hsuart6_device;
#else
#error "Bad CONFIG_CONS_INDEX."
#endif
}

void mtk_serial_initialize(void)
{
#if defined(CONFIG_SYS_NS16550_COM1)
	serial_register(&mtk_hsuart1_device);
#endif
#if defined(CONFIG_SYS_NS16550_COM2)
	serial_register(&mtk_hsuart2_device);
#endif
#if defined(CONFIG_SYS_NS16550_COM3)
	serial_register(&mtk_hsuart3_device);
#endif
#if defined(CONFIG_SYS_NS16550_COM4)
	serial_register(&mtk_hsuart4_device);
#endif
#if defined(CONFIG_SYS_NS16550_COM5)
	serial_register(&mtk_hsuart5_device);
#endif
#if defined(CONFIG_SYS_NS16550_COM6)
	serial_register(&mtk_hsuart6_device);
#endif
}

#endif

#ifdef CONFIG_DEBUG_UART_MTK

#include <debug_uart.h>

static inline void _debug_uart_init(void)
{
	struct mtk_serial_priv priv;

	priv.regs = (void *) CONFIG_DEBUG_UART_BASE;
	priv.clock = CONFIG_DEBUG_UART_CLOCK;

	writel(0, &priv.regs->ier);
	writel(UART_MCRVAL, &priv.regs->mcr);
	writel(UART_FCRVAL, &priv.regs->fcr);

	_mtk_serial_setbrg(&priv, CONFIG_BAUDRATE);
}

static inline void _debug_uart_putc(int ch)
{
	struct mtk_serial_regs __iomem *regs =
		(void *) CONFIG_DEBUG_UART_BASE;

	while (!(readl(&regs->lsr) & UART_LSR_THRE))
		;

	writel(ch, &regs->thr);
}

DEBUG_UART_FUNCS

#endif
Commit	Line	Data
849b1160 RL	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* MediaTek High-speed UART driver
	4	*
	5	* Copyright (C) 2018 MediaTek Inc.
	6	* Author: Weijie Gao <[email protected]>
	7	*/
	8
	9	#include <clk.h>
	10	#include <common.h>
	11	#include <div64.h>
	12	#include <dm.h>
	13	#include <errno.h>
f7ae49fc	14	#include <log.h>
849b1160 RL	15	#include <serial.h>
	16	#include <watchdog.h>
	17	#include <asm/io.h>
	18	#include <asm/types.h>
61b29b82	19	#include <linux/err.h>
849b1160 RL	20
	21	struct mtk_serial_regs {
	22	u32 rbr;
	23	u32 ier;
	24	u32 fcr;
	25	u32 lcr;
	26	u32 mcr;
	27	u32 lsr;
	28	u32 msr;
	29	u32 spr;
	30	u32 mdr1;
	31	u32 highspeed;
	32	u32 sample_count;
	33	u32 sample_point;
	34	u32 fracdiv_l;
	35	u32 fracdiv_m;
	36	u32 escape_en;
	37	u32 guard;
	38	u32 rx_sel;
	39	};
	40
	41	#define thr rbr
	42	#define iir fcr
	43	#define dll rbr
	44	#define dlm ier
	45
	46	#define UART_LCR_WLS_8 0x03 /* 8 bit character length */
	47	#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
	48
	49	#define UART_LSR_DR 0x01 /* Data ready */
	50	#define UART_LSR_THRE 0x20 /* Xmit holding register empty */
99ced533 WG	51	#define UART_LSR_TEMT 0x40 /* Xmitter empty */
	52
	53	#define UART_MCR_DTR 0x01 /* DTR */
	54	#define UART_MCR_RTS 0x02 /* RTS */
	55
	56	#define UART_FCR_FIFO_EN 0x01 /* Fifo enable */
	57	#define UART_FCR_RXSR 0x02 /* Receiver soft reset */
	58	#define UART_FCR_TXSR 0x04 /* Transmitter soft reset */
	59
	60	#define UART_MCRVAL (UART_MCR_DTR \| \
	61	UART_MCR_RTS)
	62
	63	/* Clear & enable FIFOs */
	64	#define UART_FCRVAL (UART_FCR_FIFO_EN \| \
	65	UART_FCR_RXSR \| \
	66	UART_FCR_TXSR)
849b1160 RL	67
	68	/* the data is correct if the real baud is within 3%. */
	69	#define BAUD_ALLOW_MAX(baud) ((baud) + (baud) * 3 / 100)
	70	#define BAUD_ALLOW_MIX(baud) ((baud) - (baud) * 3 / 100)
	71
	72	struct mtk_serial_priv {
	73	struct mtk_serial_regs __iomem *regs;
	74	u32 clock;
	75	};
	76
	77	static void _mtk_serial_setbrg(struct mtk_serial_priv *priv, int baud)
	78	{
	79	bool support_clk12m_baud115200;
	80	u32 quot, samplecount, realbaud;
	81
	82	if ((baud <= 115200) && (priv->clock == 12000000))
	83	support_clk12m_baud115200 = true;
	84	else
	85	support_clk12m_baud115200 = false;
	86
	87	if (baud <= 115200) {
	88	writel(0, &priv->regs->highspeed);
	89	quot = DIV_ROUND_CLOSEST(priv->clock, 16 * baud);
	90
	91	if (support_clk12m_baud115200) {
	92	writel(3, &priv->regs->highspeed);
	93	quot = DIV_ROUND_CLOSEST(priv->clock, 256 * baud);
	94	if (quot == 0)
	95	quot = 1;
	96
	97	samplecount = DIV_ROUND_CLOSEST(priv->clock,
	98	quot * baud);
	99	if (samplecount != 0) {
	100	realbaud = priv->clock / samplecount / quot;
	101	if ((realbaud > BAUD_ALLOW_MAX(baud)) \|\|
	102	(realbaud < BAUD_ALLOW_MIX(baud))) {
	103	pr_info("baud %d can't be handled\n",
	104	baud);
	105	}
	106	} else {
	107	pr_info("samplecount is 0\n");
	108	}
	109	}
	110	} else if (baud <= 576000) {
	111	writel(2, &priv->regs->highspeed);
	112
	113	/* Set to next lower baudrate supported */
	114	if ((baud == 500000) \|\| (baud == 576000))
	115	baud = 460800;
	116	quot = DIV_ROUND_UP(priv->clock, 4 * baud);
	117	} else {
	118	writel(3, &priv->regs->highspeed);
	119	quot = DIV_ROUND_UP(priv->clock, 256 * baud);
	120	}
	121
	122	/* set divisor */
	123	writel(UART_LCR_WLS_8 \| UART_LCR_DLAB, &priv->regs->lcr);
	124	writel(quot & 0xff, &priv->regs->dll);
	125	writel((quot >> 8) & 0xff, &priv->regs->dlm);
	126	writel(UART_LCR_WLS_8, &priv->regs->lcr);
	127
	128	if (baud > 460800) {
	129	u32 tmp;
	130
131	tmp = DIV_ROUND_CLOSEST(priv->clock, quot * baud);
132	writel(tmp - 1, &priv->regs->sample_count);
133	writel((tmp - 2) >> 1, &priv->regs->sample_point);
134	} else {
135	writel(0, &priv->regs->sample_count);
136	writel(0xff, &priv->regs->sample_point);
137	}
138
139	if (support_clk12m_baud115200) {
140	writel(samplecount - 1, &priv->regs->sample_count);
141	writel((samplecount - 2) >> 1, &priv->regs->sample_point);
142	}
143	}
144
44fa676e WG	145	static int _mtk_serial_putc(struct mtk_serial_priv *priv, const char ch)
	146	{
	147	if (!(readl(&priv->regs->lsr) & UART_LSR_THRE))
	148	return -EAGAIN;
	149
	150	writel(ch, &priv->regs->thr);
	151
	152	if (ch == '\n')
	153	WATCHDOG_RESET();
	154
	155	return 0;
	156	}
	157
	158	static int _mtk_serial_getc(struct mtk_serial_priv *priv)
	159	{
	160	if (!(readl(&priv->regs->lsr) & UART_LSR_DR))
	161	return -EAGAIN;
	162
	163	return readl(&priv->regs->rbr);
	164	}
	165
	166	static int _mtk_serial_pending(struct mtk_serial_priv *priv, bool input)
	167	{
	168	if (input)
	169	return (readl(&priv->regs->lsr) & UART_LSR_DR) ? 1 : 0;
	170	else
	171	return (readl(&priv->regs->lsr) & UART_LSR_THRE) ? 0 : 1;
	172	}
	173
	174	#if defined(CONFIG_DM_SERIAL) && \
	175	(!defined(CONFIG_SPL_BUILD) \|\| defined(CONFIG_SPL_DM))
849b1160 RL	176	static int mtk_serial_setbrg(struct udevice *dev, int baudrate)
	177	{
	178	struct mtk_serial_priv *priv = dev_get_priv(dev);
	179
	180	_mtk_serial_setbrg(priv, baudrate);
	181
	182	return 0;
	183	}
	184
	185	static int mtk_serial_putc(struct udevice *dev, const char ch)
	186	{
	187	struct mtk_serial_priv *priv = dev_get_priv(dev);
	188
44fa676e	189	return _mtk_serial_putc(priv, ch);
849b1160 RL	190	}
	191
	192	static int mtk_serial_getc(struct udevice *dev)
	193	{
	194	struct mtk_serial_priv *priv = dev_get_priv(dev);
	195
44fa676e	196	return _mtk_serial_getc(priv);
849b1160 RL	197	}
	198
	199	static int mtk_serial_pending(struct udevice *dev, bool input)
	200	{
	201	struct mtk_serial_priv *priv = dev_get_priv(dev);
	202
44fa676e	203	return _mtk_serial_pending(priv, input);
849b1160 RL	204	}
	205
	206	static int mtk_serial_probe(struct udevice *dev)
	207	{
	208	struct mtk_serial_priv *priv = dev_get_priv(dev);
	209
	210	/* Disable interrupt */
	211	writel(0, &priv->regs->ier);
	212
99ced533 WG	213	writel(UART_MCRVAL, &priv->regs->mcr);
	214	writel(UART_FCRVAL, &priv->regs->fcr);
	215
849b1160 RL	216	return 0;
	217	}
	218
d1998a9f	219	static int mtk_serial_of_to_plat(struct udevice *dev)
849b1160 RL	220	{
	221	struct mtk_serial_priv *priv = dev_get_priv(dev);
	222	fdt_addr_t addr;
	223	struct clk clk;
	224	int err;
	225
	226	addr = dev_read_addr(dev);
	227	if (addr == FDT_ADDR_T_NONE)
	228	return -EINVAL;
	229
	230	priv->regs = map_physmem(addr, 0, MAP_NOCACHE);
	231
	232	err = clk_get_by_index(dev, 0, &clk);
	233	if (!err) {
	234	err = clk_get_rate(&clk);
	235	if (!IS_ERR_VALUE(err))
	236	priv->clock = err;
	237	} else if (err != -ENOENT && err != -ENODEV && err != -ENOSYS) {
	238	debug("mtk_serial: failed to get clock\n");
	239	return err;
	240	}
	241
	242	if (!priv->clock)
	243	priv->clock = dev_read_u32_default(dev, "clock-frequency", 0);
	244
	245	if (!priv->clock) {
	246	debug("mtk_serial: clock not defined\n");
	247	return -EINVAL;
	248	}
	249
	250	return 0;
	251	}
	252
	253	static const struct dm_serial_ops mtk_serial_ops = {
	254	.putc = mtk_serial_putc,
	255	.pending = mtk_serial_pending,
	256	.getc = mtk_serial_getc,
	257	.setbrg = mtk_serial_setbrg,
	258	};
	259
	260	static const struct udevice_id mtk_serial_ids[] = {
	261	{ .compatible = "mediatek,hsuart" },
	262	{ .compatible = "mediatek,mt6577-uart" },
	263	{ }
	264	};
	265
	266	U_BOOT_DRIVER(serial_mtk) = {
	267	.name = "serial_mtk",
	268	.id = UCLASS_SERIAL,
	269	.of_match = mtk_serial_ids,
d1998a9f	270	.of_to_plat = mtk_serial_of_to_plat,
41575d8e	271	.priv_auto = sizeof(struct mtk_serial_priv),
849b1160 RL	272	.probe = mtk_serial_probe,
	273	.ops = &mtk_serial_ops,
	274	.flags = DM_FLAG_PRE_RELOC,
	275	};
44fa676e WG	276	#else
	277
	278	DECLARE_GLOBAL_DATA_PTR;
	279
	280	#define DECLARE_HSUART_PRIV(port) \
	281	static struct mtk_serial_priv mtk_hsuart##port = { \
	282	.regs = (struct mtk_serial_regs *)CONFIG_SYS_NS16550_COM##port, \
	283	.clock = CONFIG_SYS_NS16550_CLK \
	284	};
	285
	286	#define DECLARE_HSUART_FUNCTIONS(port) \
	287	static int mtk_serial##port##_init(void) \
	288	{ \
	289	writel(0, &mtk_hsuart##port.regs->ier); \
	290	writel(UART_MCRVAL, &mtk_hsuart##port.regs->mcr); \
	291	writel(UART_FCRVAL, &mtk_hsuart##port.regs->fcr); \
	292	_mtk_serial_setbrg(&mtk_hsuart##port, gd->baudrate); \
	293	return 0 ; \
	294	} \
	295	static void mtk_serial##port##_setbrg(void) \
	296	{ \
	297	_mtk_serial_setbrg(&mtk_hsuart##port, gd->baudrate); \
	298	} \
	299	static int mtk_serial##port##_getc(void) \
	300	{ \
	301	int err; \
	302	do { \
	303	err = _mtk_serial_getc(&mtk_hsuart##port); \
	304	if (err == -EAGAIN) \
	305	WATCHDOG_RESET(); \
	306	} while (err == -EAGAIN); \
	307	return err >= 0 ? err : 0; \
	308	} \
	309	static int mtk_serial##port##_tstc(void) \
	310	{ \
	311	return _mtk_serial_pending(&mtk_hsuart##port, true); \
	312	} \
	313	static void mtk_serial##port##_putc(const char c) \
	314	{ \
	315	int err; \
	316	if (c == '\n') \
	317	mtk_serial##port##_putc('\r'); \
	318	do { \
	319	err = _mtk_serial_putc(&mtk_hsuart##port, c); \
	320	} while (err == -EAGAIN); \
	321	} \
	322	static void mtk_serial##port##_puts(const char *s) \
	323	{ \
	324	while (*s) { \
	325	mtk_serial##port##_putc(*s++); \
	326	} \
	327	}
	328
	329	/* Serial device descriptor */
	330	#define INIT_HSUART_STRUCTURE(port, __name) { \
	331	.name = __name, \
	332	.start = mtk_serial##port##_init, \
	333	.stop = NULL, \
	334	.setbrg = mtk_serial##port##_setbrg, \
	335	.getc = mtk_serial##port##_getc, \
	336	.tstc = mtk_serial##port##_tstc, \
	337	.putc = mtk_serial##port##_putc, \
	338	.puts = mtk_serial##port##_puts, \
	339	}
340
341	#define DECLARE_HSUART(port, __name) \
342	DECLARE_HSUART_PRIV(port); \
343	DECLARE_HSUART_FUNCTIONS(port); \
344	struct serial_device mtk_hsuart##port##_device = \
345	INIT_HSUART_STRUCTURE(port, __name);
346
347	#if !defined(CONFIG_CONS_INDEX)
348	#elif (CONFIG_CONS_INDEX < 1) \|\| (CONFIG_CONS_INDEX > 6)
349	#error "Invalid console index value."
350	#endif
351
352	#if CONFIG_CONS_INDEX == 1 && !defined(CONFIG_SYS_NS16550_COM1)
353	#error "Console port 1 defined but not configured."
354	#elif CONFIG_CONS_INDEX == 2 && !defined(CONFIG_SYS_NS16550_COM2)
355	#error "Console port 2 defined but not configured."
356	#elif CONFIG_CONS_INDEX == 3 && !defined(CONFIG_SYS_NS16550_COM3)
357	#error "Console port 3 defined but not configured."
358	#elif CONFIG_CONS_INDEX == 4 && !defined(CONFIG_SYS_NS16550_COM4)
359	#error "Console port 4 defined but not configured."
360	#elif CONFIG_CONS_INDEX == 5 && !defined(CONFIG_SYS_NS16550_COM5)
361	#error "Console port 5 defined but not configured."
362	#elif CONFIG_CONS_INDEX == 6 && !defined(CONFIG_SYS_NS16550_COM6)
363	#error "Console port 6 defined but not configured."
364	#endif
365
366	#if defined(CONFIG_SYS_NS16550_COM1)
367	DECLARE_HSUART(1, "mtk-hsuart0");
368	#endif
369	#if defined(CONFIG_SYS_NS16550_COM2)
370	DECLARE_HSUART(2, "mtk-hsuart1");
371	#endif
372	#if defined(CONFIG_SYS_NS16550_COM3)
373	DECLARE_HSUART(3, "mtk-hsuart2");
374	#endif
375	#if defined(CONFIG_SYS_NS16550_COM4)
376	DECLARE_HSUART(4, "mtk-hsuart3");
377	#endif
378	#if defined(CONFIG_SYS_NS16550_COM5)
379	DECLARE_HSUART(5, "mtk-hsuart4");
380	#endif
381	#if defined(CONFIG_SYS_NS16550_COM6)
382	DECLARE_HSUART(6, "mtk-hsuart5");
383	#endif
384
385	__weak struct serial_device *default_serial_console(void)
386	{
387	#if CONFIG_CONS_INDEX == 1
388	return &mtk_hsuart1_device;
389	#elif CONFIG_CONS_INDEX == 2
390	return &mtk_hsuart2_device;
391	#elif CONFIG_CONS_INDEX == 3
392	return &mtk_hsuart3_device;
393	#elif CONFIG_CONS_INDEX == 4
394	return &mtk_hsuart4_device;
395	#elif CONFIG_CONS_INDEX == 5
396	return &mtk_hsuart5_device;
397	#elif CONFIG_CONS_INDEX == 6
398	return &mtk_hsuart6_device;
399	#else
400	#error "Bad CONFIG_CONS_INDEX."
401	#endif
402	}
403
404	void mtk_serial_initialize(void)
405	{
406	#if defined(CONFIG_SYS_NS16550_COM1)
407	serial_register(&mtk_hsuart1_device);
408	#endif
409	#if defined(CONFIG_SYS_NS16550_COM2)
410	serial_register(&mtk_hsuart2_device);
411	#endif
412	#if defined(CONFIG_SYS_NS16550_COM3)
413	serial_register(&mtk_hsuart3_device);
414	#endif
415	#if defined(CONFIG_SYS_NS16550_COM4)
416	serial_register(&mtk_hsuart4_device);
417	#endif
418	#if defined(CONFIG_SYS_NS16550_COM5)
419	serial_register(&mtk_hsuart5_device);
420	#endif
421	#if defined(CONFIG_SYS_NS16550_COM6)
422	serial_register(&mtk_hsuart6_device);
423	#endif
424	}
425
426	#endif
849b1160 RL	427
	428	#ifdef CONFIG_DEBUG_UART_MTK
	429
	430	#include <debug_uart.h>
	431
	432	static inline void _debug_uart_init(void)
	433	{
	434	struct mtk_serial_priv priv;
	435
	436	priv.regs = (void *) CONFIG_DEBUG_UART_BASE;
	437	priv.clock = CONFIG_DEBUG_UART_CLOCK;
	438
	439	writel(0, &priv.regs->ier);
99ced533 WG	440	writel(UART_MCRVAL, &priv.regs->mcr);
99ced533 WG	441	writel(UART_FCRVAL, &priv.regs->fcr);
849b1160 RL	442
	443	_mtk_serial_setbrg(&priv, CONFIG_BAUDRATE);
	444	}
	445
	446	static inline void _debug_uart_putc(int ch)
	447	{
	448	struct mtk_serial_regs __iomem *regs =
	449	(void *) CONFIG_DEBUG_UART_BASE;
	450
	451	while (!(readl(&regs->lsr) & UART_LSR_THRE))
	452	;
	453
	454	writel(ch, &regs->thr);
	455	}
	456
	457	DEBUG_UART_FUNCS
	458
61b29b82	459	#endif