[J-u-boot.git] / nand_spl / nand_boot.c

/*
 * (C) Copyright 2006-2008
 * Stefan Roese, DENX Software Engineering, [email protected].
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <nand.h>
#include <asm/io.h>

static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;

#define ECCSTEPS	(CONFIG_SYS_NAND_PAGE_SIZE / \
					CONFIG_SYS_NAND_ECCSIZE)
#define ECCTOTAL	(ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES)


#if (CONFIG_SYS_NAND_PAGE_SIZE <= 512)
/*
 * NAND command for small page NAND devices (512)
 */
static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8 cmd)
{
	struct nand_chip *this = mtd->priv;
	int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;

	while (!this->dev_ready(mtd))
		;

	/* Begin command latch cycle */
	this->cmd_ctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
	/* Set ALE and clear CLE to start address cycle */
	/* Column address */
	this->cmd_ctrl(mtd, offs, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
	this->cmd_ctrl(mtd, page_addr & 0xff, NAND_CTRL_ALE); /* A[16:9] */
	this->cmd_ctrl(mtd, (page_addr >> 8) & 0xff,
		       NAND_CTRL_ALE); /* A[24:17] */
#ifdef CONFIG_SYS_NAND_4_ADDR_CYCLE
	/* One more address cycle for devices > 32MiB */
	this->cmd_ctrl(mtd, (page_addr >> 16) & 0x0f,
		       NAND_CTRL_ALE); /* A[28:25] */
#endif
	/* Latch in address */
	this->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);

	/*
	 * Wait a while for the data to be ready
	 */
	while (!this->dev_ready(mtd))
		;

	return 0;
}
#else
/*
 * NAND command for large page NAND devices (2k)
 */
static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8 cmd)
{
	struct nand_chip *this = mtd->priv;
	int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
	void (*hwctrl)(struct mtd_info *mtd, int cmd,
			unsigned int ctrl) = this->cmd_ctrl;

	while (!this->dev_ready(mtd))
		;

	/* Emulate NAND_CMD_READOOB */
	if (cmd == NAND_CMD_READOOB) {
		offs += CONFIG_SYS_NAND_PAGE_SIZE;
		cmd = NAND_CMD_READ0;
	}

	/* Shift the offset from byte addressing to word addressing. */
	if (this->options & NAND_BUSWIDTH_16)
		offs >>= 1;

	/* Begin command latch cycle */
	hwctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
	/* Set ALE and clear CLE to start address cycle */
	/* Column address */
	hwctrl(mtd, offs & 0xff,
		       NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
	hwctrl(mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
	/* Row address */
	hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */
	hwctrl(mtd, ((page_addr >> 8) & 0xff),
		       NAND_CTRL_ALE); /* A[27:20] */
#ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
	/* One more address cycle for devices > 128MiB */
	hwctrl(mtd, (page_addr >> 16) & 0x0f,
		       NAND_CTRL_ALE); /* A[31:28] */
#endif
	/* Latch in address */
	hwctrl(mtd, NAND_CMD_READSTART,
		       NAND_CTRL_CLE | NAND_CTRL_CHANGE);
	hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);

	/*
	 * Wait a while for the data to be ready
	 */
	while (!this->dev_ready(mtd))
		;

	return 0;
}
#endif

static int nand_is_bad_block(struct mtd_info *mtd, int block)
{
	struct nand_chip *this = mtd->priv;

	nand_command(mtd, block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB);

	/*
	 * Read one byte (or two if it's a 16 bit chip).
	 */
	if (this->options & NAND_BUSWIDTH_16) {
		if (readw(this->IO_ADDR_R) != 0xffff)
			return 1;
	} else {
		if (readb(this->IO_ADDR_R) != 0xff)
			return 1;
	}

	return 0;
}

#if defined(CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST)
static int nand_read_page(struct mtd_info *mtd, int block, int page, uchar *dst)
{
	struct nand_chip *this = mtd->priv;
	u_char ecc_calc[ECCTOTAL];
	u_char ecc_code[ECCTOTAL];
	u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
	int i;
	int eccsize = CONFIG_SYS_NAND_ECCSIZE;
	int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
	int eccsteps = ECCSTEPS;
	uint8_t *p = dst;

	nand_command(mtd, block, page, 0, NAND_CMD_READOOB);
	this->read_buf(mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
	nand_command(mtd, block, page, 0, NAND_CMD_READ0);

	/* Pick the ECC bytes out of the oob data */
	for (i = 0; i < ECCTOTAL; i++)
		ecc_code[i] = oob_data[nand_ecc_pos[i]];


	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
		this->ecc.hwctl(mtd, NAND_ECC_READ);
		this->read_buf(mtd, p, eccsize);
		this->ecc.calculate(mtd, p, &ecc_calc[i]);
		this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
	}

	return 0;
}
#else
static int nand_read_page(struct mtd_info *mtd, int block, int page, uchar *dst)
{
	struct nand_chip *this = mtd->priv;
	u_char ecc_calc[ECCTOTAL];
	u_char ecc_code[ECCTOTAL];
	u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
	int i;
	int eccsize = CONFIG_SYS_NAND_ECCSIZE;
	int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
	int eccsteps = ECCSTEPS;
	uint8_t *p = dst;

	nand_command(mtd, block, page, 0, NAND_CMD_READ0);

	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
		this->ecc.hwctl(mtd, NAND_ECC_READ);
		this->read_buf(mtd, p, eccsize);
		this->ecc.calculate(mtd, p, &ecc_calc[i]);
	}
	this->read_buf(mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);

	/* Pick the ECC bytes out of the oob data */
	for (i = 0; i < ECCTOTAL; i++)
		ecc_code[i] = oob_data[nand_ecc_pos[i]];

	eccsteps = ECCSTEPS;
	p = dst;

	for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
		/* No chance to do something with the possible error message
		 * from correct_data(). We just hope that all possible errors
		 * are corrected by this routine.
		 */
		this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
	}

	return 0;
}
#endif /* #if defined(CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST) */

static int nand_load(struct mtd_info *mtd, unsigned int offs,
		     unsigned int uboot_size, uchar *dst)
{
	unsigned int block, lastblock;
	unsigned int page;

	/*
	 * offs has to be aligned to a page address!
	 */
	block = offs / CONFIG_SYS_NAND_BLOCK_SIZE;
	lastblock = (offs + uboot_size - 1) / CONFIG_SYS_NAND_BLOCK_SIZE;
	page = (offs % CONFIG_SYS_NAND_BLOCK_SIZE) / CONFIG_SYS_NAND_PAGE_SIZE;

	while (block <= lastblock) {
		if (!nand_is_bad_block(mtd, block)) {
			/*
			 * Skip bad blocks
			 */
			while (page < CONFIG_SYS_NAND_PAGE_COUNT) {
				nand_read_page(mtd, block, page, dst);
				dst += CONFIG_SYS_NAND_PAGE_SIZE;
				page++;
			}

			page = 0;
		} else {
			lastblock++;
		}

		block++;
	}

	return 0;
}

/*
 * The main entry for NAND booting. It's necessary that SDRAM is already
 * configured and available since this code loads the main U-Boot image
 * from NAND into SDRAM and starts it from there.
 */
void nand_boot(void)
{
	struct nand_chip nand_chip;
	nand_info_t nand_info;
	__attribute__((noreturn)) void (*uboot)(void);

	/*
	 * Init board specific nand support
	 */
	nand_chip.select_chip = NULL;
	nand_info.priv = &nand_chip;
	nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W = (void  __iomem *)CONFIG_SYS_NAND_BASE;
	nand_chip.dev_ready = NULL;	/* preset to NULL */
	nand_chip.options = 0;
	board_nand_init(&nand_chip);

	if (nand_chip.select_chip)
		nand_chip.select_chip(&nand_info, 0);

	/*
	 * Load U-Boot image from NAND into RAM
	 */
	nand_load(&nand_info, CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE,
		  (uchar *)CONFIG_SYS_NAND_U_BOOT_DST);

#ifdef CONFIG_NAND_ENV_DST
	nand_load(&nand_info, CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
		  (uchar *)CONFIG_NAND_ENV_DST);

#ifdef CONFIG_ENV_OFFSET_REDUND
	nand_load(&nand_info, CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
		  (uchar *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
#endif
#endif

	if (nand_chip.select_chip)
		nand_chip.select_chip(&nand_info, -1);

	/*
	 * Jump to U-Boot image
	 */
	uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
	(*uboot)();
}
Commit	Line	Data
887e2ec9	1	/*
46f37383	2	* (C) Copyright 2006-2008
887e2ec9 SR	3	* Stefan Roese, DENX Software Engineering, [email protected].
	4	*
	5	* This program is free software; you can redistribute it and/or
	6	* modify it under the terms of the GNU General Public License as
	7	* published by the Free Software Foundation; either version 2 of
	8	* the License, or (at your option) any later version.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program; if not, write to the Free Software
	17	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	18	* MA 02111-1307 USA
	19	*/
	20
	21	#include <common.h>
	22	#include <nand.h>
c568f77a	23	#include <asm/io.h>
887e2ec9	24
6d0f6bcf	25	static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
42be56f5	26
25efd99d SW	27	#define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
	28	CONFIG_SYS_NAND_ECCSIZE)
	29	#define ECCTOTAL (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES)
	30
	31
6d0f6bcf	32	#if (CONFIG_SYS_NAND_PAGE_SIZE <= 512)
46f37383 SR	33	/*
	34	* NAND command for small page NAND devices (512)
	35	*/
42be56f5	36	static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8 cmd)
887e2ec9	37	{
511d0c72	38	struct nand_chip *this = mtd->priv;
6d0f6bcf	39	int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
42be56f5	40
e29816f3 SR	41	while (!this->dev_ready(mtd))
e29816f3 SR	42	;
887e2ec9 SR	43
887e2ec9 SR	44	/* Begin command latch cycle */
4f32d776	45	this->cmd_ctrl(mtd, cmd, NAND_CTRL_CLE \| NAND_CTRL_CHANGE);
887e2ec9	46	/* Set ALE and clear CLE to start address cycle */
887e2ec9	47	/* Column address */
4f32d776	48	this->cmd_ctrl(mtd, offs, NAND_CTRL_ALE \| NAND_CTRL_CHANGE);
1dac3a51 SW	49	this->cmd_ctrl(mtd, page_addr & 0xff, NAND_CTRL_ALE); /* A[16:9] */
	50	this->cmd_ctrl(mtd, (page_addr >> 8) & 0xff,
	51	NAND_CTRL_ALE); /* A[24:17] */
6d0f6bcf	52	#ifdef CONFIG_SYS_NAND_4_ADDR_CYCLE
887e2ec9	53	/* One more address cycle for devices > 32MiB */
1dac3a51 SW	54	this->cmd_ctrl(mtd, (page_addr >> 16) & 0x0f,
1dac3a51 SW	55	NAND_CTRL_ALE); /* A[28:25] */
887e2ec9 SR	56	#endif
887e2ec9 SR	57	/* Latch in address */
c568f77a	58	this->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE \| NAND_CTRL_CHANGE);
887e2ec9 SR	59
	60	/*
	61	* Wait a while for the data to be ready
	62	*/
a9c847cb SR	63	while (!this->dev_ready(mtd))
a9c847cb SR	64	;
887e2ec9	65
42be56f5 SR	66	return 0;
42be56f5 SR	67	}
46f37383 SR	68	#else
	69	/*
	70	* NAND command for large page NAND devices (2k)
	71	*/
	72	static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8 cmd)
	73	{
	74	struct nand_chip *this = mtd->priv;
6d0f6bcf	75	int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
83709783 AW	76	void (hwctrl)(struct mtd_info mtd, int cmd,
83709783 AW	77	unsigned int ctrl) = this->cmd_ctrl;
46f37383	78
a9c847cb SR	79	while (!this->dev_ready(mtd))
a9c847cb SR	80	;
46f37383 SR	81
	82	/* Emulate NAND_CMD_READOOB */
	83	if (cmd == NAND_CMD_READOOB) {
6d0f6bcf	84	offs += CONFIG_SYS_NAND_PAGE_SIZE;
46f37383 SR	85	cmd = NAND_CMD_READ0;
	86	}
	87
65a9db7b AW	88	/* Shift the offset from byte addressing to word addressing. */
	89	if (this->options & NAND_BUSWIDTH_16)
	90	offs >>= 1;
	91
46f37383	92	/* Begin command latch cycle */
83709783	93	hwctrl(mtd, cmd, NAND_CTRL_CLE \| NAND_CTRL_CHANGE);
46f37383	94	/* Set ALE and clear CLE to start address cycle */
46f37383	95	/* Column address */
83709783	96	hwctrl(mtd, offs & 0xff,
4b070809	97	NAND_CTRL_ALE \| NAND_CTRL_CHANGE); /* A[7:0] */
83709783	98	hwctrl(mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
46f37383	99	/* Row address */
83709783 AW	100	hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */
83709783 AW	101	hwctrl(mtd, ((page_addr >> 8) & 0xff),
1dac3a51	102	NAND_CTRL_ALE); /* A[27:20] */
6d0f6bcf	103	#ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
46f37383	104	/* One more address cycle for devices > 128MiB */
83709783	105	hwctrl(mtd, (page_addr >> 16) & 0x0f,
1dac3a51	106	NAND_CTRL_ALE); /* A[31:28] */
46f37383 SR	107	#endif
46f37383 SR	108	/* Latch in address */
83709783	109	hwctrl(mtd, NAND_CMD_READSTART,
4b070809	110	NAND_CTRL_CLE \| NAND_CTRL_CHANGE);
83709783	111	hwctrl(mtd, NAND_CMD_NONE, NAND_NCE \| NAND_CTRL_CHANGE);
46f37383 SR	112
	113	/*
	114	* Wait a while for the data to be ready
	115	*/
a9c847cb SR	116	while (!this->dev_ready(mtd))
a9c847cb SR	117	;
46f37383 SR	118
	119	return 0;
	120	}
	121	#endif
42be56f5 SR	122
	123	static int nand_is_bad_block(struct mtd_info *mtd, int block)
	124	{
	125	struct nand_chip *this = mtd->priv;
	126
6d0f6bcf	127	nand_command(mtd, block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB);
42be56f5	128
887e2ec9	129	/*
eced4626	130	* Read one byte (or two if it's a 16 bit chip).
887e2ec9	131	*/
eced4626 AW	132	if (this->options & NAND_BUSWIDTH_16) {
	133	if (readw(this->IO_ADDR_R) != 0xffff)
	134	return 1;
	135	} else {
	136	if (readb(this->IO_ADDR_R) != 0xff)
	137	return 1;
	138	}
887e2ec9 SR	139
	140	return 0;
	141	}
	142
dc7cd8e5 HS	143	#if defined(CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST)
	144	static int nand_read_page(struct mtd_info mtd, int block, int page, uchar dst)
	145	{
	146	struct nand_chip *this = mtd->priv;
25efd99d SW	147	u_char ecc_calc[ECCTOTAL];
	148	u_char ecc_code[ECCTOTAL];
	149	u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
dc7cd8e5 HS	150	int i;
	151	int eccsize = CONFIG_SYS_NAND_ECCSIZE;
	152	int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
25efd99d	153	int eccsteps = ECCSTEPS;
dc7cd8e5	154	uint8_t *p = dst;
dc7cd8e5	155
dc7cd8e5 HS	156	nand_command(mtd, block, page, 0, NAND_CMD_READOOB);
	157	this->read_buf(mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
	158	nand_command(mtd, block, page, 0, NAND_CMD_READ0);
	159
	160	/* Pick the ECC bytes out of the oob data */
25efd99d	161	for (i = 0; i < ECCTOTAL; i++)
dc7cd8e5 HS	162	ecc_code[i] = oob_data[nand_ecc_pos[i]];
	163
	164
	165	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
	166	this->ecc.hwctl(mtd, NAND_ECC_READ);
	167	this->read_buf(mtd, p, eccsize);
	168	this->ecc.calculate(mtd, p, &ecc_calc[i]);
40a0682d	169	this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
dc7cd8e5 HS	170	}
	171
	172	return 0;
	173	}
	174	#else
887e2ec9 SR	175	static int nand_read_page(struct mtd_info mtd, int block, int page, uchar dst)
887e2ec9 SR	176	{
511d0c72	177	struct nand_chip *this = mtd->priv;
25efd99d SW	178	u_char ecc_calc[ECCTOTAL];
	179	u_char ecc_code[ECCTOTAL];
	180	u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
887e2ec9	181	int i;
6d0f6bcf JCPV	182	int eccsize = CONFIG_SYS_NAND_ECCSIZE;
6d0f6bcf JCPV	183	int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
25efd99d	184	int eccsteps = ECCSTEPS;
42be56f5	185	uint8_t *p = dst;
887e2ec9	186
42be56f5	187	nand_command(mtd, block, page, 0, NAND_CMD_READ0);
887e2ec9	188
42be56f5	189	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
c568f77a	190	this->ecc.hwctl(mtd, NAND_ECC_READ);
42be56f5	191	this->read_buf(mtd, p, eccsize);
c568f77a	192	this->ecc.calculate(mtd, p, &ecc_calc[i]);
42be56f5	193	}
6d0f6bcf	194	this->read_buf(mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
42be56f5 SR	195
42be56f5 SR	196	/* Pick the ECC bytes out of the oob data */
25efd99d	197	for (i = 0; i < ECCTOTAL; i++)
42be56f5 SR	198	ecc_code[i] = oob_data[nand_ecc_pos[i]];
42be56f5 SR	199
25efd99d	200	eccsteps = ECCSTEPS;
42be56f5 SR	201	p = dst;
	202
	203	for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
	204	/* No chance to do something with the possible error message
	205	* from correct_data(). We just hope that all possible errors
	206	* are corrected by this routine.
	207	*/
6d68621c	208	this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
42be56f5	209	}
887e2ec9 SR	210
	211	return 0;
	212	}
dc7cd8e5	213	#endif /* #if defined(CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST) */
887e2ec9	214
aa646643	215	static int nand_load(struct mtd_info *mtd, unsigned int offs,
4b070809	216	unsigned int uboot_size, uchar *dst)
887e2ec9	217	{
aa646643 GL	218	unsigned int block, lastblock;
aa646643 GL	219	unsigned int page;
887e2ec9 SR	220
887e2ec9 SR	221	/*
aa646643	222	* offs has to be aligned to a page address!
887e2ec9	223	*/
6d0f6bcf JCPV	224	block = offs / CONFIG_SYS_NAND_BLOCK_SIZE;
	225	lastblock = (offs + uboot_size - 1) / CONFIG_SYS_NAND_BLOCK_SIZE;
	226	page = (offs % CONFIG_SYS_NAND_BLOCK_SIZE) / CONFIG_SYS_NAND_PAGE_SIZE;
887e2ec9	227
aa646643	228	while (block <= lastblock) {
887e2ec9 SR	229	if (!nand_is_bad_block(mtd, block)) {
	230	/*
	231	* Skip bad blocks
	232	*/
6d0f6bcf	233	while (page < CONFIG_SYS_NAND_PAGE_COUNT) {
887e2ec9	234	nand_read_page(mtd, block, page, dst);
6d0f6bcf	235	dst += CONFIG_SYS_NAND_PAGE_SIZE;
aa646643	236	page++;
887e2ec9 SR	237	}
887e2ec9 SR	238
aa646643 GL	239	page = 0;
	240	} else {
	241	lastblock++;
887e2ec9 SR	242	}
	243
	244	block++;
	245	}
	246
	247	return 0;
	248	}
	249
64852d09 SR	250	/*
	251	* The main entry for NAND booting. It's necessary that SDRAM is already
	252	* configured and available since this code loads the main U-Boot image
	253	* from NAND into SDRAM and starts it from there.
	254	*/
887e2ec9 SR	255	void nand_boot(void)
887e2ec9 SR	256	{
887e2ec9 SR	257	struct nand_chip nand_chip;
887e2ec9 SR	258	nand_info_t nand_info;
e4c09508	259	__attribute__((noreturn)) void (*uboot)(void);
887e2ec9	260
887e2ec9 SR	261	/*
	262	* Init board specific nand support
	263	*/
48571ff0	264	nand_chip.select_chip = NULL;
887e2ec9	265	nand_info.priv = &nand_chip;
6d0f6bcf	266	nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE;
887e2ec9	267	nand_chip.dev_ready = NULL; /* preset to NULL */
a89a9901	268	nand_chip.options = 0;
887e2ec9 SR	269	board_nand_init(&nand_chip);
887e2ec9 SR	270
aa646643 GL	271	if (nand_chip.select_chip)
	272	nand_chip.select_chip(&nand_info, 0);
	273
887e2ec9 SR	274	/*
	275	* Load U-Boot image from NAND into RAM
	276	*/
6d68621c SR	277	nand_load(&nand_info, CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE,
6d68621c SR	278	(uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
887e2ec9	279
b74ab737 GL	280	#ifdef CONFIG_NAND_ENV_DST
	281	nand_load(&nand_info, CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
	282	(uchar *)CONFIG_NAND_ENV_DST);
	283
	284	#ifdef CONFIG_ENV_OFFSET_REDUND
	285	nand_load(&nand_info, CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
	286	(uchar *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
	287	#endif
	288	#endif
	289
aa646643 GL	290	if (nand_chip.select_chip)
	291	nand_chip.select_chip(&nand_info, -1);
	292
887e2ec9 SR	293	/*
	294	* Jump to U-Boot image
	295	*/
6d0f6bcf	296	uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
887e2ec9 SR	297	(*uboot)();
887e2ec9 SR	298	}