[J-u-boot.git] / include / configs / socfpga_common.h

/*
 * Copyright (C) 2012 Altera Corporation <www.altera.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
#ifndef __CONFIG_SOCFPGA_COMMON_H__
#define __CONFIG_SOCFPGA_COMMON_H__

/* Virtual target or real hardware */
#undef CONFIG_SOCFPGA_VIRTUAL_TARGET

#define CONFIG_SYS_THUMB_BUILD

/*
 * High level configuration
 */
#define CONFIG_DISPLAY_BOARDINFO_LATE
#define CONFIG_ARCH_MISC_INIT
#define CONFIG_ARCH_EARLY_INIT_R
#define CONFIG_SYS_NO_FLASH
#define CONFIG_CLOCKS

#define CONFIG_CRC32_VERIFY

#define CONFIG_SYS_BOOTMAPSZ		(64 * 1024 * 1024)

#define CONFIG_TIMESTAMP		/* Print image info with timestamp */

/* add target to build it automatically upon "make" */
#define CONFIG_BUILD_TARGET		"u-boot-with-spl.sfp"

/*
 * Memory configurations
 */
#define CONFIG_NR_DRAM_BANKS		1
#define PHYS_SDRAM_1			0x0
#define CONFIG_SYS_MALLOC_LEN		(64 * 1024 * 1024)
#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_1
#define CONFIG_SYS_MEMTEST_END		PHYS_SDRAM_1_SIZE

#define CONFIG_SYS_INIT_RAM_ADDR	0xFFFF0000
#define CONFIG_SYS_INIT_RAM_SIZE	0x10000
#define CONFIG_SYS_INIT_SP_OFFSET		\
	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR			\
	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)

#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
#define CONFIG_SYS_TEXT_BASE		0x08000040
#else
#define CONFIG_SYS_TEXT_BASE		0x01000040
#endif

/*
 * U-Boot general configurations
 */
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_CBSIZE	1024		/* Console I/O buffer size */
#define CONFIG_SYS_PBSIZE	\
	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
						/* Print buffer size */
#define CONFIG_SYS_MAXARGS	32		/* Max number of command args */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
						/* Boot argument buffer size */
#define CONFIG_AUTO_COMPLETE			/* Command auto complete */
#define CONFIG_CMDLINE_EDITING			/* Command history etc */

#ifndef CONFIG_SYS_HOSTNAME
#define CONFIG_SYS_HOSTNAME	CONFIG_SYS_BOARD
#endif

/*
 * Cache
 */
#define CONFIG_SYS_L2_PL310
#define CONFIG_SYS_PL310_BASE		SOCFPGA_MPUL2_ADDRESS

/*
 * SDRAM controller
 */
#define CONFIG_ALTERA_SDRAM

/*
 * EPCS/EPCQx1 Serial Flash Controller
 */
#ifdef CONFIG_ALTERA_SPI
#define CONFIG_SF_DEFAULT_SPEED		30000000
/*
 * The base address is configurable in QSys, each board must specify the
 * base address based on it's particular FPGA configuration. Please note
 * that the address here is incremented by  0x400  from the Base address
 * selected in QSys, since the SPI registers are at offset +0x400.
 * #define CONFIG_SYS_SPI_BASE		0xff240400
 */
#endif

/*
 * Ethernet on SoC (EMAC)
 */
#if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
#define CONFIG_DW_ALTDESCRIPTOR
#define CONFIG_MII
#define CONFIG_AUTONEG_TIMEOUT		(15 * CONFIG_SYS_HZ)
#define CONFIG_PHY_GIGE
#endif

/*
 * FPGA Driver
 */
#ifdef CONFIG_CMD_FPGA
#define CONFIG_FPGA
#define CONFIG_FPGA_ALTERA
#define CONFIG_FPGA_SOCFPGA
#define CONFIG_FPGA_COUNT		1
#endif

/*
 * L4 OSC1 Timer 0
 */
/* This timer uses eosc1, whose clock frequency is fixed at any condition. */
#define CONFIG_SYS_TIMERBASE		SOCFPGA_OSC1TIMER0_ADDRESS
#define CONFIG_SYS_TIMER_COUNTS_DOWN
#define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMERBASE + 0x4)
#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
#define CONFIG_SYS_TIMER_RATE		2400000
#else
#define CONFIG_SYS_TIMER_RATE		25000000
#endif

/*
 * L4 Watchdog
 */
#ifdef CONFIG_HW_WATCHDOG
#define CONFIG_DESIGNWARE_WATCHDOG
#define CONFIG_DW_WDT_BASE		SOCFPGA_L4WD0_ADDRESS
#define CONFIG_DW_WDT_CLOCK_KHZ		25000
#define CONFIG_HW_WATCHDOG_TIMEOUT_MS	30000
#endif

/*
 * MMC Driver
 */
#ifdef CONFIG_CMD_MMC
#define CONFIG_MMC
#define CONFIG_BOUNCE_BUFFER
#define CONFIG_GENERIC_MMC
#define CONFIG_DWMMC
#define CONFIG_SOCFPGA_DWMMC
#define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH	1024
/* FIXME */
/* using smaller max blk cnt to avoid flooding the limited stack we have */
#define CONFIG_SYS_MMC_MAX_BLK_COUNT	256	/* FIXME -- SPL only? */
#endif

/*
 * NAND Support
 */
#ifdef CONFIG_NAND_DENALI
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_SYS_NAND_MAX_CHIPS	1
#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_NAND_DENALI_ECC_SIZE	512
#define CONFIG_SYS_NAND_REGS_BASE	SOCFPGA_NANDREGS_ADDRESS
#define CONFIG_SYS_NAND_DATA_BASE	SOCFPGA_NANDDATA_ADDRESS
#define CONFIG_SYS_NAND_BASE		(CONFIG_SYS_NAND_DATA_BASE + 0x10)
#endif

/*
 * I2C support
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_BUS_MAX		4
#define CONFIG_SYS_I2C_BASE		SOCFPGA_I2C0_ADDRESS
#define CONFIG_SYS_I2C_BASE1		SOCFPGA_I2C1_ADDRESS
#define CONFIG_SYS_I2C_BASE2		SOCFPGA_I2C2_ADDRESS
#define CONFIG_SYS_I2C_BASE3		SOCFPGA_I2C3_ADDRESS
/* Using standard mode which the speed up to 100Kb/s */
#define CONFIG_SYS_I2C_SPEED		100000
#define CONFIG_SYS_I2C_SPEED1		100000
#define CONFIG_SYS_I2C_SPEED2		100000
#define CONFIG_SYS_I2C_SPEED3		100000
/* Address of device when used as slave */
#define CONFIG_SYS_I2C_SLAVE		0x02
#define CONFIG_SYS_I2C_SLAVE1		0x02
#define CONFIG_SYS_I2C_SLAVE2		0x02
#define CONFIG_SYS_I2C_SLAVE3		0x02
#ifndef __ASSEMBLY__
/* Clock supplied to I2C controller in unit of MHz */
unsigned int cm_get_l4_sp_clk_hz(void);
#define IC_CLK				(cm_get_l4_sp_clk_hz() / 1000000)
#endif

/*
 * QSPI support
 */
/* Enable multiple SPI NOR flash manufacturers */
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SPI_FLASH_MTD
#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
#define MTDIDS_DEFAULT			"nor0=ff705000.spi.0"
#endif
/* QSPI reference clock */
#ifndef __ASSEMBLY__
unsigned int cm_get_qspi_controller_clk_hz(void);
#define CONFIG_CQSPI_REF_CLK		cm_get_qspi_controller_clk_hz()
#endif
#define CONFIG_CQSPI_DECODER		0

/*
 * Designware SPI support
 */

/*
 * Serial Driver
 */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	-4
#define CONFIG_SYS_NS16550_COM1		SOCFPGA_UART0_ADDRESS
#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
#define CONFIG_SYS_NS16550_CLK		1000000
#else
#define CONFIG_SYS_NS16550_CLK		100000000
#endif
#define CONFIG_CONS_INDEX		1
#define CONFIG_BAUDRATE			115200

/*
 * USB
 */
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_DWC2
#endif

/*
 * USB Gadget (DFU, UMS)
 */
#if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
#define CONFIG_USB_FUNCTION_MASS_STORAGE

#define CONFIG_SYS_DFU_DATA_BUF_SIZE	(32 * 1024 * 1024)
#define DFU_DEFAULT_POLL_TIMEOUT	300

/* USB IDs */
#define CONFIG_G_DNL_UMS_VENDOR_NUM	0x0525
#define CONFIG_G_DNL_UMS_PRODUCT_NUM	0xA4A5
#endif

/*
 * U-Boot environment
 */
#if !defined(CONFIG_ENV_SIZE)
#define CONFIG_ENV_SIZE			4096
#endif

/* Environment for SDMMC boot */
#if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET)
#define CONFIG_SYS_MMC_ENV_DEV		0	/* device 0 */
#define CONFIG_ENV_OFFSET		512	/* just after the MBR */
#endif

/* Environment for QSPI boot */
#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET)
#define CONFIG_ENV_OFFSET		0x00100000
#define CONFIG_ENV_SECT_SIZE		(64 * 1024)
#endif

/*
 * mtd partitioning for serial NOR flash
 *
 * device nor0 <ff705000.spi.0>, # parts = 6
 * #: name                size            offset          mask_flags
 * 0: u-boot              0x00100000      0x00000000      0
 * 1: env1                0x00040000      0x00100000      0
 * 2: env2                0x00040000      0x00140000      0
 * 3: UBI                 0x03e80000      0x00180000      0
 * 4: boot                0x00e80000      0x00180000      0
 * 5: rootfs              0x01000000      0x01000000      0
 *
 */
#if defined(CONFIG_CMD_SF) && !defined(MTDPARTS_DEFAULT)
#define MTDPARTS_DEFAULT	"mtdparts=ff705000.spi.0:"\
				"1m(u-boot),"		\
				"256k(env1),"		\
				"256k(env2),"		\
				"14848k(boot),"		\
				"16m(rootfs),"		\
				"-@1536k(UBI)\0"
#endif

/* UBI and UBIFS support */
#if defined(CONFIG_CMD_SF) || defined(CONFIG_CMD_NAND)
#define CONFIG_CMD_UBIFS
#define CONFIG_RBTREE
#define CONFIG_LZO
#endif

/*
 * SPL
 *
 * SRAM Memory layout:
 *
 * 0xFFFF_0000 ...... Start of SRAM
 * 0xFFFF_xxxx ...... Top of stack (grows down)
 * 0xFFFF_yyyy ...... Malloc area
 * 0xFFFF_zzzz ...... Global Data
 * 0xFFFF_FF00 ...... End of SRAM
 */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_RAM_DEVICE
#define CONFIG_SPL_TEXT_BASE		CONFIG_SYS_INIT_RAM_ADDR
#define CONFIG_SPL_MAX_SIZE		(64 * 1024)

/* SPL SDMMC boot support */
#ifdef CONFIG_SPL_MMC_SUPPORT
#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	2
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME		"u-boot-dtb.img"
#else
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION	1
#endif
#endif

/* SPL QSPI boot support */
#ifdef CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x40000
#endif

/* SPL NAND boot support */
#ifdef CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x40000
#endif

/*
 * Stack setup
 */
#define CONFIG_SPL_STACK		CONFIG_SYS_INIT_SP_ADDR

#endif	/* __CONFIG_SOCFPGA_COMMON_H__ */
Commit	Line	Data
5095ee08 PM	1	/*
	2	* Copyright (C) 2012 Altera Corporation <www.altera.com>
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
48275c96 DN	6	#ifndef __CONFIG_SOCFPGA_COMMON_H__
48275c96 DN	7	#define __CONFIG_SOCFPGA_COMMON_H__
5095ee08	8
5095ee08 PM	9	/* Virtual target or real hardware */
	10	#undef CONFIG_SOCFPGA_VIRTUAL_TARGET
	11
5095ee08 PM	12	#define CONFIG_SYS_THUMB_BUILD
5095ee08 PM	13
5095ee08 PM	14	/*
	15	* High level configuration
	16	*/
7287d5f0	17	#define CONFIG_DISPLAY_BOARDINFO_LATE
9ec7414e	18	#define CONFIG_ARCH_MISC_INIT
fc520894	19	#define CONFIG_ARCH_EARLY_INIT_R
5095ee08 PM	20	#define CONFIG_SYS_NO_FLASH
	21	#define CONFIG_CLOCKS
	22
251faa20 MV	23	#define CONFIG_CRC32_VERIFY
251faa20 MV	24
5095ee08 PM	25	#define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024)
	26
	27	#define CONFIG_TIMESTAMP /* Print image info with timestamp */
	28
dc0a1a08 MV	29	/* add target to build it automatically upon "make" */
	30	#define CONFIG_BUILD_TARGET "u-boot-with-spl.sfp"
	31
5095ee08 PM	32	/*
	33	* Memory configurations
	34	*/
	35	#define CONFIG_NR_DRAM_BANKS 1
	36	#define PHYS_SDRAM_1 0x0
0223a95c	37	#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024)
5095ee08 PM	38	#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
	39	#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE
	40
	41	#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
7599b53d MV	42	#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
	43	#define CONFIG_SYS_INIT_SP_OFFSET \
	44	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
	45	#define CONFIG_SYS_INIT_SP_ADDR \
	46	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
5095ee08 PM	47
	48	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
	49	#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
	50	#define CONFIG_SYS_TEXT_BASE 0x08000040
	51	#else
	52	#define CONFIG_SYS_TEXT_BASE 0x01000040
	53	#endif
	54
	55	/*
	56	* U-Boot general configurations
	57	*/
	58	#define CONFIG_SYS_LONGHELP
	59	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
	60	#define CONFIG_SYS_PBSIZE \
	61	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
	62	/* Print buffer size */
	63	#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
	64	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	65	/* Boot argument buffer size */
5095ee08 PM	66	#define CONFIG_AUTO_COMPLETE /* Command auto complete */
5095ee08 PM	67	#define CONFIG_CMDLINE_EDITING /* Command history etc */
5095ee08	68
ea082346 MV	69	#ifndef CONFIG_SYS_HOSTNAME
	70	#define CONFIG_SYS_HOSTNAME CONFIG_SYS_BOARD
	71	#endif
	72
5095ee08 PM	73	/*
	74	* Cache
	75	*/
5095ee08 PM	76	#define CONFIG_SYS_L2_PL310
	77	#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
	78
cdd4e6cc DN	79	/*
	80	* SDRAM controller
	81	*/
	82	#define CONFIG_ALTERA_SDRAM
	83
8a78ca9e MV	84	/*
	85	* EPCS/EPCQx1 Serial Flash Controller
	86	*/
	87	#ifdef CONFIG_ALTERA_SPI
8a78ca9e	88	#define CONFIG_SF_DEFAULT_SPEED 30000000
8a78ca9e MV	89	/*
	90	* The base address is configurable in QSys, each board must specify the
	91	* base address based on it's particular FPGA configuration. Please note
	92	* that the address here is incremented by 0x400 from the Base address
	93	* selected in QSys, since the SPI registers are at offset +0x400.
	94	* #define CONFIG_SYS_SPI_BASE 0xff240400
	95	*/
	96	#endif
	97
5095ee08 PM	98	/*
	99	* Ethernet on SoC (EMAC)
	100	*/
	101	#if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
5095ee08 PM	102	#define CONFIG_DW_ALTDESCRIPTOR
	103	#define CONFIG_MII
	104	#define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ)
5095ee08 PM	105	#define CONFIG_PHY_GIGE
	106	#endif
	107
	108	/*
	109	* FPGA Driver
	110	*/
	111	#ifdef CONFIG_CMD_FPGA
	112	#define CONFIG_FPGA
	113	#define CONFIG_FPGA_ALTERA
	114	#define CONFIG_FPGA_SOCFPGA
	115	#define CONFIG_FPGA_COUNT 1
	116	#endif
	117
	118	/*
	119	* L4 OSC1 Timer 0
	120	*/
	121	/* This timer uses eosc1, whose clock frequency is fixed at any condition. */
	122	#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
	123	#define CONFIG_SYS_TIMER_COUNTS_DOWN
	124	#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
	125	#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
	126	#define CONFIG_SYS_TIMER_RATE 2400000
	127	#else
	128	#define CONFIG_SYS_TIMER_RATE 25000000
	129	#endif
	130
	131	/*
	132	* L4 Watchdog
	133	*/
	134	#ifdef CONFIG_HW_WATCHDOG
	135	#define CONFIG_DESIGNWARE_WATCHDOG
	136	#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
	137	#define CONFIG_DW_WDT_CLOCK_KHZ 25000
d0e932de	138	#define CONFIG_HW_WATCHDOG_TIMEOUT_MS 30000
5095ee08 PM	139	#endif
	140
	141	/*
	142	* MMC Driver
	143	*/
	144	#ifdef CONFIG_CMD_MMC
	145	#define CONFIG_MMC
	146	#define CONFIG_BOUNCE_BUFFER
	147	#define CONFIG_GENERIC_MMC
	148	#define CONFIG_DWMMC
	149	#define CONFIG_SOCFPGA_DWMMC
	150	#define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024
5095ee08 PM	151	/* FIXME */
	152	/* using smaller max blk cnt to avoid flooding the limited stack we have */
	153	#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */
	154	#endif
	155
c339ea5b MV	156	/*
	157	* NAND Support
	158	*/
	159	#ifdef CONFIG_NAND_DENALI
	160	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	161	#define CONFIG_SYS_NAND_MAX_CHIPS 1
	162	#define CONFIG_SYS_NAND_ONFI_DETECTION
	163	#define CONFIG_NAND_DENALI_ECC_SIZE 512
	164	#define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS
	165	#define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS
	166	#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10)
	167	#endif
	168
7fb0f596	169	/*
ebcaf966 SR	170	* I2C support
	171	*/
	172	#define CONFIG_SYS_I2C
ebcaf966 SR	173	#define CONFIG_SYS_I2C_BUS_MAX 4
	174	#define CONFIG_SYS_I2C_BASE SOCFPGA_I2C0_ADDRESS
	175	#define CONFIG_SYS_I2C_BASE1 SOCFPGA_I2C1_ADDRESS
	176	#define CONFIG_SYS_I2C_BASE2 SOCFPGA_I2C2_ADDRESS
	177	#define CONFIG_SYS_I2C_BASE3 SOCFPGA_I2C3_ADDRESS
	178	/* Using standard mode which the speed up to 100Kb/s */
	179	#define CONFIG_SYS_I2C_SPEED 100000
	180	#define CONFIG_SYS_I2C_SPEED1 100000
	181	#define CONFIG_SYS_I2C_SPEED2 100000
	182	#define CONFIG_SYS_I2C_SPEED3 100000
	183	/* Address of device when used as slave */
	184	#define CONFIG_SYS_I2C_SLAVE 0x02
	185	#define CONFIG_SYS_I2C_SLAVE1 0x02
	186	#define CONFIG_SYS_I2C_SLAVE2 0x02
	187	#define CONFIG_SYS_I2C_SLAVE3 0x02
	188	#ifndef __ASSEMBLY__
	189	/* Clock supplied to I2C controller in unit of MHz */
	190	unsigned int cm_get_l4_sp_clk_hz(void);
	191	#define IC_CLK (cm_get_l4_sp_clk_hz() / 1000000)
	192	#endif
ebcaf966	193
7fb0f596 SR	194	/*
	195	* QSPI support
	196	*/
7fb0f596	197	/* Enable multiple SPI NOR flash manufacturers */
cbc9544d	198	#ifndef CONFIG_SPL_BUILD
7fb0f596	199	#define CONFIG_SPI_FLASH_MTD
55b4312b MV	200	#define CONFIG_CMD_MTDPARTS
	201	#define CONFIG_MTD_DEVICE
	202	#define CONFIG_MTD_PARTITIONS
55702fe2	203	#define MTDIDS_DEFAULT "nor0=ff705000.spi.0"
cbc9544d	204	#endif
7fb0f596 SR	205	/* QSPI reference clock */
	206	#ifndef __ASSEMBLY__
	207	unsigned int cm_get_qspi_controller_clk_hz(void);
	208	#define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz()
	209	#endif
	210	#define CONFIG_CQSPI_DECODER 0
7fb0f596	211
0c745d00 MV	212	/*
	213	* Designware SPI support
	214	*/
a6e73591	215
5095ee08 PM	216	/*
	217	* Serial Driver
	218	*/
5095ee08 PM	219	#define CONFIG_SYS_NS16550_SERIAL
	220	#define CONFIG_SYS_NS16550_REG_SIZE -4
	221	#define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS
	222	#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
	223	#define CONFIG_SYS_NS16550_CLK 1000000
	224	#else
	225	#define CONFIG_SYS_NS16550_CLK 100000000
	226	#endif
	227	#define CONFIG_CONS_INDEX 1
	228	#define CONFIG_BAUDRATE 115200
	229
20cadbbe MV	230	/*
	231	* USB
	232	*/
	233	#ifdef CONFIG_CMD_USB
	234	#define CONFIG_USB_DWC2
20cadbbe MV	235	#endif
20cadbbe MV	236
0223a95c MV	237	/*
	238	* USB Gadget (DFU, UMS)
	239	*/
	240	#if defined(CONFIG_CMD_DFU) \|\| defined(CONFIG_CMD_USB_MASS_STORAGE)
01acd6ab	241	#define CONFIG_USB_FUNCTION_MASS_STORAGE
0223a95c	242
0223a95c MV	243	#define CONFIG_SYS_DFU_DATA_BUF_SIZE (32 * 1024 * 1024)
	244	#define DFU_DEFAULT_POLL_TIMEOUT 300
	245
	246	/* USB IDs */
e6c0bc06 SP	247	#define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525
e6c0bc06 SP	248	#define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5
0223a95c MV	249	#endif
0223a95c MV	250
5095ee08 PM	251	/*
	252	* U-Boot environment
	253	*/
ead2fb29	254	#if !defined(CONFIG_ENV_SIZE)
5095ee08	255	#define CONFIG_ENV_SIZE 4096
ead2fb29	256	#endif
5095ee08	257
79cc48e7 CLS	258	/* Environment for SDMMC boot */
	259	#if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET)
	260	#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */
	261	#define CONFIG_ENV_OFFSET 512 /* just after the MBR */
	262	#endif
	263
ec8b7528 CLS	264	/* Environment for QSPI boot */
	265	#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET)
	266	#define CONFIG_ENV_OFFSET 0x00100000
	267	#define CONFIG_ENV_SECT_SIZE (64 * 1024)
	268	#endif
	269
55702fe2 CLS	270	/*
	271	* mtd partitioning for serial NOR flash
	272	*
	273	* device nor0 <ff705000.spi.0>, # parts = 6
	274	* #: name size offset mask_flags
	275	* 0: u-boot 0x00100000 0x00000000 0
	276	* 1: env1 0x00040000 0x00100000 0
	277	* 2: env2 0x00040000 0x00140000 0
	278	* 3: UBI 0x03e80000 0x00180000 0
	279	* 4: boot 0x00e80000 0x00180000 0
	280	* 5: rootfs 0x01000000 0x01000000 0
	281	*
	282	*/
	283	#if defined(CONFIG_CMD_SF) && !defined(MTDPARTS_DEFAULT)
	284	#define MTDPARTS_DEFAULT "mtdparts=ff705000.spi.0:"\
	285	"1m(u-boot)," \
	286	"256k(env1)," \
	287	"256k(env2)," \
	288	"14848k(boot)," \
	289	"16m(rootfs)," \
	290	"-@1536k(UBI)\0"
	291	#endif
	292
6cdd465c CLS	293	/* UBI and UBIFS support */
6cdd465c CLS	294	#if defined(CONFIG_CMD_SF) \|\| defined(CONFIG_CMD_NAND)
6cdd465c CLS	295	#define CONFIG_CMD_UBIFS
	296	#define CONFIG_RBTREE
	297	#define CONFIG_LZO
	298	#endif
	299
5095ee08 PM	300	/*
5095ee08 PM	301	* SPL
34584d19 MV	302	*
	303	* SRAM Memory layout:
	304	*
	305	* 0xFFFF_0000 ...... Start of SRAM
	306	* 0xFFFF_xxxx ...... Top of stack (grows down)
	307	* 0xFFFF_yyyy ...... Malloc area
	308	* 0xFFFF_zzzz ...... Global Data
	309	* 0xFFFF_FF00 ...... End of SRAM
5095ee08 PM	310	*/
5095ee08 PM	311	#define CONFIG_SPL_FRAMEWORK
5095ee08	312	#define CONFIG_SPL_RAM_DEVICE
34584d19	313	#define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR
6868160a	314	#define CONFIG_SPL_MAX_SIZE (64 * 1024)
5095ee08	315
d3f34e75 MV	316	/* SPL SDMMC boot support */
	317	#ifdef CONFIG_SPL_MMC_SUPPORT
	318	#if defined(CONFIG_SPL_FAT_SUPPORT) \|\| defined(CONFIG_SPL_EXT_SUPPORT)
	319	#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 2
	320	#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img"
d3f34e75	321	#else
61520ac4	322	#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1
d3f34e75 MV	323	#endif
d3f34e75 MV	324	#endif
5095ee08	325
346d6f56 MV	326	/* SPL QSPI boot support */
346d6f56 MV	327	#ifdef CONFIG_SPL_SPI_SUPPORT
346d6f56 MV	328	#define CONFIG_SPL_SPI_LOAD
	329	#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000
	330	#endif
	331
c339ea5b MV	332	/* SPL NAND boot support */
	333	#ifdef CONFIG_SPL_NAND_SUPPORT
	334	#define CONFIG_SYS_NAND_USE_FLASH_BBT
	335	#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
	336	#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
	337	#endif
	338
a717b811 DN	339	/*
	340	* Stack setup
	341	*/
	342	#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
	343
48275c96	344	#endif /* __CONFIG_SOCFPGA_COMMON_H__ */