[J-u-boot.git] / board / freescale / mpc8548cds / mpc8548cds.c

/*
 * Copyright 2004, 2007, 2009-2010 Freescale Semiconductor, Inc.
 *
 * (C) Copyright 2002 Scott McNutt <[email protected]>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <spd_sdram.h>
#include <miiphy.h>
#include <libfdt.h>
#include <fdt_support.h>

#include "../common/cadmus.h"
#include "../common/eeprom.h"
#include "../common/via.h"

DECLARE_GLOBAL_DATA_PTR;

void local_bus_init(void);

int checkboard (void)
{
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);

	/* PCI slot in USER bits CSR[6:7] by convention. */
	uint pci_slot = get_pci_slot ();

	uint cpu_board_rev = get_cpu_board_revision ();

	printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
		get_board_version (), pci_slot);

	printf ("CPU Board Revision %d.%d (0x%04x)\n",
		MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
		MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
	/*
	 * Initialize local bus.
	 */
	local_bus_init ();

	/*
	 * Hack TSEC 3 and 4 IO voltages.
	 */
	gur->tsec34ioovcr = 0xe7e0;	/*  1110 0111 1110 0xxx */

	ecm->eedr = 0xffffffff;		/* clear ecm errors */
	ecm->eeer = 0xffffffff;		/* enable ecm errors */
	return 0;
}

/*
 * Initialize Local Bus
 */
void
local_bus_init(void)
{
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;

	uint clkdiv;
	uint lbc_hz;
	sys_info_t sysinfo;

	get_sys_info(&sysinfo);
	clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;

	gur->lbiuiplldcr1 = 0x00078080;
	if (clkdiv == 16) {
		gur->lbiuiplldcr0 = 0x7c0f1bf0;
	} else if (clkdiv == 8) {
		gur->lbiuiplldcr0 = 0x6c0f1bf0;
	} else if (clkdiv == 4) {
		gur->lbiuiplldcr0 = 0x5c0f1bf0;
	}

	lbc->lcrr |= 0x00030000;

	asm("sync;isync;msync");

	lbc->ltesr = 0xffffffff;	/* Clear LBC error interrupts */
	lbc->lteir = 0xffffffff;	/* Enable LBC error interrupts */
}

/*
 * Initialize SDRAM memory on the Local Bus.
 */
void
sdram_init(void)
{
#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)

	uint idx;
	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
	uint cpu_board_rev;
	uint lsdmr_common;

	puts("    SDRAM: ");

	print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");

	/*
	 * Setup SDRAM Base and Option Registers
	 */
	set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
	set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
	asm("msync");

	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
	asm("msync");

	/*
	 * MPC8548 uses "new" 15-16 style addressing.
	 */
	cpu_board_rev = get_cpu_board_revision();
	lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
	lsdmr_common |= LSDMR_BSMA1516;

	/*
	 * Issue PRECHARGE ALL command.
	 */
	lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
	asm("sync;msync");
	*sdram_addr = 0xff;
	ppcDcbf((unsigned long) sdram_addr);
	udelay(100);

	/*
	 * Issue 8 AUTO REFRESH commands.
	 */
	for (idx = 0; idx < 8; idx++) {
		lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
		asm("sync;msync");
		*sdram_addr = 0xff;
		ppcDcbf((unsigned long) sdram_addr);
		udelay(100);
	}

	/*
	 * Issue 8 MODE-set command.
	 */
	lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
	asm("sync;msync");
	*sdram_addr = 0xff;
	ppcDcbf((unsigned long) sdram_addr);
	udelay(100);

	/*
	 * Issue NORMAL OP command.
	 */
	lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
	asm("sync;msync");
	*sdram_addr = 0xff;
	ppcDcbf((unsigned long) sdram_addr);
	udelay(200);    /* Overkill. Must wait > 200 bus cycles */

#endif	/* enable SDRAM init */
}

#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
/* For some reason the Tundra PCI bridge shows up on itself as a
 * different device.  Work around that by refusing to configure it.
 */
void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }

static struct pci_config_table pci_mpc85xxcds_config_table[] = {
	{0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
	{0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
	{0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
		mpc85xx_config_via_usbide, {0,0,0}},
	{0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
		mpc85xx_config_via_usb, {0,0,0}},
	{0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
		mpc85xx_config_via_usb2, {0,0,0}},
	{0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
		mpc85xx_config_via_power, {0,0,0}},
	{0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
		mpc85xx_config_via_ac97, {0,0,0}},
	{},
};

static struct pci_controller pci1_hose = {
	config_table: pci_mpc85xxcds_config_table};
#endif	/* CONFIG_PCI */

#ifdef CONFIG_PCI2
static struct pci_controller pci2_hose;
#endif	/* CONFIG_PCI2 */

#ifdef CONFIG_PCIE1
static struct pci_controller pcie1_hose;
#endif	/* CONFIG_PCIE1 */

void pci_init_board(void)
{
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	struct fsl_pci_info pci_info[4];
	u32 devdisr, pordevsr, io_sel;
	u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
	int first_free_busno = 0;
	int num = 0;

	int pcie_ep, pcie_configured;

	devdisr = in_be32(&gur->devdisr);
	pordevsr = in_be32(&gur->pordevsr);
	porpllsr = in_be32(&gur->porpllsr);
	io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;

	debug ("   pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);

#ifdef CONFIG_PCI1
	pci_speed = get_clock_freq ();	/* PCI PSPEED in [4:5] */
	pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;	/* PORDEVSR[15] */
	pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
	pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;

	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
		SET_STD_PCI_INFO(pci_info[num], 1);
		pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
		printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
			(pci_32) ? 32 : 64,
			(pci_speed == 33333000) ? "33" :
			(pci_speed == 66666000) ? "66" : "unknown",
			pci_clk_sel ? "sync" : "async",
			pci_agent ? "agent" : "host",
			pci_arb ? "arbiter" : "external-arbiter",
			pci_info[num].regs);

		first_free_busno = fsl_pci_init_port(&pci_info[num++],
					&pci1_hose, first_free_busno);

#ifdef CONFIG_PCIX_CHECK
		if (!(pordevsr & MPC85xx_PORDEVSR_PCI1)) {
			/* PCI-X init */
			if (CONFIG_SYS_CLK_FREQ < 66000000)
				printf("PCI-X will only work at 66 MHz\n");

			reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
				| PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
			pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16);
		}
#endif
	} else {
		printf("PCI: disabled\n");
	}

	puts("\n");
#else
	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
#endif

#ifdef CONFIG_PCI2
{
	uint pci2_clk_sel = porpllsr & 0x4000;	/* PORPLLSR[17] */
	uint pci_dual = get_pci_dual ();	/* PCI DUAL in CM_PCI[3] */
	if (pci_dual) {
		printf("PCI2: 32 bit, 66 MHz, %s\n",
			pci2_clk_sel ? "sync" : "async");
	} else {
		printf("PCI2: disabled\n");
	}
}
#else
	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable */
#endif /* CONFIG_PCI2 */

#ifdef CONFIG_PCIE1
	pcie_configured = is_serdes_configured(PCIE1);

	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
		SET_STD_PCIE_INFO(pci_info[num], 1);
		pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
		printf("PCIE1: connected to Slot as %s (base addr %lx)\n",
			pcie_ep ? "Endpoint" : "Root Complex",
			pci_info[num].regs);

		first_free_busno = fsl_pci_init_port(&pci_info[num++],
					&pcie1_hose, first_free_busno);
	} else {
		printf("PCIE1: disabled\n");
	}

	puts("\n");
#else
	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
#endif
}

int last_stage_init(void)
{
	unsigned short temp;

	/* Change the resistors for the PHY */
	/* This is needed to get the RGMII working for the 1.3+
	 * CDS cards */
	if (get_board_version() ==  0x13) {
		miiphy_write(CONFIG_TSEC1_NAME,
				TSEC1_PHY_ADDR, 29, 18);

		miiphy_read(CONFIG_TSEC1_NAME,
				TSEC1_PHY_ADDR, 30, &temp);

		temp = (temp & 0xf03f);
		temp |= 2 << 9;		/* 36 ohm */
		temp |= 2 << 6;		/* 39 ohm */

		miiphy_write(CONFIG_TSEC1_NAME,
				TSEC1_PHY_ADDR, 30, temp);

		miiphy_write(CONFIG_TSEC1_NAME,
				TSEC1_PHY_ADDR, 29, 3);

		miiphy_write(CONFIG_TSEC1_NAME,
				TSEC1_PHY_ADDR, 30, 0x8000);
	}

	return 0;
}


#if defined(CONFIG_OF_BOARD_SETUP)
void ft_pci_setup(void *blob, bd_t *bd)
{
	FT_FSL_PCI_SETUP;
}
#endif
Commit	Line	Data
d9b94f28	1	/*
6525d51f	2	* Copyright 2004, 2007, 2009-2010 Freescale Semiconductor, Inc.
d9b94f28 JL	3	*
	4	* (C) Copyright 2002 Scott McNutt <[email protected]>
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	#include <common.h>
	26	#include <pci.h>
	27	#include <asm/processor.h>
e31d2c1e	28	#include <asm/mmu.h>
d9b94f28	29	#include <asm/immap_85xx.h>
c8514622	30	#include <asm/fsl_pci.h>
e31d2c1e	31	#include <asm/fsl_ddr_sdram.h>
5d27e02c	32	#include <asm/fsl_serdes.h>
a30a549a	33	#include <spd_sdram.h>
09f3e09e	34	#include <miiphy.h>
b90d2549 KG	35	#include <libfdt.h>
b90d2549 KG	36	#include <fdt_support.h>
d9b94f28 JL	37
	38	#include "../common/cadmus.h"
	39	#include "../common/eeprom.h"
bf1dfffd	40	#include "../common/via.h"
d9b94f28	41
f2cff6b1 ES	42	DECLARE_GLOBAL_DATA_PTR;
f2cff6b1 ES	43
d9b94f28	44	void local_bus_init(void);
d9b94f28	45
d9b94f28 JL	46	int checkboard (void)
d9b94f28 JL	47	{
6d0f6bcf JCPV	48	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
6d0f6bcf JCPV	49	volatile ccsr_local_ecm_t ecm = (void )(CONFIG_SYS_MPC85xx_ECM_ADDR);
d9b94f28 JL	50
	51	/* PCI slot in USER bits CSR[6:7] by convention. */
	52	uint pci_slot = get_pci_slot ();
	53
d9b94f28 JL	54	uint cpu_board_rev = get_cpu_board_revision ();
	55
	56	printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
	57	get_board_version (), pci_slot);
	58
	59	printf ("CPU Board Revision %d.%d (0x%04x)\n",
	60	MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
	61	MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
d9b94f28 JL	62	/*
	63	* Initialize local bus.
	64	*/
	65	local_bus_init ();
	66
d9b94f28 JL	67	/*
	68	* Hack TSEC 3 and 4 IO voltages.
	69	*/
	70	gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */
	71
f2cff6b1 ES	72	ecm->eedr = 0xffffffff; /* clear ecm errors */
f2cff6b1 ES	73	ecm->eeer = 0xffffffff; /* enable ecm errors */
d9b94f28 JL	74	return 0;
	75	}
	76
d9b94f28 JL	77	/*
	78	* Initialize Local Bus
	79	*/
	80	void
	81	local_bus_init(void)
	82	{
6d0f6bcf	83	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
f51cdaf1	84	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
d9b94f28 JL	85
	86	uint clkdiv;
	87	uint lbc_hz;
	88	sys_info_t sysinfo;
	89
	90	get_sys_info(&sysinfo);
a5d212a2	91	clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
d9b94f28 JL	92	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
	93
	94	gur->lbiuiplldcr1 = 0x00078080;
	95	if (clkdiv == 16) {
	96	gur->lbiuiplldcr0 = 0x7c0f1bf0;
	97	} else if (clkdiv == 8) {
	98	gur->lbiuiplldcr0 = 0x6c0f1bf0;
	99	} else if (clkdiv == 4) {
	100	gur->lbiuiplldcr0 = 0x5c0f1bf0;
	101	}
	102
	103	lbc->lcrr \|= 0x00030000;
	104
	105	asm("sync;isync;msync");
f2cff6b1 ES	106
	107	lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
	108	lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
d9b94f28 JL	109	}
	110
	111	/*
	112	* Initialize SDRAM memory on the Local Bus.
	113	*/
	114	void
	115	sdram_init(void)
	116	{
6d0f6bcf	117	#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
d9b94f28 JL	118
d9b94f28 JL	119	uint idx;
f51cdaf1	120	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
6d0f6bcf	121	uint sdram_addr = (uint )CONFIG_SYS_LBC_SDRAM_BASE;
d9b94f28 JL	122	uint cpu_board_rev;
	123	uint lsdmr_common;
	124
	125	puts(" SDRAM: ");
	126
6d0f6bcf	127	print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
d9b94f28 JL	128
	129	/*
	130	* Setup SDRAM Base and Option Registers
	131	*/
f51cdaf1 BB	132	set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
f51cdaf1 BB	133	set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
6d0f6bcf	134	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
d9b94f28 JL	135	asm("msync");
d9b94f28 JL	136
6d0f6bcf JCPV	137	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
6d0f6bcf JCPV	138	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
d9b94f28 JL	139	asm("msync");
	140
	141	/*
	142	* MPC8548 uses "new" 15-16 style addressing.
	143	*/
	144	cpu_board_rev = get_cpu_board_revision();
6d0f6bcf	145	lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
b0fe93ed	146	lsdmr_common \|= LSDMR_BSMA1516;
d9b94f28 JL	147
	148	/*
	149	* Issue PRECHARGE ALL command.
	150	*/
b0fe93ed	151	lbc->lsdmr = lsdmr_common \| LSDMR_OP_PCHALL;
d9b94f28 JL	152	asm("sync;msync");
	153	*sdram_addr = 0xff;
	154	ppcDcbf((unsigned long) sdram_addr);
	155	udelay(100);
	156
	157	/*
	158	* Issue 8 AUTO REFRESH commands.
	159	*/
	160	for (idx = 0; idx < 8; idx++) {
b0fe93ed	161	lbc->lsdmr = lsdmr_common \| LSDMR_OP_ARFRSH;
d9b94f28 JL	162	asm("sync;msync");
	163	*sdram_addr = 0xff;
	164	ppcDcbf((unsigned long) sdram_addr);
	165	udelay(100);
	166	}
	167
	168	/*
	169	* Issue 8 MODE-set command.
	170	*/
b0fe93ed	171	lbc->lsdmr = lsdmr_common \| LSDMR_OP_MRW;
d9b94f28 JL	172	asm("sync;msync");
	173	*sdram_addr = 0xff;
	174	ppcDcbf((unsigned long) sdram_addr);
	175	udelay(100);
	176
	177	/*
	178	* Issue NORMAL OP command.
	179	*/
b0fe93ed	180	lbc->lsdmr = lsdmr_common \| LSDMR_OP_NORMAL;
d9b94f28 JL	181	asm("sync;msync");
	182	*sdram_addr = 0xff;
	183	ppcDcbf((unsigned long) sdram_addr);
	184	udelay(200); /* Overkill. Must wait > 200 bus cycles */
	185
	186	#endif /* enable SDRAM init */
	187	}
	188
f2cff6b1	189	#if defined(CONFIG_PCI) \|\| defined(CONFIG_PCI1)
bf1dfffd MM	190	/* For some reason the Tundra PCI bridge shows up on itself as a
bf1dfffd MM	191	* different device. Work around that by refusing to configure it.
d9b94f28	192	*/
bf1dfffd	193	void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
d9b94f28	194
d9b94f28	195	static struct pci_config_table pci_mpc85xxcds_config_table[] = {
bf1dfffd	196	{0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
7f3f2bd2 RV	197	{0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
7f3f2bd2 RV	198	{0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
ffa621a0	199	mpc85xx_config_via_usbide, {0,0,0}},
7f3f2bd2 RV	200	{0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
	201	mpc85xx_config_via_usb, {0,0,0}},
	202	{0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
	203	mpc85xx_config_via_usb2, {0,0,0}},
	204	{0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
ffa621a0	205	mpc85xx_config_via_power, {0,0,0}},
7f3f2bd2 RV	206	{0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
7f3f2bd2 RV	207	mpc85xx_config_via_ac97, {0,0,0}},
ffa621a0	208	{},
d9b94f28	209	};
d9b94f28	210
f2cff6b1 ES	211	static struct pci_controller pci1_hose = {
f2cff6b1 ES	212	config_table: pci_mpc85xxcds_config_table};
d9b94f28 JL	213	#endif /* CONFIG_PCI */
d9b94f28 JL	214
f2cff6b1 ES	215	#ifdef CONFIG_PCI2
	216	static struct pci_controller pci2_hose;
	217	#endif /* CONFIG_PCI2 */
	218
	219	#ifdef CONFIG_PCIE1
	220	static struct pci_controller pcie1_hose;
	221	#endif /* CONFIG_PCIE1 */
	222
7b626880	223	void pci_init_board(void)
d9b94f28	224	{
6d0f6bcf	225	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
7b626880 KG	226	struct fsl_pci_info pci_info[4];
	227	u32 devdisr, pordevsr, io_sel;
	228	u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
	229	int first_free_busno = 0;
	230	int num = 0;
f2cff6b1	231
7b626880	232	int pcie_ep, pcie_configured;
f2cff6b1	233
7b626880 KG	234	devdisr = in_be32(&gur->devdisr);
	235	pordevsr = in_be32(&gur->pordevsr);
	236	porpllsr = in_be32(&gur->porpllsr);
	237	io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
f2cff6b1	238
7b626880	239	debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
f2cff6b1	240
7b626880 KG	241	#ifdef CONFIG_PCI1
	242	pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
	243	pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */
	244	pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
	245	pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
	246
	247	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
	248	SET_STD_PCI_INFO(pci_info[num], 1);
	249	pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
8ca78f2c	250	printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
f2cff6b1 ES	251	(pci_32) ? 32 : 64,
	252	(pci_speed == 33333000) ? "33" :
	253	(pci_speed == 66666000) ? "66" : "unknown",
	254	pci_clk_sel ? "sync" : "async",
	255	pci_agent ? "agent" : "host",
7b626880 KG	256	pci_arb ? "arbiter" : "external-arbiter",
	257	pci_info[num].regs);
	258
	259	first_free_busno = fsl_pci_init_port(&pci_info[num++],
	260	&pci1_hose, first_free_busno);
	261
f2cff6b1	262	#ifdef CONFIG_PCIX_CHECK
7b626880	263	if (!(pordevsr & MPC85xx_PORDEVSR_PCI1)) {
f2cff6b1 ES	264	/* PCI-X init */
	265	if (CONFIG_SYS_CLK_FREQ < 66000000)
	266	printf("PCI-X will only work at 66 MHz\n");
	267
	268	reg16 = PCI_X_CMD_MAX_SPLIT \| PCI_X_CMD_MAX_READ
	269	\| PCI_X_CMD_ERO \| PCI_X_CMD_DPERR_E;
	270	pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16);
	271	}
d9b94f28	272	#endif
f2cff6b1	273	} else {
8ca78f2c	274	printf("PCI: disabled\n");
f2cff6b1	275	}
7b626880 KG	276
7b626880 KG	277	puts("\n");
f2cff6b1	278	#else
7b626880	279	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
f2cff6b1 ES	280	#endif
	281
	282	#ifdef CONFIG_PCI2
	283	{
7b626880	284	uint pci2_clk_sel = porpllsr & 0x4000; /* PORPLLSR[17] */
f2cff6b1 ES	285	uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
f2cff6b1 ES	286	if (pci_dual) {
8ca78f2c	287	printf("PCI2: 32 bit, 66 MHz, %s\n",
f2cff6b1 ES	288	pci2_clk_sel ? "sync" : "async");
f2cff6b1 ES	289	} else {
8ca78f2c	290	printf("PCI2: disabled\n");
f2cff6b1 ES	291	}
	292	}
	293	#else
7b626880	294	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable */
f2cff6b1 ES	295	#endif /* CONFIG_PCI2 */
	296
	297	#ifdef CONFIG_PCIE1
5d27e02c	298	pcie_configured = is_serdes_configured(PCIE1);
f2cff6b1	299
7b626880 KG	300	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
	301	SET_STD_PCIE_INFO(pci_info[num], 1);
	302	pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
8ca78f2c PT	303	printf("PCIE1: connected to Slot as %s (base addr %lx)\n",
	304	pcie_ep ? "Endpoint" : "Root Complex",
	305	pci_info[num].regs);
f2cff6b1	306
7b626880 KG	307	first_free_busno = fsl_pci_init_port(&pci_info[num++],
7b626880 KG	308	&pcie1_hose, first_free_busno);
f2cff6b1	309	} else {
8ca78f2c	310	printf("PCIE1: disabled\n");
f2cff6b1	311	}
7b626880 KG	312
7b626880 KG	313	puts("\n");
f2cff6b1	314	#else
7b626880	315	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
f2cff6b1	316	#endif
d9b94f28	317	}
09f3e09e AF	318
	319	int last_stage_init(void)
	320	{
f5012827	321	unsigned short temp;
09f3e09e AF	322
	323	/* Change the resistors for the PHY */
	324	/* This is needed to get the RGMII working for the 1.3+
	325	* CDS cards */
	326	if (get_board_version() == 0x13) {
255a3577	327	miiphy_write(CONFIG_TSEC1_NAME,
09f3e09e AF	328	TSEC1_PHY_ADDR, 29, 18);
09f3e09e AF	329
255a3577	330	miiphy_read(CONFIG_TSEC1_NAME,
09f3e09e AF	331	TSEC1_PHY_ADDR, 30, &temp);
	332
	333	temp = (temp & 0xf03f);
	334	temp \|= 2 << 9; /* 36 ohm */
	335	temp \|= 2 << 6; /* 39 ohm */
	336
255a3577	337	miiphy_write(CONFIG_TSEC1_NAME,
09f3e09e AF	338	TSEC1_PHY_ADDR, 30, temp);
09f3e09e AF	339
255a3577	340	miiphy_write(CONFIG_TSEC1_NAME,
09f3e09e AF	341	TSEC1_PHY_ADDR, 29, 3);
09f3e09e AF	342
255a3577	343	miiphy_write(CONFIG_TSEC1_NAME,
09f3e09e AF	344	TSEC1_PHY_ADDR, 30, 0x8000);
	345	}
	346
	347	return 0;
	348	}
f2cff6b1 ES	349
f2cff6b1 ES	350
b90d2549	351	#if defined(CONFIG_OF_BOARD_SETUP)
2dba0dea KG	352	void ft_pci_setup(void blob, bd_t bd)
2dba0dea KG	353	{
6525d51f	354	FT_FSL_PCI_SETUP;
f2cff6b1 ES	355	}
f2cff6b1 ES	356	#endif