[J-u-boot.git] / drivers / net / mcffec.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2000-2004
 * Wolfgang Denk, DENX Software Engineering, [email protected].
 *
 * (C) Copyright 2007 Freescale Semiconductor, Inc.
 * TsiChung Liew ([email protected])
 */

#include <common.h>
#include <env.h>
#include <malloc.h>

#include <command.h>
#include <net.h>
#include <netdev.h>
#include <miiphy.h>

#include <asm/fec.h>
#include <asm/immap.h>
#include <linux/mii.h>

#undef	ET_DEBUG
#undef	MII_DEBUG

/* Ethernet Transmit and Receive Buffers */
#define DBUF_LENGTH		1520
#define TX_BUF_CNT		2
#define PKT_MAXBUF_SIZE		1518
#define PKT_MINBUF_SIZE		64
#define PKT_MAXBLR_SIZE		1520
#define LAST_PKTBUFSRX		PKTBUFSRX - 1
#define BD_ENET_RX_W_E		(BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY)
#define BD_ENET_TX_RDY_LST	(BD_ENET_TX_READY | BD_ENET_TX_LAST)

struct fec_info_s fec_info[] = {
#ifdef CONFIG_SYS_FEC0_IOBASE
	{
	 0,			/* index */
	 CONFIG_SYS_FEC0_IOBASE,	/* io base */
	 CONFIG_SYS_FEC0_PINMUX,	/* gpio pin muxing */
	 CONFIG_SYS_FEC0_MIIBASE,	/* mii base */
	 -1,			/* phy_addr */
	 0,			/* duplex and speed */
	 0,			/* phy name */
	 0,			/* phyname init */
	 0,			/* RX BD */
	 0,			/* TX BD */
	 0,			/* rx Index */
	 0,			/* tx Index */
	 0,			/* tx buffer */
	 0,			/* initialized flag */
	 (struct fec_info_s *)-1,
	 },
#endif
#ifdef CONFIG_SYS_FEC1_IOBASE
	{
	 1,			/* index */
	 CONFIG_SYS_FEC1_IOBASE,	/* io base */
	 CONFIG_SYS_FEC1_PINMUX,	/* gpio pin muxing */
	 CONFIG_SYS_FEC1_MIIBASE,	/* mii base */
	 -1,			/* phy_addr */
	 0,			/* duplex and speed */
	 0,			/* phy name */
	 0,			/* phy name init */
#ifdef CONFIG_SYS_FEC_BUF_USE_SRAM
	 (cbd_t *)DBUF_LENGTH,	/* RX BD */
#else
	 0,			/* RX BD */
#endif
	 0,			/* TX BD */
	 0,			/* rx Index */
	 0,			/* tx Index */
	 0,			/* tx buffer */
	 0,			/* initialized flag */
	 (struct fec_info_s *)-1,
	 }
#endif
};

int fec_recv(struct eth_device *dev);
int fec_init(struct eth_device *dev, bd_t * bd);
void fec_halt(struct eth_device *dev);
void fec_reset(struct eth_device *dev);

void setFecDuplexSpeed(volatile fec_t * fecp, bd_t * bd, int dup_spd)
{
	if ((dup_spd >> 16) == FULL) {
		/* Set maximum frame length */
		fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE |
		    FEC_RCR_PROM | 0x100;
		fecp->tcr = FEC_TCR_FDEN;
	} else {
		/* Half duplex mode */
		fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) |
		    FEC_RCR_MII_MODE | FEC_RCR_DRT;
		fecp->tcr &= ~FEC_TCR_FDEN;
	}

	if ((dup_spd & 0xFFFF) == _100BASET) {
#ifdef CONFIG_MCF5445x
		fecp->rcr &= ~0x200;	/* disabled 10T base */
#endif
#ifdef MII_DEBUG
		printf("100Mbps\n");
#endif
		bd->bi_ethspeed = 100;
	} else {
#ifdef CONFIG_MCF5445x
		fecp->rcr |= 0x200;	/* enabled 10T base */
#endif
#ifdef MII_DEBUG
		printf("10Mbps\n");
#endif
		bd->bi_ethspeed = 10;
	}
}

static int fec_send(struct eth_device *dev, void *packet, int length)
{
	struct fec_info_s *info = dev->priv;
	volatile fec_t *fecp = (fec_t *) (info->iobase);
	int j, rc;
	u16 phyStatus;

	miiphy_read(dev->name, info->phy_addr, MII_BMSR, &phyStatus);

	/* section 16.9.23.3
	 * Wait for ready
	 */
	j = 0;
	while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) &&
	       (j < MCFFEC_TOUT_LOOP)) {
		udelay(1);
		j++;
	}
	if (j >= MCFFEC_TOUT_LOOP) {
		printf("TX not ready\n");
	}

	info->txbd[info->txIdx].cbd_bufaddr = (uint) packet;
	info->txbd[info->txIdx].cbd_datlen = length;
	info->txbd[info->txIdx].cbd_sc |= BD_ENET_TX_RDY_LST;

	/* Activate transmit Buffer Descriptor polling */
	fecp->tdar = 0x01000000;	/* Descriptor polling active    */

#ifndef CONFIG_SYS_FEC_BUF_USE_SRAM
	/*
	 * FEC unable to initial transmit data packet.
	 * A nop will ensure the descriptor polling active completed.
	 * CF Internal RAM has shorter cycle access than DRAM. If use
	 * DRAM as Buffer descriptor and data, a nop is a must.
	 * Affect only V2 and V3.
	 */
	__asm__ ("nop");

#endif

#ifdef CONFIG_SYS_UNIFY_CACHE
	icache_invalid();
#endif

	j = 0;
	while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) &&
	       (j < MCFFEC_TOUT_LOOP)) {
		udelay(1);
		j++;
	}
	if (j >= MCFFEC_TOUT_LOOP) {
		printf("TX timeout\n");
	}

#ifdef ET_DEBUG
	printf("%s[%d] %s: cycles: %d    status: %x  retry cnt: %d\n",
	       __FILE__, __LINE__, __FUNCTION__, j,
	       info->txbd[info->txIdx].cbd_sc,
	       (info->txbd[info->txIdx].cbd_sc & 0x003C) >> 2);
#endif

	/* return only status bits */
	rc = (info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_STATS);
	info->txIdx = (info->txIdx + 1) % TX_BUF_CNT;

	return rc;
}

int fec_recv(struct eth_device *dev)
{
	struct fec_info_s *info = dev->priv;
	volatile fec_t *fecp = (fec_t *) (info->iobase);
	int length;

	for (;;) {
#ifndef CONFIG_SYS_FEC_BUF_USE_SRAM
#endif
#ifdef CONFIG_SYS_UNIFY_CACHE
		icache_invalid();
#endif
		/* section 16.9.23.2 */
		if (info->rxbd[info->rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
			length = -1;
			break;	/* nothing received - leave for() loop */
		}

		length = info->rxbd[info->rxIdx].cbd_datlen;

		if (info->rxbd[info->rxIdx].cbd_sc & 0x003f) {
			printf("%s[%d] err: %x\n",
			       __FUNCTION__, __LINE__,
			       info->rxbd[info->rxIdx].cbd_sc);
#ifdef ET_DEBUG
			printf("%s[%d] err: %x\n",
			       __FUNCTION__, __LINE__,
			       info->rxbd[info->rxIdx].cbd_sc);
#endif
		} else {

			length -= 4;
			/* Pass the packet up to the protocol layers. */
			net_process_received_packet(net_rx_packets[info->rxIdx],
						    length);

			fecp->eir |= FEC_EIR_RXF;
		}

		/* Give the buffer back to the FEC. */
		info->rxbd[info->rxIdx].cbd_datlen = 0;

		/* wrap around buffer index when necessary */
		if (info->rxIdx == LAST_PKTBUFSRX) {
			info->rxbd[PKTBUFSRX - 1].cbd_sc = BD_ENET_RX_W_E;
			info->rxIdx = 0;
		} else {
			info->rxbd[info->rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
			info->rxIdx++;
		}

		/* Try to fill Buffer Descriptors */
		fecp->rdar = 0x01000000;	/* Descriptor polling active    */
	}

	return length;
}

#ifdef ET_DEBUG
void dbgFecRegs(struct eth_device *dev)
{
	struct fec_info_s *info = dev->priv;
	volatile fec_t *fecp = (fec_t *) (info->iobase);

	printf("=====\n");
	printf("ievent       %x - %x\n", (int)&fecp->eir, fecp->eir);
	printf("imask        %x - %x\n", (int)&fecp->eimr, fecp->eimr);
	printf("r_des_active %x - %x\n", (int)&fecp->rdar, fecp->rdar);
	printf("x_des_active %x - %x\n", (int)&fecp->tdar, fecp->tdar);
	printf("ecntrl       %x - %x\n", (int)&fecp->ecr, fecp->ecr);
	printf("mii_mframe   %x - %x\n", (int)&fecp->mmfr, fecp->mmfr);
	printf("mii_speed    %x - %x\n", (int)&fecp->mscr, fecp->mscr);
	printf("mii_ctrlstat %x - %x\n", (int)&fecp->mibc, fecp->mibc);
	printf("r_cntrl      %x - %x\n", (int)&fecp->rcr, fecp->rcr);
	printf("x_cntrl      %x - %x\n", (int)&fecp->tcr, fecp->tcr);
	printf("padr_l       %x - %x\n", (int)&fecp->palr, fecp->palr);
	printf("padr_u       %x - %x\n", (int)&fecp->paur, fecp->paur);
	printf("op_pause     %x - %x\n", (int)&fecp->opd, fecp->opd);
	printf("iadr_u       %x - %x\n", (int)&fecp->iaur, fecp->iaur);
	printf("iadr_l       %x - %x\n", (int)&fecp->ialr, fecp->ialr);
	printf("gadr_u       %x - %x\n", (int)&fecp->gaur, fecp->gaur);
	printf("gadr_l       %x - %x\n", (int)&fecp->galr, fecp->galr);
	printf("x_wmrk       %x - %x\n", (int)&fecp->tfwr, fecp->tfwr);
	printf("r_bound      %x - %x\n", (int)&fecp->frbr, fecp->frbr);
	printf("r_fstart     %x - %x\n", (int)&fecp->frsr, fecp->frsr);
	printf("r_drng       %x - %x\n", (int)&fecp->erdsr, fecp->erdsr);
	printf("x_drng       %x - %x\n", (int)&fecp->etdsr, fecp->etdsr);
	printf("r_bufsz      %x - %x\n", (int)&fecp->emrbr, fecp->emrbr);

	printf("\n");
	printf("rmon_t_drop        %x - %x\n", (int)&fecp->rmon_t_drop,
	       fecp->rmon_t_drop);
	printf("rmon_t_packets     %x - %x\n", (int)&fecp->rmon_t_packets,
	       fecp->rmon_t_packets);
	printf("rmon_t_bc_pkt      %x - %x\n", (int)&fecp->rmon_t_bc_pkt,
	       fecp->rmon_t_bc_pkt);
	printf("rmon_t_mc_pkt      %x - %x\n", (int)&fecp->rmon_t_mc_pkt,
	       fecp->rmon_t_mc_pkt);
	printf("rmon_t_crc_align   %x - %x\n", (int)&fecp->rmon_t_crc_align,
	       fecp->rmon_t_crc_align);
	printf("rmon_t_undersize   %x - %x\n", (int)&fecp->rmon_t_undersize,
	       fecp->rmon_t_undersize);
	printf("rmon_t_oversize    %x - %x\n", (int)&fecp->rmon_t_oversize,
	       fecp->rmon_t_oversize);
	printf("rmon_t_frag        %x - %x\n", (int)&fecp->rmon_t_frag,
	       fecp->rmon_t_frag);
	printf("rmon_t_jab         %x - %x\n", (int)&fecp->rmon_t_jab,
	       fecp->rmon_t_jab);
	printf("rmon_t_col         %x - %x\n", (int)&fecp->rmon_t_col,
	       fecp->rmon_t_col);
	printf("rmon_t_p64         %x - %x\n", (int)&fecp->rmon_t_p64,
	       fecp->rmon_t_p64);
	printf("rmon_t_p65to127    %x - %x\n", (int)&fecp->rmon_t_p65to127,
	       fecp->rmon_t_p65to127);
	printf("rmon_t_p128to255   %x - %x\n", (int)&fecp->rmon_t_p128to255,
	       fecp->rmon_t_p128to255);
	printf("rmon_t_p256to511   %x - %x\n", (int)&fecp->rmon_t_p256to511,
	       fecp->rmon_t_p256to511);
	printf("rmon_t_p512to1023  %x - %x\n", (int)&fecp->rmon_t_p512to1023,
	       fecp->rmon_t_p512to1023);
	printf("rmon_t_p1024to2047 %x - %x\n", (int)&fecp->rmon_t_p1024to2047,
	       fecp->rmon_t_p1024to2047);
	printf("rmon_t_p_gte2048   %x - %x\n", (int)&fecp->rmon_t_p_gte2048,
	       fecp->rmon_t_p_gte2048);
	printf("rmon_t_octets      %x - %x\n", (int)&fecp->rmon_t_octets,
	       fecp->rmon_t_octets);

	printf("\n");
	printf("ieee_t_drop      %x - %x\n", (int)&fecp->ieee_t_drop,
	       fecp->ieee_t_drop);
	printf("ieee_t_frame_ok  %x - %x\n", (int)&fecp->ieee_t_frame_ok,
	       fecp->ieee_t_frame_ok);
	printf("ieee_t_1col      %x - %x\n", (int)&fecp->ieee_t_1col,
	       fecp->ieee_t_1col);
	printf("ieee_t_mcol      %x - %x\n", (int)&fecp->ieee_t_mcol,
	       fecp->ieee_t_mcol);
	printf("ieee_t_def       %x - %x\n", (int)&fecp->ieee_t_def,
	       fecp->ieee_t_def);
	printf("ieee_t_lcol      %x - %x\n", (int)&fecp->ieee_t_lcol,
	       fecp->ieee_t_lcol);
	printf("ieee_t_excol     %x - %x\n", (int)&fecp->ieee_t_excol,
	       fecp->ieee_t_excol);
	printf("ieee_t_macerr    %x - %x\n", (int)&fecp->ieee_t_macerr,
	       fecp->ieee_t_macerr);
	printf("ieee_t_cserr     %x - %x\n", (int)&fecp->ieee_t_cserr,
	       fecp->ieee_t_cserr);
	printf("ieee_t_sqe       %x - %x\n", (int)&fecp->ieee_t_sqe,
	       fecp->ieee_t_sqe);
	printf("ieee_t_fdxfc     %x - %x\n", (int)&fecp->ieee_t_fdxfc,
	       fecp->ieee_t_fdxfc);
	printf("ieee_t_octets_ok %x - %x\n", (int)&fecp->ieee_t_octets_ok,
	       fecp->ieee_t_octets_ok);

	printf("\n");
	printf("rmon_r_drop        %x - %x\n", (int)&fecp->rmon_r_drop,
	       fecp->rmon_r_drop);
	printf("rmon_r_packets     %x - %x\n", (int)&fecp->rmon_r_packets,
	       fecp->rmon_r_packets);
	printf("rmon_r_bc_pkt      %x - %x\n", (int)&fecp->rmon_r_bc_pkt,
	       fecp->rmon_r_bc_pkt);
	printf("rmon_r_mc_pkt      %x - %x\n", (int)&fecp->rmon_r_mc_pkt,
	       fecp->rmon_r_mc_pkt);
	printf("rmon_r_crc_align   %x - %x\n", (int)&fecp->rmon_r_crc_align,
	       fecp->rmon_r_crc_align);
	printf("rmon_r_undersize   %x - %x\n", (int)&fecp->rmon_r_undersize,
	       fecp->rmon_r_undersize);
	printf("rmon_r_oversize    %x - %x\n", (int)&fecp->rmon_r_oversize,
	       fecp->rmon_r_oversize);
	printf("rmon_r_frag        %x - %x\n", (int)&fecp->rmon_r_frag,
	       fecp->rmon_r_frag);
	printf("rmon_r_jab         %x - %x\n", (int)&fecp->rmon_r_jab,
	       fecp->rmon_r_jab);
	printf("rmon_r_p64         %x - %x\n", (int)&fecp->rmon_r_p64,
	       fecp->rmon_r_p64);
	printf("rmon_r_p65to127    %x - %x\n", (int)&fecp->rmon_r_p65to127,
	       fecp->rmon_r_p65to127);
	printf("rmon_r_p128to255   %x - %x\n", (int)&fecp->rmon_r_p128to255,
	       fecp->rmon_r_p128to255);
	printf("rmon_r_p256to511   %x - %x\n", (int)&fecp->rmon_r_p256to511,
	       fecp->rmon_r_p256to511);
	printf("rmon_r_p512to1023  %x - %x\n", (int)&fecp->rmon_r_p512to1023,
	       fecp->rmon_r_p512to1023);
	printf("rmon_r_p1024to2047 %x - %x\n", (int)&fecp->rmon_r_p1024to2047,
	       fecp->rmon_r_p1024to2047);
	printf("rmon_r_p_gte2048   %x - %x\n", (int)&fecp->rmon_r_p_gte2048,
	       fecp->rmon_r_p_gte2048);
	printf("rmon_r_octets      %x - %x\n", (int)&fecp->rmon_r_octets,
	       fecp->rmon_r_octets);

	printf("\n");
	printf("ieee_r_drop      %x - %x\n", (int)&fecp->ieee_r_drop,
	       fecp->ieee_r_drop);
	printf("ieee_r_frame_ok  %x - %x\n", (int)&fecp->ieee_r_frame_ok,
	       fecp->ieee_r_frame_ok);
	printf("ieee_r_crc       %x - %x\n", (int)&fecp->ieee_r_crc,
	       fecp->ieee_r_crc);
	printf("ieee_r_align     %x - %x\n", (int)&fecp->ieee_r_align,
	       fecp->ieee_r_align);
	printf("ieee_r_macerr    %x - %x\n", (int)&fecp->ieee_r_macerr,
	       fecp->ieee_r_macerr);
	printf("ieee_r_fdxfc     %x - %x\n", (int)&fecp->ieee_r_fdxfc,
	       fecp->ieee_r_fdxfc);
	printf("ieee_r_octets_ok %x - %x\n", (int)&fecp->ieee_r_octets_ok,
	       fecp->ieee_r_octets_ok);

	printf("\n\n\n");
}
#endif

int fec_init(struct eth_device *dev, bd_t * bd)
{
	struct fec_info_s *info = dev->priv;
	volatile fec_t *fecp = (fec_t *) (info->iobase);
	int i;
	uchar ea[6];

	fecpin_setclear(dev, 1);

	fec_reset(dev);

#if defined(CONFIG_CMD_MII) || defined (CONFIG_MII) || \
	defined (CONFIG_SYS_DISCOVER_PHY)

	mii_init();

	setFecDuplexSpeed(fecp, bd, info->dup_spd);
#else
#ifndef CONFIG_SYS_DISCOVER_PHY
	setFecDuplexSpeed(fecp, bd, (FECDUPLEX << 16) | FECSPEED);
#endif				/* ifndef CONFIG_SYS_DISCOVER_PHY */
#endif				/* CONFIG_CMD_MII || CONFIG_MII */

	/* We use strictly polling mode only */
	fecp->eimr = 0;

	/* Clear any pending interrupt */
	fecp->eir = 0xffffffff;

	/* Set station address   */
	if ((u32) fecp == CONFIG_SYS_FEC0_IOBASE) {
#ifdef CONFIG_SYS_FEC1_IOBASE
		volatile fec_t *fecp1 = (fec_t *) (CONFIG_SYS_FEC1_IOBASE);
		eth_env_get_enetaddr("eth1addr", ea);
		fecp1->palr =
		    (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
		fecp1->paur = (ea[4] << 24) | (ea[5] << 16);
#endif
		eth_env_get_enetaddr("ethaddr", ea);
		fecp->palr =
		    (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
		fecp->paur = (ea[4] << 24) | (ea[5] << 16);
	} else {
#ifdef CONFIG_SYS_FEC0_IOBASE
		volatile fec_t *fecp0 = (fec_t *) (CONFIG_SYS_FEC0_IOBASE);
		eth_env_get_enetaddr("ethaddr", ea);
		fecp0->palr =
		    (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
		fecp0->paur = (ea[4] << 24) | (ea[5] << 16);
#endif
#ifdef CONFIG_SYS_FEC1_IOBASE
		eth_env_get_enetaddr("eth1addr", ea);
		fecp->palr =
		    (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
		fecp->paur = (ea[4] << 24) | (ea[5] << 16);
#endif
	}

	/* Clear unicast address hash table */
	fecp->iaur = 0;
	fecp->ialr = 0;

	/* Clear multicast address hash table */
	fecp->gaur = 0;
	fecp->galr = 0;

	/* Set maximum receive buffer size. */
	fecp->emrbr = PKT_MAXBLR_SIZE;

	/*
	 * Setup Buffers and Buffer Descriptors
	 */
	info->rxIdx = 0;
	info->txIdx = 0;

	/*
	 * Setup Receiver Buffer Descriptors (13.14.24.18)
	 * Settings:
	 *     Empty, Wrap
	 */
	for (i = 0; i < PKTBUFSRX; i++) {
		info->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
		info->rxbd[i].cbd_datlen = 0;	/* Reset */
		info->rxbd[i].cbd_bufaddr = (uint) net_rx_packets[i];
	}
	info->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;

	/*
	 * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
	 * Settings:
	 *    Last, Tx CRC
	 */
	for (i = 0; i < TX_BUF_CNT; i++) {
		info->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC;
		info->txbd[i].cbd_datlen = 0;	/* Reset */
		info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]);
	}
	info->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;

	/* Set receive and transmit descriptor base */
	fecp->erdsr = (unsigned int)(&info->rxbd[0]);
	fecp->etdsr = (unsigned int)(&info->txbd[0]);

	/* Now enable the transmit and receive processing */
	fecp->ecr |= FEC_ECR_ETHER_EN;

	/* And last, try to fill Rx Buffer Descriptors */
	fecp->rdar = 0x01000000;	/* Descriptor polling active    */

	return 1;
}

void fec_reset(struct eth_device *dev)
{
	struct fec_info_s *info = dev->priv;
	volatile fec_t *fecp = (fec_t *) (info->iobase);
	int i;

	fecp->ecr = FEC_ECR_RESET;
	for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
		udelay(1);
	}
	if (i == FEC_RESET_DELAY) {
		printf("FEC_RESET_DELAY timeout\n");
	}
}

void fec_halt(struct eth_device *dev)
{
	struct fec_info_s *info = dev->priv;

	fec_reset(dev);

	fecpin_setclear(dev, 0);

	info->rxIdx = info->txIdx = 0;
	memset(info->rxbd, 0, PKTBUFSRX * sizeof(cbd_t));
	memset(info->txbd, 0, TX_BUF_CNT * sizeof(cbd_t));
	memset(info->txbuf, 0, DBUF_LENGTH);
}

int mcffec_initialize(bd_t * bis)
{
	struct eth_device *dev;
	int i;
#ifdef CONFIG_SYS_FEC_BUF_USE_SRAM
	u32 tmp = CONFIG_SYS_INIT_RAM_ADDR + 0x1000;
#endif

	for (i = 0; i < ARRAY_SIZE(fec_info); i++) {

		dev =
		    (struct eth_device *)memalign(CONFIG_SYS_CACHELINE_SIZE,
						  sizeof *dev);
		if (dev == NULL)
			hang();

		memset(dev, 0, sizeof(*dev));

		sprintf(dev->name, "FEC%d", fec_info[i].index);

		dev->priv = &fec_info[i];
		dev->init = fec_init;
		dev->halt = fec_halt;
		dev->send = fec_send;
		dev->recv = fec_recv;

		/* setup Receive and Transmit buffer descriptor */
#ifdef CONFIG_SYS_FEC_BUF_USE_SRAM
		fec_info[i].rxbd = (cbd_t *)((u32)fec_info[i].rxbd + tmp);
		tmp = (u32)fec_info[i].rxbd;
		fec_info[i].txbd =
		    (cbd_t *)((u32)fec_info[i].txbd + tmp +
		    (PKTBUFSRX * sizeof(cbd_t)));
		tmp = (u32)fec_info[i].txbd;
		fec_info[i].txbuf =
		    (char *)((u32)fec_info[i].txbuf + tmp +
		    (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
		tmp = (u32)fec_info[i].txbuf;
#else
		fec_info[i].rxbd =
		    (cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE,
				       (PKTBUFSRX * sizeof(cbd_t)));
		fec_info[i].txbd =
		    (cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE,
				       (TX_BUF_CNT * sizeof(cbd_t)));
		fec_info[i].txbuf =
		    (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, DBUF_LENGTH);
#endif

#ifdef ET_DEBUG
		printf("rxbd %x txbd %x\n",
		       (int)fec_info[i].rxbd, (int)fec_info[i].txbd);
#endif

		fec_info[i].phy_name = (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, 32);

		eth_register(dev);

#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
		int retval;
		struct mii_dev *mdiodev = mdio_alloc();
		if (!mdiodev)
			return -ENOMEM;
		strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
		mdiodev->read = mcffec_miiphy_read;
		mdiodev->write = mcffec_miiphy_write;

		retval = mdio_register(mdiodev);
		if (retval < 0)
			return retval;
#endif
		if (i > 0)
			fec_info[i - 1].next = &fec_info[i];
	}
	fec_info[i - 1].next = &fec_info[0];

	/* default speed */
	bis->bi_ethspeed = 10;

	return 0;
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
8e585f02 TL	2	/*
	3	* (C) Copyright 2000-2004
	4	* Wolfgang Denk, DENX Software Engineering, [email protected].
	5	*
f2208fbc	6	* (C) Copyright 2007 Freescale Semiconductor, Inc.
8e585f02	7	* TsiChung Liew ([email protected])
8e585f02 TL	8	*/
	9
	10	#include <common.h>
7b51b576	11	#include <env.h>
8e585f02 TL	12	#include <malloc.h>
8e585f02 TL	13
8e585f02	14	#include <command.h>
8e585f02	15	#include <net.h>
89973f8a	16	#include <netdev.h>
8e585f02 TL	17	#include <miiphy.h>
8e585f02 TL	18
54bdcc9f TL	19	#include <asm/fec.h>
54bdcc9f TL	20	#include <asm/immap.h>
68a6aa85	21	#include <linux/mii.h>
54bdcc9f	22
8e585f02 TL	23	#undef ET_DEBUG
	24	#undef MII_DEBUG
	25
	26	/* Ethernet Transmit and Receive Buffers */
f2208fbc TL	27	#define DBUF_LENGTH 1520
f2208fbc TL	28	#define TX_BUF_CNT 2
8e585f02 TL	29	#define PKT_MAXBUF_SIZE 1518
	30	#define PKT_MINBUF_SIZE 64
	31	#define PKT_MAXBLR_SIZE 1520
	32	#define LAST_PKTBUFSRX PKTBUFSRX - 1
	33	#define BD_ENET_RX_W_E (BD_ENET_RX_WRAP \| BD_ENET_RX_EMPTY)
	34	#define BD_ENET_TX_RDY_LST (BD_ENET_TX_READY \| BD_ENET_TX_LAST)
	35
8e585f02	36	struct fec_info_s fec_info[] = {
6d0f6bcf	37	#ifdef CONFIG_SYS_FEC0_IOBASE
8e585f02 TL	38	{
8e585f02 TL	39	0, /* index */
6d0f6bcf JCPV	40	CONFIG_SYS_FEC0_IOBASE, /* io base */
	41	CONFIG_SYS_FEC0_PINMUX, /* gpio pin muxing */
	42	CONFIG_SYS_FEC0_MIIBASE, /* mii base */
8e585f02 TL	43	-1, /* phy_addr */
	44	0, /* duplex and speed */
	45	0, /* phy name */
	46	0, /* phyname init */
	47	0, /* RX BD */
	48	0, /* TX BD */
	49	0, /* rx Index */
	50	0, /* tx Index */
	51	0, /* tx buffer */
	52	0, /* initialized flag */
1803f7f9	53	(struct fec_info_s *)-1,
8e585f02 TL	54	},
8e585f02 TL	55	#endif
6d0f6bcf	56	#ifdef CONFIG_SYS_FEC1_IOBASE
8e585f02 TL	57	{
8e585f02 TL	58	1, /* index */
6d0f6bcf JCPV	59	CONFIG_SYS_FEC1_IOBASE, /* io base */
	60	CONFIG_SYS_FEC1_PINMUX, /* gpio pin muxing */
	61	CONFIG_SYS_FEC1_MIIBASE, /* mii base */
8e585f02 TL	62	-1, /* phy_addr */
	63	0, /* duplex and speed */
	64	0, /* phy name */
	65	0, /* phy name init */
6d0f6bcf	66	#ifdef CONFIG_SYS_FEC_BUF_USE_SRAM
1803f7f9 TL	67	(cbd_t )DBUF_LENGTH, / RX BD */
1803f7f9 TL	68	#else
8e585f02	69	0, /* RX BD */
1803f7f9	70	#endif
8e585f02 TL	71	0, /* TX BD */
	72	0, /* rx Index */
	73	0, /* tx Index */
	74	0, /* tx buffer */
	75	0, /* initialized flag */
1803f7f9	76	(struct fec_info_s *)-1,
8e585f02 TL	77	}
	78	#endif
	79	};
	80
8e585f02 TL	81	int fec_recv(struct eth_device *dev);
	82	int fec_init(struct eth_device dev, bd_t bd);
	83	void fec_halt(struct eth_device *dev);
	84	void fec_reset(struct eth_device *dev);
	85
8e585f02 TL	86	void setFecDuplexSpeed(volatile fec_t * fecp, bd_t * bd, int dup_spd)
	87	{
	88	if ((dup_spd >> 16) == FULL) {
	89	/* Set maximum frame length */
	90	fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) \| FEC_RCR_MII_MODE \|
	91	FEC_RCR_PROM \| 0x100;
	92	fecp->tcr = FEC_TCR_FDEN;
	93	} else {
	94	/* Half duplex mode */
	95	fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) \|
	96	FEC_RCR_MII_MODE \| FEC_RCR_DRT;
	97	fecp->tcr &= ~FEC_TCR_FDEN;
	98	}
	99
	100	if ((dup_spd & 0xFFFF) == _100BASET) {
ff36fbb2 TL	101	#ifdef CONFIG_MCF5445x
	102	fecp->rcr &= ~0x200; /* disabled 10T base */
	103	#endif
8e585f02 TL	104	#ifdef MII_DEBUG
	105	printf("100Mbps\n");
	106	#endif
	107	bd->bi_ethspeed = 100;
	108	} else {
ff36fbb2 TL	109	#ifdef CONFIG_MCF5445x
	110	fecp->rcr \|= 0x200; /* enabled 10T base */
	111	#endif
8e585f02 TL	112	#ifdef MII_DEBUG
	113	printf("10Mbps\n");
	114	#endif
	115	bd->bi_ethspeed = 10;
	116	}
	117	}
	118
10cbe3b6	119	static int fec_send(struct eth_device dev, void packet, int length)
8e585f02 TL	120	{
	121	struct fec_info_s *info = dev->priv;
	122	volatile fec_t fecp = (fec_t ) (info->iobase);
	123	int j, rc;
	124	u16 phyStatus;
	125
8ef583a0	126	miiphy_read(dev->name, info->phy_addr, MII_BMSR, &phyStatus);
8e585f02 TL	127
	128	/* section 16.9.23.3
	129	* Wait for ready
	130	*/
	131	j = 0;
	132	while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) &&
	133	(j < MCFFEC_TOUT_LOOP)) {
	134	udelay(1);
	135	j++;
	136	}
	137	if (j >= MCFFEC_TOUT_LOOP) {
	138	printf("TX not ready\n");
	139	}
0dca874d	140
8e585f02 TL	141	info->txbd[info->txIdx].cbd_bufaddr = (uint) packet;
	142	info->txbd[info->txIdx].cbd_datlen = length;
	143	info->txbd[info->txIdx].cbd_sc \|= BD_ENET_TX_RDY_LST;
	144
	145	/* Activate transmit Buffer Descriptor polling */
	146	fecp->tdar = 0x01000000; /* Descriptor polling active */
	147
6d0f6bcf	148	#ifndef CONFIG_SYS_FEC_BUF_USE_SRAM
1803f7f9 TL	149	/*
1803f7f9 TL	150	* FEC unable to initial transmit data packet.
f605479d	151	* A nop will ensure the descriptor polling active completed.
1803f7f9 TL	152	* CF Internal RAM has shorter cycle access than DRAM. If use
	153	* DRAM as Buffer descriptor and data, a nop is a must.
	154	* Affect only V2 and V3.
f605479d	155	*/
f605479d	156	__asm__ ("nop");
1803f7f9	157
f605479d TL	158	#endif
f605479d TL	159
6d0f6bcf	160	#ifdef CONFIG_SYS_UNIFY_CACHE
f2208fbc TL	161	icache_invalid();
f2208fbc TL	162	#endif
1803f7f9	163
0dca874d	164	j = 0;
8e585f02 TL	165	while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) &&
	166	(j < MCFFEC_TOUT_LOOP)) {
	167	udelay(1);
	168	j++;
	169	}
	170	if (j >= MCFFEC_TOUT_LOOP) {
	171	printf("TX timeout\n");
	172	}
0dca874d	173
8e585f02 TL	174	#ifdef ET_DEBUG
	175	printf("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n",
	176	__FILE__, __LINE__, __FUNCTION__, j,
	177	info->txbd[info->txIdx].cbd_sc,
	178	(info->txbd[info->txIdx].cbd_sc & 0x003C) >> 2);
	179	#endif
	180
0dca874d	181	/* return only status bits */
8e585f02 TL	182	rc = (info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_STATS);
	183	info->txIdx = (info->txIdx + 1) % TX_BUF_CNT;
	184
	185	return rc;
	186	}
	187
	188	int fec_recv(struct eth_device *dev)
	189	{
	190	struct fec_info_s *info = dev->priv;
	191	volatile fec_t fecp = (fec_t ) (info->iobase);
	192	int length;
	193
	194	for (;;) {
6d0f6bcf	195	#ifndef CONFIG_SYS_FEC_BUF_USE_SRAM
1803f7f9	196	#endif
6d0f6bcf	197	#ifdef CONFIG_SYS_UNIFY_CACHE
53677ef1	198	icache_invalid();
0dca874d	199	#endif
8e585f02 TL	200	/* section 16.9.23.2 */
	201	if (info->rxbd[info->rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
	202	length = -1;
	203	break; /* nothing received - leave for() loop */
	204	}
	205
	206	length = info->rxbd[info->rxIdx].cbd_datlen;
	207
	208	if (info->rxbd[info->rxIdx].cbd_sc & 0x003f) {
	209	printf("%s[%d] err: %x\n",
	210	__FUNCTION__, __LINE__,
	211	info->rxbd[info->rxIdx].cbd_sc);
	212	#ifdef ET_DEBUG
	213	printf("%s[%d] err: %x\n",
	214	__FUNCTION__, __LINE__,
	215	info->rxbd[info->rxIdx].cbd_sc);
	216	#endif
	217	} else {
	218
	219	length -= 4;
	220	/* Pass the packet up to the protocol layers. */
1fd92db8 JH	221	net_process_received_packet(net_rx_packets[info->rxIdx],
1fd92db8 JH	222	length);
8e585f02 TL	223
	224	fecp->eir \|= FEC_EIR_RXF;
	225	}
	226
	227	/* Give the buffer back to the FEC. */
	228	info->rxbd[info->rxIdx].cbd_datlen = 0;
	229
	230	/* wrap around buffer index when necessary */
	231	if (info->rxIdx == LAST_PKTBUFSRX) {
	232	info->rxbd[PKTBUFSRX - 1].cbd_sc = BD_ENET_RX_W_E;
	233	info->rxIdx = 0;
	234	} else {
	235	info->rxbd[info->rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
	236	info->rxIdx++;
	237	}
	238
	239	/* Try to fill Buffer Descriptors */
	240	fecp->rdar = 0x01000000; /* Descriptor polling active */
	241	}
	242
	243	return length;
	244	}
	245
8e585f02 TL	246	#ifdef ET_DEBUG
	247	void dbgFecRegs(struct eth_device *dev)
	248	{
	249	struct fec_info_s *info = dev->priv;
	250	volatile fec_t fecp = (fec_t ) (info->iobase);
	251
	252	printf("=====\n");
	253	printf("ievent %x - %x\n", (int)&fecp->eir, fecp->eir);
	254	printf("imask %x - %x\n", (int)&fecp->eimr, fecp->eimr);
	255	printf("r_des_active %x - %x\n", (int)&fecp->rdar, fecp->rdar);
	256	printf("x_des_active %x - %x\n", (int)&fecp->tdar, fecp->tdar);
	257	printf("ecntrl %x - %x\n", (int)&fecp->ecr, fecp->ecr);
	258	printf("mii_mframe %x - %x\n", (int)&fecp->mmfr, fecp->mmfr);
	259	printf("mii_speed %x - %x\n", (int)&fecp->mscr, fecp->mscr);
	260	printf("mii_ctrlstat %x - %x\n", (int)&fecp->mibc, fecp->mibc);
	261	printf("r_cntrl %x - %x\n", (int)&fecp->rcr, fecp->rcr);
	262	printf("x_cntrl %x - %x\n", (int)&fecp->tcr, fecp->tcr);
	263	printf("padr_l %x - %x\n", (int)&fecp->palr, fecp->palr);
	264	printf("padr_u %x - %x\n", (int)&fecp->paur, fecp->paur);
	265	printf("op_pause %x - %x\n", (int)&fecp->opd, fecp->opd);
	266	printf("iadr_u %x - %x\n", (int)&fecp->iaur, fecp->iaur);
	267	printf("iadr_l %x - %x\n", (int)&fecp->ialr, fecp->ialr);
	268	printf("gadr_u %x - %x\n", (int)&fecp->gaur, fecp->gaur);
	269	printf("gadr_l %x - %x\n", (int)&fecp->galr, fecp->galr);
	270	printf("x_wmrk %x - %x\n", (int)&fecp->tfwr, fecp->tfwr);
	271	printf("r_bound %x - %x\n", (int)&fecp->frbr, fecp->frbr);
	272	printf("r_fstart %x - %x\n", (int)&fecp->frsr, fecp->frsr);
	273	printf("r_drng %x - %x\n", (int)&fecp->erdsr, fecp->erdsr);
	274	printf("x_drng %x - %x\n", (int)&fecp->etdsr, fecp->etdsr);
	275	printf("r_bufsz %x - %x\n", (int)&fecp->emrbr, fecp->emrbr);
	276
	277	printf("\n");
	278	printf("rmon_t_drop %x - %x\n", (int)&fecp->rmon_t_drop,
	279	fecp->rmon_t_drop);
	280	printf("rmon_t_packets %x - %x\n", (int)&fecp->rmon_t_packets,
	281	fecp->rmon_t_packets);
	282	printf("rmon_t_bc_pkt %x - %x\n", (int)&fecp->rmon_t_bc_pkt,
	283	fecp->rmon_t_bc_pkt);
	284	printf("rmon_t_mc_pkt %x - %x\n", (int)&fecp->rmon_t_mc_pkt,
	285	fecp->rmon_t_mc_pkt);
	286	printf("rmon_t_crc_align %x - %x\n", (int)&fecp->rmon_t_crc_align,
	287	fecp->rmon_t_crc_align);
	288	printf("rmon_t_undersize %x - %x\n", (int)&fecp->rmon_t_undersize,
	289	fecp->rmon_t_undersize);
	290	printf("rmon_t_oversize %x - %x\n", (int)&fecp->rmon_t_oversize,
	291	fecp->rmon_t_oversize);
	292	printf("rmon_t_frag %x - %x\n", (int)&fecp->rmon_t_frag,
	293	fecp->rmon_t_frag);
	294	printf("rmon_t_jab %x - %x\n", (int)&fecp->rmon_t_jab,
	295	fecp->rmon_t_jab);
	296	printf("rmon_t_col %x - %x\n", (int)&fecp->rmon_t_col,
	297	fecp->rmon_t_col);
	298	printf("rmon_t_p64 %x - %x\n", (int)&fecp->rmon_t_p64,
	299	fecp->rmon_t_p64);
	300	printf("rmon_t_p65to127 %x - %x\n", (int)&fecp->rmon_t_p65to127,
	301	fecp->rmon_t_p65to127);
	302	printf("rmon_t_p128to255 %x - %x\n", (int)&fecp->rmon_t_p128to255,
	303	fecp->rmon_t_p128to255);
	304	printf("rmon_t_p256to511 %x - %x\n", (int)&fecp->rmon_t_p256to511,
	305	fecp->rmon_t_p256to511);
	306	printf("rmon_t_p512to1023 %x - %x\n", (int)&fecp->rmon_t_p512to1023,
	307	fecp->rmon_t_p512to1023);
	308	printf("rmon_t_p1024to2047 %x - %x\n", (int)&fecp->rmon_t_p1024to2047,
	309	fecp->rmon_t_p1024to2047);
310	printf("rmon_t_p_gte2048 %x - %x\n", (int)&fecp->rmon_t_p_gte2048,
311	fecp->rmon_t_p_gte2048);
312	printf("rmon_t_octets %x - %x\n", (int)&fecp->rmon_t_octets,
313	fecp->rmon_t_octets);
314
315	printf("\n");
316	printf("ieee_t_drop %x - %x\n", (int)&fecp->ieee_t_drop,
317	fecp->ieee_t_drop);
318	printf("ieee_t_frame_ok %x - %x\n", (int)&fecp->ieee_t_frame_ok,
319	fecp->ieee_t_frame_ok);
320	printf("ieee_t_1col %x - %x\n", (int)&fecp->ieee_t_1col,
321	fecp->ieee_t_1col);
322	printf("ieee_t_mcol %x - %x\n", (int)&fecp->ieee_t_mcol,
323	fecp->ieee_t_mcol);
324	printf("ieee_t_def %x - %x\n", (int)&fecp->ieee_t_def,
325	fecp->ieee_t_def);
326	printf("ieee_t_lcol %x - %x\n", (int)&fecp->ieee_t_lcol,
327	fecp->ieee_t_lcol);
328	printf("ieee_t_excol %x - %x\n", (int)&fecp->ieee_t_excol,
329	fecp->ieee_t_excol);
330	printf("ieee_t_macerr %x - %x\n", (int)&fecp->ieee_t_macerr,
331	fecp->ieee_t_macerr);
332	printf("ieee_t_cserr %x - %x\n", (int)&fecp->ieee_t_cserr,
333	fecp->ieee_t_cserr);
334	printf("ieee_t_sqe %x - %x\n", (int)&fecp->ieee_t_sqe,
335	fecp->ieee_t_sqe);
336	printf("ieee_t_fdxfc %x - %x\n", (int)&fecp->ieee_t_fdxfc,
337	fecp->ieee_t_fdxfc);
338	printf("ieee_t_octets_ok %x - %x\n", (int)&fecp->ieee_t_octets_ok,
339	fecp->ieee_t_octets_ok);
340
341	printf("\n");
342	printf("rmon_r_drop %x - %x\n", (int)&fecp->rmon_r_drop,
343	fecp->rmon_r_drop);
344	printf("rmon_r_packets %x - %x\n", (int)&fecp->rmon_r_packets,
345	fecp->rmon_r_packets);
346	printf("rmon_r_bc_pkt %x - %x\n", (int)&fecp->rmon_r_bc_pkt,
347	fecp->rmon_r_bc_pkt);
348	printf("rmon_r_mc_pkt %x - %x\n", (int)&fecp->rmon_r_mc_pkt,
349	fecp->rmon_r_mc_pkt);
350	printf("rmon_r_crc_align %x - %x\n", (int)&fecp->rmon_r_crc_align,
351	fecp->rmon_r_crc_align);
352	printf("rmon_r_undersize %x - %x\n", (int)&fecp->rmon_r_undersize,
353	fecp->rmon_r_undersize);
354	printf("rmon_r_oversize %x - %x\n", (int)&fecp->rmon_r_oversize,
355	fecp->rmon_r_oversize);
356	printf("rmon_r_frag %x - %x\n", (int)&fecp->rmon_r_frag,
357	fecp->rmon_r_frag);
358	printf("rmon_r_jab %x - %x\n", (int)&fecp->rmon_r_jab,
359	fecp->rmon_r_jab);
360	printf("rmon_r_p64 %x - %x\n", (int)&fecp->rmon_r_p64,
361	fecp->rmon_r_p64);
362	printf("rmon_r_p65to127 %x - %x\n", (int)&fecp->rmon_r_p65to127,
363	fecp->rmon_r_p65to127);
364	printf("rmon_r_p128to255 %x - %x\n", (int)&fecp->rmon_r_p128to255,
365	fecp->rmon_r_p128to255);
366	printf("rmon_r_p256to511 %x - %x\n", (int)&fecp->rmon_r_p256to511,
367	fecp->rmon_r_p256to511);
368	printf("rmon_r_p512to1023 %x - %x\n", (int)&fecp->rmon_r_p512to1023,
369	fecp->rmon_r_p512to1023);
370	printf("rmon_r_p1024to2047 %x - %x\n", (int)&fecp->rmon_r_p1024to2047,
371	fecp->rmon_r_p1024to2047);
372	printf("rmon_r_p_gte2048 %x - %x\n", (int)&fecp->rmon_r_p_gte2048,
373	fecp->rmon_r_p_gte2048);
374	printf("rmon_r_octets %x - %x\n", (int)&fecp->rmon_r_octets,
375	fecp->rmon_r_octets);
376
377	printf("\n");
378	printf("ieee_r_drop %x - %x\n", (int)&fecp->ieee_r_drop,
379	fecp->ieee_r_drop);
380	printf("ieee_r_frame_ok %x - %x\n", (int)&fecp->ieee_r_frame_ok,
381	fecp->ieee_r_frame_ok);
382	printf("ieee_r_crc %x - %x\n", (int)&fecp->ieee_r_crc,
383	fecp->ieee_r_crc);
384	printf("ieee_r_align %x - %x\n", (int)&fecp->ieee_r_align,
385	fecp->ieee_r_align);
386	printf("ieee_r_macerr %x - %x\n", (int)&fecp->ieee_r_macerr,
387	fecp->ieee_r_macerr);
388	printf("ieee_r_fdxfc %x - %x\n", (int)&fecp->ieee_r_fdxfc,
389	fecp->ieee_r_fdxfc);
390	printf("ieee_r_octets_ok %x - %x\n", (int)&fecp->ieee_r_octets_ok,
391	fecp->ieee_r_octets_ok);
392
393	printf("\n\n\n");
394	}
395	#endif
396
397	int fec_init(struct eth_device dev, bd_t bd)
398	{
399	struct fec_info_s *info = dev->priv;
400	volatile fec_t fecp = (fec_t ) (info->iobase);
401	int i;
d3f87148	402	uchar ea[6];
8e585f02 TL	403
	404	fecpin_setclear(dev, 1);
	405
	406	fec_reset(dev);
	407
ab77bc54	408	#if defined(CONFIG_CMD_MII) \|\| defined (CONFIG_MII) \|\| \
6d0f6bcf	409	defined (CONFIG_SYS_DISCOVER_PHY)
8e585f02 TL	410
	411	mii_init();
	412
	413	setFecDuplexSpeed(fecp, bd, info->dup_spd);
	414	#else
6d0f6bcf	415	#ifndef CONFIG_SYS_DISCOVER_PHY
8e585f02	416	setFecDuplexSpeed(fecp, bd, (FECDUPLEX << 16) \| FECSPEED);
6d0f6bcf	417	#endif /* ifndef CONFIG_SYS_DISCOVER_PHY */
ab77bc54	418	#endif /* CONFIG_CMD_MII \|\| CONFIG_MII */
8e585f02 TL	419
	420	/* We use strictly polling mode only */
	421	fecp->eimr = 0;
	422
	423	/* Clear any pending interrupt */
	424	fecp->eir = 0xffffffff;
	425
	426	/* Set station address */
6d0f6bcf JCPV	427	if ((u32) fecp == CONFIG_SYS_FEC0_IOBASE) {
	428	#ifdef CONFIG_SYS_FEC1_IOBASE
	429	volatile fec_t fecp1 = (fec_t ) (CONFIG_SYS_FEC1_IOBASE);
35affd7a	430	eth_env_get_enetaddr("eth1addr", ea);
8ae158cd TL	431	fecp1->palr =
	432	(ea[0] << 24) \| (ea[1] << 16) \| (ea[2] << 8) \| (ea[3]);
	433	fecp1->paur = (ea[4] << 24) \| (ea[5] << 16);
	434	#endif
35affd7a	435	eth_env_get_enetaddr("ethaddr", ea);
8ae158cd TL	436	fecp->palr =
	437	(ea[0] << 24) \| (ea[1] << 16) \| (ea[2] << 8) \| (ea[3]);
	438	fecp->paur = (ea[4] << 24) \| (ea[5] << 16);
8e585f02	439	} else {
6d0f6bcf JCPV	440	#ifdef CONFIG_SYS_FEC0_IOBASE
6d0f6bcf JCPV	441	volatile fec_t fecp0 = (fec_t ) (CONFIG_SYS_FEC0_IOBASE);
35affd7a	442	eth_env_get_enetaddr("ethaddr", ea);
8ae158cd TL	443	fecp0->palr =
	444	(ea[0] << 24) \| (ea[1] << 16) \| (ea[2] << 8) \| (ea[3]);
	445	fecp0->paur = (ea[4] << 24) \| (ea[5] << 16);
	446	#endif
6d0f6bcf	447	#ifdef CONFIG_SYS_FEC1_IOBASE
35affd7a	448	eth_env_get_enetaddr("eth1addr", ea);
8ae158cd TL	449	fecp->palr =
	450	(ea[0] << 24) \| (ea[1] << 16) \| (ea[2] << 8) \| (ea[3]);
	451	fecp->paur = (ea[4] << 24) \| (ea[5] << 16);
8e585f02 TL	452	#endif
	453	}
	454
8e585f02 TL	455	/* Clear unicast address hash table */
	456	fecp->iaur = 0;
	457	fecp->ialr = 0;
	458
	459	/* Clear multicast address hash table */
	460	fecp->gaur = 0;
	461	fecp->galr = 0;
	462
	463	/* Set maximum receive buffer size. */
	464	fecp->emrbr = PKT_MAXBLR_SIZE;
	465
	466	/*
e4691564	467	* Setup Buffers and Buffer Descriptors
8e585f02 TL	468	*/
	469	info->rxIdx = 0;
	470	info->txIdx = 0;
	471
	472	/*
	473	* Setup Receiver Buffer Descriptors (13.14.24.18)
	474	* Settings:
	475	* Empty, Wrap
	476	*/
	477	for (i = 0; i < PKTBUFSRX; i++) {
	478	info->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
	479	info->rxbd[i].cbd_datlen = 0; /* Reset */
1fd92db8	480	info->rxbd[i].cbd_bufaddr = (uint) net_rx_packets[i];
8e585f02 TL	481	}
	482	info->rxbd[PKTBUFSRX - 1].cbd_sc \|= BD_ENET_RX_WRAP;
	483
	484	/*
	485	* Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
	486	* Settings:
	487	* Last, Tx CRC
	488	*/
	489	for (i = 0; i < TX_BUF_CNT; i++) {
	490	info->txbd[i].cbd_sc = BD_ENET_TX_LAST \| BD_ENET_TX_TC;
	491	info->txbd[i].cbd_datlen = 0; /* Reset */
	492	info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]);
	493	}
	494	info->txbd[TX_BUF_CNT - 1].cbd_sc \|= BD_ENET_TX_WRAP;
	495
	496	/* Set receive and transmit descriptor base */
	497	fecp->erdsr = (unsigned int)(&info->rxbd[0]);
	498	fecp->etdsr = (unsigned int)(&info->txbd[0]);
	499
	500	/* Now enable the transmit and receive processing */
	501	fecp->ecr \|= FEC_ECR_ETHER_EN;
	502
	503	/* And last, try to fill Rx Buffer Descriptors */
	504	fecp->rdar = 0x01000000; /* Descriptor polling active */
	505
	506	return 1;
	507	}
	508
	509	void fec_reset(struct eth_device *dev)
	510	{
	511	struct fec_info_s *info = dev->priv;
	512	volatile fec_t fecp = (fec_t ) (info->iobase);
	513	int i;
	514
	515	fecp->ecr = FEC_ECR_RESET;
	516	for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
	517	udelay(1);
	518	}
	519	if (i == FEC_RESET_DELAY) {
	520	printf("FEC_RESET_DELAY timeout\n");
	521	}
	522	}
	523
	524	void fec_halt(struct eth_device *dev)
	525	{
	526	struct fec_info_s *info = dev->priv;
	527
	528	fec_reset(dev);
	529
	530	fecpin_setclear(dev, 0);
	531
	532	info->rxIdx = info->txIdx = 0;
	533	memset(info->rxbd, 0, PKTBUFSRX * sizeof(cbd_t));
	534	memset(info->txbd, 0, TX_BUF_CNT * sizeof(cbd_t));
	535	memset(info->txbuf, 0, DBUF_LENGTH);
	536	}
	537
	538	int mcffec_initialize(bd_t * bis)
	539	{
	540	struct eth_device *dev;
	541	int i;
6d0f6bcf JCPV	542	#ifdef CONFIG_SYS_FEC_BUF_USE_SRAM
6d0f6bcf JCPV	543	u32 tmp = CONFIG_SYS_INIT_RAM_ADDR + 0x1000;
1803f7f9	544	#endif
8e585f02	545
a62cd29c	546	for (i = 0; i < ARRAY_SIZE(fec_info); i++) {
8e585f02	547
f2208fbc	548	dev =
6d0f6bcf	549	(struct eth_device *)memalign(CONFIG_SYS_CACHELINE_SIZE,
f2208fbc	550	sizeof *dev);
8e585f02 TL	551	if (dev == NULL)
	552	hang();
	553
	554	memset(dev, 0, sizeof(*dev));
	555
	556	sprintf(dev->name, "FEC%d", fec_info[i].index);
	557
	558	dev->priv = &fec_info[i];
	559	dev->init = fec_init;
	560	dev->halt = fec_halt;
	561	dev->send = fec_send;
	562	dev->recv = fec_recv;
	563
	564	/* setup Receive and Transmit buffer descriptor */
6d0f6bcf	565	#ifdef CONFIG_SYS_FEC_BUF_USE_SRAM
1803f7f9 TL	566	fec_info[i].rxbd = (cbd_t *)((u32)fec_info[i].rxbd + tmp);
	567	tmp = (u32)fec_info[i].rxbd;
	568	fec_info[i].txbd =
	569	(cbd_t *)((u32)fec_info[i].txbd + tmp +
	570	(PKTBUFSRX * sizeof(cbd_t)));
	571	tmp = (u32)fec_info[i].txbd;
	572	fec_info[i].txbuf =
	573	(char *)((u32)fec_info[i].txbuf + tmp +
6d0f6bcf	574	(CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
1803f7f9 TL	575	tmp = (u32)fec_info[i].txbuf;
1803f7f9 TL	576	#else
8e585f02	577	fec_info[i].rxbd =
6d0f6bcf	578	(cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE,
f2208fbc	579	(PKTBUFSRX * sizeof(cbd_t)));
8e585f02	580	fec_info[i].txbd =
6d0f6bcf	581	(cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE,
f2208fbc TL	582	(TX_BUF_CNT * sizeof(cbd_t)));
f2208fbc TL	583	fec_info[i].txbuf =
6d0f6bcf	584	(char *)memalign(CONFIG_SYS_CACHELINE_SIZE, DBUF_LENGTH);
1803f7f9 TL	585	#endif
1803f7f9 TL	586
8e585f02 TL	587	#ifdef ET_DEBUG
	588	printf("rxbd %x txbd %x\n",
	589	(int)fec_info[i].rxbd, (int)fec_info[i].txbd);
	590	#endif
	591
6d0f6bcf	592	fec_info[i].phy_name = (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, 32);
8e585f02 TL	593
	594	eth_register(dev);
	595
ab77bc54	596	#if defined(CONFIG_MII) \|\| defined(CONFIG_CMD_MII)
5a49f174 JH	597	int retval;
	598	struct mii_dev *mdiodev = mdio_alloc();
	599	if (!mdiodev)
	600	return -ENOMEM;
	601	strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
	602	mdiodev->read = mcffec_miiphy_read;
	603	mdiodev->write = mcffec_miiphy_write;
	604
	605	retval = mdio_register(mdiodev);
	606	if (retval < 0)
	607	return retval;
8e585f02	608	#endif
1803f7f9 TL	609	if (i > 0)
1803f7f9 TL	610	fec_info[i - 1].next = &fec_info[i];
8e585f02	611	}
1803f7f9	612	fec_info[i - 1].next = &fec_info[0];
8e585f02 TL	613
	614	/* default speed */
	615	bis->bi_ethspeed = 10;
	616
86882b80	617	return 0;
8e585f02	618	}