[J-u-boot.git] / drivers / net / pcnet.c

/*
 * (C) Copyright 2002 Wolfgang Grandegger, [email protected].
 *
 * This driver for AMD PCnet network controllers is derived from the
 * Linux driver pcnet32.c written 1996-1999 by Thomas Bogendoerfer.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <malloc.h>
#include <net.h>
#include <asm/io.h>
#include <pci.h>

#if 0
#define	PCNET_DEBUG_LEVEL	0	/* 0=off, 1=init, 2=rx/tx */
#endif

#if PCNET_DEBUG_LEVEL > 0
#define	PCNET_DEBUG1(fmt,args...)	printf (fmt ,##args)
#if PCNET_DEBUG_LEVEL > 1
#define	PCNET_DEBUG2(fmt,args...)	printf (fmt ,##args)
#else
#define PCNET_DEBUG2(fmt,args...)
#endif
#else
#define PCNET_DEBUG1(fmt,args...)
#define PCNET_DEBUG2(fmt,args...)
#endif

#if defined(CONFIG_CMD_NET) \
	&& defined(CONFIG_NET_MULTI) && defined(CONFIG_PCNET)

#if !defined(CONF_PCNET_79C973) && defined(CONF_PCNET_79C975)
#error "Macro for PCnet chip version is not defined!"
#endif

/*
 * Set the number of Tx and Rx buffers, using Log_2(# buffers).
 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
 */
#define PCNET_LOG_TX_BUFFERS	0
#define PCNET_LOG_RX_BUFFERS	2

#define TX_RING_SIZE		(1 << (PCNET_LOG_TX_BUFFERS))
#define TX_RING_LEN_BITS	((PCNET_LOG_TX_BUFFERS) << 12)

#define RX_RING_SIZE		(1 << (PCNET_LOG_RX_BUFFERS))
#define RX_RING_LEN_BITS	((PCNET_LOG_RX_BUFFERS) << 4)

#define PKT_BUF_SZ		1544

/* The PCNET Rx and Tx ring descriptors. */
struct pcnet_rx_head {
	u32 base;
	s16 buf_length;
	s16 status;
	u32 msg_length;
	u32 reserved;
};

struct pcnet_tx_head {
	u32 base;
	s16 length;
	s16 status;
	u32 misc;
	u32 reserved;
};

/* The PCNET 32-Bit initialization block, described in databook. */
struct pcnet_init_block {
	u16 mode;
	u16 tlen_rlen;
	u8 phys_addr[6];
	u16 reserved;
	u32 filter[2];
	/* Receive and transmit ring base, along with extra bits. */
	u32 rx_ring;
	u32 tx_ring;
	u32 reserved2;
};

typedef struct pcnet_priv {
	struct pcnet_rx_head rx_ring[RX_RING_SIZE];
	struct pcnet_tx_head tx_ring[TX_RING_SIZE];
	struct pcnet_init_block init_block;
	/* Receive Buffer space */
	unsigned char rx_buf[RX_RING_SIZE][PKT_BUF_SZ + 4];
	int cur_rx;
	int cur_tx;
} pcnet_priv_t;

static pcnet_priv_t *lp;

/* Offsets from base I/O address for WIO mode */
#define PCNET_RDP		0x10
#define PCNET_RAP		0x12
#define PCNET_RESET		0x14
#define PCNET_BDP		0x16

static u16 pcnet_read_csr (struct eth_device *dev, int index)
{
	outw (index, dev->iobase + PCNET_RAP);
	return inw (dev->iobase + PCNET_RDP);
}

static void pcnet_write_csr (struct eth_device *dev, int index, u16 val)
{
	outw (index, dev->iobase + PCNET_RAP);
	outw (val, dev->iobase + PCNET_RDP);
}

static u16 pcnet_read_bcr (struct eth_device *dev, int index)
{
	outw (index, dev->iobase + PCNET_RAP);
	return inw (dev->iobase + PCNET_BDP);
}

static void pcnet_write_bcr (struct eth_device *dev, int index, u16 val)
{
	outw (index, dev->iobase + PCNET_RAP);
	outw (val, dev->iobase + PCNET_BDP);
}

static void pcnet_reset (struct eth_device *dev)
{
	inw (dev->iobase + PCNET_RESET);
}

static int pcnet_check (struct eth_device *dev)
{
	outw (88, dev->iobase + PCNET_RAP);
	return (inw (dev->iobase + PCNET_RAP) == 88);
}

static int pcnet_init (struct eth_device *dev, bd_t * bis);
static int pcnet_send (struct eth_device *dev, volatile void *packet,
		       int length);
static int pcnet_recv (struct eth_device *dev);
static void pcnet_halt (struct eth_device *dev);
static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_num);

#define PCI_TO_MEM(d,a) pci_phys_to_mem((pci_dev_t)d->priv, (u_long)(a))
#define PCI_TO_MEM_LE(d,a) (u32)(cpu_to_le32(PCI_TO_MEM(d,a)))

static struct pci_device_id supported[] = {
	{PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE},
	{}
};


int pcnet_initialize (bd_t * bis)
{
<<<<<<< HEAD:drivers/net/pcnet.c
	pci_dev_t devbusfn;
	struct eth_device *dev;
	u16 command, status;
	int dev_nr = 0;

	PCNET_DEBUG1 ("\npcnet_initialize...\n");

	for (dev_nr = 0;; dev_nr++) {

		/*
		 * Find the PCnet PCI device(s).
		 */
		if ((devbusfn = pci_find_devices (supported, dev_nr)) < 0) {
			break;
		}

		/*
		 * Allocate and pre-fill the device structure.
		 */
		dev = (struct eth_device *) malloc (sizeof *dev);
		dev->priv = (void *) devbusfn;
		sprintf (dev->name, "pcnet#%d", dev_nr);

		/*
		 * Setup the PCI device.
		 */
		pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0,
				       (unsigned int *) &dev->iobase);
		dev->iobase=pci_io_to_phys (devbusfn, dev->iobase);
		dev->iobase &= ~0xf;

		PCNET_DEBUG1 ("%s: devbusfn=0x%x iobase=0x%x: ",
			      dev->name, devbusfn, dev->iobase);

		command = PCI_COMMAND_IO | PCI_COMMAND_MASTER;
		pci_write_config_word (devbusfn, PCI_COMMAND, command);
		pci_read_config_word (devbusfn, PCI_COMMAND, &status);
		if ((status & command) != command) {
			printf ("%s: Couldn't enable IO access or Bus Mastering\n", dev->name);
			free (dev);
			continue;
		}

		pci_write_config_byte (devbusfn, PCI_LATENCY_TIMER, 0x40);

		/*
		 * Probe the PCnet chip.
		 */
		if (pcnet_probe (dev, bis, dev_nr) < 0) {
			free (dev);
			continue;
		}

		/*
		 * Setup device structure and register the driver.
		 */
		dev->init = pcnet_init;
		dev->halt = pcnet_halt;
		dev->send = pcnet_send;
		dev->recv = pcnet_recv;

		eth_register (dev);
=======
    pci_dev_t devbusfn;
    struct eth_device* dev;
    u16 command, status;
    int dev_nr = 0;

    PCNET_DEBUG1("\npcnet_initialize...\n");

    for (dev_nr = 0; ; dev_nr++) {

	/*
	 * Find the PCnet PCI device(s).
	 */
	if ((devbusfn = pci_find_devices(supported, dev_nr)) < 0) {
	    break;
	}

	/*
	 * Allocate and pre-fill the device structure.
	 */
	dev = (struct eth_device*) malloc(sizeof *dev);
	dev->priv = (void *)devbusfn;
	sprintf(dev->name, "pcnet#%d", dev_nr);

	/*
	 * Setup the PCI device.
	 */
	pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, (unsigned int *)&dev->iobase);
	dev->iobase=pci_io_to_phys(devbusfn,dev->iobase);
	dev->iobase &= ~0xf;

	PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%x: ",
	       dev->name, devbusfn, dev->iobase);

	command = PCI_COMMAND_IO | PCI_COMMAND_MASTER;
	pci_write_config_word(devbusfn, PCI_COMMAND, command);
	pci_read_config_word(devbusfn, PCI_COMMAND, &status);
	if ((status & command) != command) {
	    printf("%s: Couldn't enable IO access or Bus Mastering\n",
		   dev->name);
	    free(dev);
	    continue;
	}

	pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x40);

	/*
	 * Probe the PCnet chip.
	 */
	if (pcnet_probe(dev, bis, dev_nr) < 0) {
	    free(dev);
	    continue;
>>>>>>> Fixed pcnet io_base:drivers/net/pcnet.c
	}

	udelay (10 * 1000);

	return dev_nr;
}

static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_nr)
{
	int chip_version;
	char *chipname;

#ifdef PCNET_HAS_PROM
	int i;
#endif

	/* Reset the PCnet controller */
	pcnet_reset (dev);

	/* Check if register access is working */
	if (pcnet_read_csr (dev, 0) != 4 || !pcnet_check (dev)) {
		printf ("%s: CSR register access check failed\n", dev->name);
		return -1;
	}

	/* Identify the chip */
	chip_version =
		pcnet_read_csr (dev, 88) | (pcnet_read_csr (dev, 89) << 16);
	if ((chip_version & 0xfff) != 0x003)
		return -1;
	chip_version = (chip_version >> 12) & 0xffff;
	switch (chip_version) {
	case 0x2621:
		chipname = "PCnet/PCI II 79C970A";	/* PCI */
		break;
#ifdef CONFIG_PCNET_79C973
	case 0x2625:
		chipname = "PCnet/FAST III 79C973";	/* PCI */
		break;
#endif
#ifdef CONFIG_PCNET_79C975
	case 0x2627:
		chipname = "PCnet/FAST III 79C975";	/* PCI */
		break;
#endif
	default:
		printf ("%s: PCnet version %#x not supported\n",
			dev->name, chip_version);
		return -1;
	}

	PCNET_DEBUG1 ("AMD %s\n", chipname);

#ifdef PCNET_HAS_PROM
	/*
	 * In most chips, after a chip reset, the ethernet address is read from
	 * the station address PROM at the base address and programmed into the
	 * "Physical Address Registers" CSR12-14.
	 */
	for (i = 0; i < 3; i++) {
		unsigned int val;

		val = pcnet_read_csr (dev, i + 12) & 0x0ffff;
		/* There may be endianness issues here. */
		dev->enetaddr[2 * i] = val & 0x0ff;
		dev->enetaddr[2 * i + 1] = (val >> 8) & 0x0ff;
	}
#endif /* PCNET_HAS_PROM */

	return 0;
}

static int pcnet_init (struct eth_device *dev, bd_t * bis)
{
	int i, val;
	u32 addr;

	PCNET_DEBUG1 ("%s: pcnet_init...\n", dev->name);

	/* Switch pcnet to 32bit mode */
	pcnet_write_bcr (dev, 20, 2);

#ifdef CONFIG_PN62
	/* Setup LED registers */
	val = pcnet_read_bcr (dev, 2) | 0x1000;
	pcnet_write_bcr (dev, 2, val);	/* enable LEDPE */
	pcnet_write_bcr (dev, 4, 0x5080);	/* 100MBit */
	pcnet_write_bcr (dev, 5, 0x40c0);	/* LNKSE */
	pcnet_write_bcr (dev, 6, 0x4090);	/* TX Activity */
	pcnet_write_bcr (dev, 7, 0x4084);	/* RX Activity */
#endif

	/* Set/reset autoselect bit */
	val = pcnet_read_bcr (dev, 2) & ~2;
	val |= 2;
	pcnet_write_bcr (dev, 2, val);

	/* Enable auto negotiate, setup, disable fd */
	val = pcnet_read_bcr (dev, 32) & ~0x98;
	val |= 0x20;
	pcnet_write_bcr (dev, 32, val);

	/*
	 * We only maintain one structure because the drivers will never
	 * be used concurrently. In 32bit mode the RX and TX ring entries
	 * must be aligned on 16-byte boundaries.
	 */
	if (lp == NULL) {
		addr = (u32) malloc (sizeof (pcnet_priv_t) + 0x10);
		addr = (addr + 0xf) & ~0xf;
		lp = (pcnet_priv_t *) addr;
	}

	lp->init_block.mode = cpu_to_le16 (0x0000);
	lp->init_block.filter[0] = 0x00000000;
	lp->init_block.filter[1] = 0x00000000;

	/*
	 * Initialize the Rx ring.
	 */
	lp->cur_rx = 0;
	for (i = 0; i < RX_RING_SIZE; i++) {
		lp->rx_ring[i].base = PCI_TO_MEM_LE (dev, lp->rx_buf[i]);
		lp->rx_ring[i].buf_length = cpu_to_le16 (-PKT_BUF_SZ);
		lp->rx_ring[i].status = cpu_to_le16 (0x8000);
		PCNET_DEBUG1
			("Rx%d: base=0x%x buf_length=0x%hx status=0x%hx\n", i,
			 lp->rx_ring[i].base, lp->rx_ring[i].buf_length,
			 lp->rx_ring[i].status);
	}

	/*
	 * Initialize the Tx ring. The Tx buffer address is filled in as
	 * needed, but we do need to clear the upper ownership bit.
	 */
	lp->cur_tx = 0;
	for (i = 0; i < TX_RING_SIZE; i++) {
		lp->tx_ring[i].base = 0;
		lp->tx_ring[i].status = 0;
	}

	/*
	 * Setup Init Block.
	 */
	PCNET_DEBUG1 ("Init block at 0x%p: MAC", &lp->init_block);

	for (i = 0; i < 6; i++) {
		lp->init_block.phys_addr[i] = dev->enetaddr[i];
		PCNET_DEBUG1 (" %02x", lp->init_block.phys_addr[i]);
	}

	lp->init_block.tlen_rlen = cpu_to_le16 (TX_RING_LEN_BITS |
						RX_RING_LEN_BITS);
	lp->init_block.rx_ring = PCI_TO_MEM_LE (dev, lp->rx_ring);
	lp->init_block.tx_ring = PCI_TO_MEM_LE (dev, lp->tx_ring);

	PCNET_DEBUG1 ("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n",
		      lp->init_block.tlen_rlen,
		      lp->init_block.rx_ring, lp->init_block.tx_ring);

	/*
	 * Tell the controller where the Init Block is located.
	 */
	addr = PCI_TO_MEM (dev, &lp->init_block);
	pcnet_write_csr (dev, 1, addr & 0xffff);
	pcnet_write_csr (dev, 2, (addr >> 16) & 0xffff);

	pcnet_write_csr (dev, 4, 0x0915);
	pcnet_write_csr (dev, 0, 0x0001);	/* start */

	/* Wait for Init Done bit */
	for (i = 10000; i > 0; i--) {
		if (pcnet_read_csr (dev, 0) & 0x0100)
			break;
		udelay (10);
	}
	if (i <= 0) {
		printf ("%s: TIMEOUT: controller init failed\n", dev->name);
		pcnet_reset (dev);
		return -1;
	}

	/*
	 * Finally start network controller operation.
	 */
	pcnet_write_csr (dev, 0, 0x0002);

	return 0;
}

static int pcnet_send (struct eth_device *dev, volatile void *packet,
		       int pkt_len)
{
	int i, status;
	struct pcnet_tx_head *entry = &lp->tx_ring[lp->cur_tx];

	PCNET_DEBUG2 ("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len,
		      packet);

	/* Wait for completion by testing the OWN bit */
	for (i = 1000; i > 0; i--) {
		status = le16_to_cpu (entry->status);
		if ((status & 0x8000) == 0)
			break;
		udelay (100);
		PCNET_DEBUG2 (".");
	}
	if (i <= 0) {
		printf ("%s: TIMEOUT: Tx%d failed (status = 0x%x)\n",
			dev->name, lp->cur_tx, status);
		pkt_len = 0;
		goto failure;
	}

	/*
	 * Setup Tx ring. Caution: the write order is important here,
	 * set the status with the "ownership" bits last.
	 */
	status = 0x8300;
	entry->length = le16_to_cpu (-pkt_len);
	entry->misc = 0x00000000;
	entry->base = PCI_TO_MEM_LE (dev, packet);
	entry->status = le16_to_cpu (status);

	/* Trigger an immediate send poll. */
	pcnet_write_csr (dev, 0, 0x0008);

      failure:
	if (++lp->cur_tx >= TX_RING_SIZE)
		lp->cur_tx = 0;

	PCNET_DEBUG2 ("done\n");
	return pkt_len;
}

static int pcnet_recv (struct eth_device *dev)
{
	struct pcnet_rx_head *entry;
	int pkt_len = 0;
	u16 status;

	while (1) {
		entry = &lp->rx_ring[lp->cur_rx];
		/*
		 * If we own the next entry, it's a new packet. Send it up.
		 */
		if (((status = le16_to_cpu (entry->status)) & 0x8000) != 0) {
			break;
		}
		status >>= 8;

		if (status != 0x03) {	/* There was an error. */

			printf ("%s: Rx%d", dev->name, lp->cur_rx);
			PCNET_DEBUG1 (" (status=0x%x)", status);
			if (status & 0x20)
				printf (" Frame");
			if (status & 0x10)
				printf (" Overflow");
			if (status & 0x08)
				printf (" CRC");
			if (status & 0x04)
				printf (" Fifo");
			printf (" Error\n");
			entry->status &= le16_to_cpu (0x03ff);

		} else {

			pkt_len =
				(le32_to_cpu (entry->msg_length) & 0xfff) - 4;
			if (pkt_len < 60) {
				printf ("%s: Rx%d: invalid packet length %d\n", dev->name, lp->cur_rx, pkt_len);
			} else {
				NetReceive (lp->rx_buf[lp->cur_rx], pkt_len);
				PCNET_DEBUG2 ("Rx%d: %d bytes from 0x%p\n",
					      lp->cur_rx, pkt_len,
					      lp->rx_buf[lp->cur_rx]);
			}
		}
		entry->status |= cpu_to_le16 (0x8000);

		if (++lp->cur_rx >= RX_RING_SIZE)
			lp->cur_rx = 0;
	}
	return pkt_len;
}

static void pcnet_halt (struct eth_device *dev)
{
	int i;

	PCNET_DEBUG1 ("%s: pcnet_halt...\n", dev->name);

	/* Reset the PCnet controller */
	pcnet_reset (dev);

	/* Wait for Stop bit */
	for (i = 1000; i > 0; i--) {
		if (pcnet_read_csr (dev, 0) & 0x4)
			break;
		udelay (10);
	}
	if (i <= 0) {
		printf ("%s: TIMEOUT: controller reset failed\n", dev->name);
	}
}
#endif
Commit	Line	Data
c609719b WD	1	/*
	2	* (C) Copyright 2002 Wolfgang Grandegger, [email protected].
	3	*
	4	* This driver for AMD PCnet network controllers is derived from the
	5	* Linux driver pcnet32.c written 1996-1999 by Thomas Bogendoerfer.
	6	*
	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*/
	25
	26	#include <common.h>
	27	#include <malloc.h>
	28	#include <net.h>
	29	#include <asm/io.h>
	30	#include <pci.h>
	31
	32	#if 0
11ea26fd	33	#define PCNET_DEBUG_LEVEL 0 /* 0=off, 1=init, 2=rx/tx */
c609719b WD	34	#endif
	35
	36	#if PCNET_DEBUG_LEVEL > 0
39539887	37	#define PCNET_DEBUG1(fmt,args...) printf (fmt ,##args)
c609719b	38	#if PCNET_DEBUG_LEVEL > 1
39539887	39	#define PCNET_DEBUG2(fmt,args...) printf (fmt ,##args)
c609719b	40	#else
39539887	41	#define PCNET_DEBUG2(fmt,args...)
c609719b WD	42	#endif
c609719b WD	43	#else
39539887 WD	44	#define PCNET_DEBUG1(fmt,args...)
39539887 WD	45	#define PCNET_DEBUG2(fmt,args...)
c609719b WD	46	#endif
c609719b WD	47
cb51c0bf	48	#if defined(CONFIG_CMD_NET) \
d5be43de	49	&& defined(CONFIG_NET_MULTI) && defined(CONFIG_PCNET)
c609719b WD	50
	51	#if !defined(CONF_PCNET_79C973) && defined(CONF_PCNET_79C975)
	52	#error "Macro for PCnet chip version is not defined!"
	53	#endif
	54
	55	/*
	56	* Set the number of Tx and Rx buffers, using Log_2(# buffers).
	57	* Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
	58	* That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
	59	*/
	60	#define PCNET_LOG_TX_BUFFERS 0
	61	#define PCNET_LOG_RX_BUFFERS 2
	62
	63	#define TX_RING_SIZE (1 << (PCNET_LOG_TX_BUFFERS))
	64	#define TX_RING_LEN_BITS ((PCNET_LOG_TX_BUFFERS) << 12)
	65
	66	#define RX_RING_SIZE (1 << (PCNET_LOG_RX_BUFFERS))
	67	#define RX_RING_LEN_BITS ((PCNET_LOG_RX_BUFFERS) << 4)
	68
	69	#define PKT_BUF_SZ 1544
	70
	71	/* The PCNET Rx and Tx ring descriptors. */
	72	struct pcnet_rx_head {
11ea26fd WD	73	u32 base;
	74	s16 buf_length;
	75	s16 status;
	76	u32 msg_length;
	77	u32 reserved;
c609719b WD	78	};
	79
	80	struct pcnet_tx_head {
11ea26fd WD	81	u32 base;
	82	s16 length;
	83	s16 status;
	84	u32 misc;
	85	u32 reserved;
c609719b WD	86	};
	87
	88	/* The PCNET 32-Bit initialization block, described in databook. */
	89	struct pcnet_init_block {
11ea26fd WD	90	u16 mode;
	91	u16 tlen_rlen;
	92	u8 phys_addr[6];
	93	u16 reserved;
	94	u32 filter[2];
	95	/* Receive and transmit ring base, along with extra bits. */
	96	u32 rx_ring;
	97	u32 tx_ring;
	98	u32 reserved2;
c609719b WD	99	};
	100
	101	typedef struct pcnet_priv {
11ea26fd WD	102	struct pcnet_rx_head rx_ring[RX_RING_SIZE];
	103	struct pcnet_tx_head tx_ring[TX_RING_SIZE];
	104	struct pcnet_init_block init_block;
	105	/* Receive Buffer space */
	106	unsigned char rx_buf[RX_RING_SIZE][PKT_BUF_SZ + 4];
	107	int cur_rx;
	108	int cur_tx;
c609719b WD	109	} pcnet_priv_t;
	110
	111	static pcnet_priv_t *lp;
	112
	113	/* Offsets from base I/O address for WIO mode */
	114	#define PCNET_RDP 0x10
	115	#define PCNET_RAP 0x12
	116	#define PCNET_RESET 0x14
	117	#define PCNET_BDP 0x16
	118
	119	static u16 pcnet_read_csr (struct eth_device *dev, int index)
	120	{
11ea26fd WD	121	outw (index, dev->iobase + PCNET_RAP);
11ea26fd WD	122	return inw (dev->iobase + PCNET_RDP);
c609719b WD	123	}
	124
	125	static void pcnet_write_csr (struct eth_device *dev, int index, u16 val)
	126	{
11ea26fd WD	127	outw (index, dev->iobase + PCNET_RAP);
11ea26fd WD	128	outw (val, dev->iobase + PCNET_RDP);
c609719b WD	129	}
	130
	131	static u16 pcnet_read_bcr (struct eth_device *dev, int index)
	132	{
11ea26fd WD	133	outw (index, dev->iobase + PCNET_RAP);
11ea26fd WD	134	return inw (dev->iobase + PCNET_BDP);
c609719b WD	135	}
	136
	137	static void pcnet_write_bcr (struct eth_device *dev, int index, u16 val)
	138	{
11ea26fd WD	139	outw (index, dev->iobase + PCNET_RAP);
11ea26fd WD	140	outw (val, dev->iobase + PCNET_BDP);
c609719b WD	141	}
	142
	143	static void pcnet_reset (struct eth_device *dev)
	144	{
11ea26fd	145	inw (dev->iobase + PCNET_RESET);
c609719b WD	146	}
	147
	148	static int pcnet_check (struct eth_device *dev)
	149	{
11ea26fd WD	150	outw (88, dev->iobase + PCNET_RAP);
11ea26fd WD	151	return (inw (dev->iobase + PCNET_RAP) == 88);
c609719b WD	152	}
c609719b WD	153
11ea26fd WD	154	static int pcnet_init (struct eth_device dev, bd_t bis);
	155	static int pcnet_send (struct eth_device dev, volatile void packet,
	156	int length);
	157	static int pcnet_recv (struct eth_device *dev);
	158	static void pcnet_halt (struct eth_device *dev);
	159	static int pcnet_probe (struct eth_device dev, bd_t bis, int dev_num);
c609719b WD	160
	161	#define PCI_TO_MEM(d,a) pci_phys_to_mem((pci_dev_t)d->priv, (u_long)(a))
	162	#define PCI_TO_MEM_LE(d,a) (u32)(cpu_to_le32(PCI_TO_MEM(d,a)))
	163
	164	static struct pci_device_id supported[] = {
11ea26fd WD	165	{PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE},
11ea26fd WD	166	{}
c609719b WD	167	};
	168
	169
11ea26fd	170	int pcnet_initialize (bd_t * bis)
c609719b	171	{
38656319	172	<<<<<<< HEAD:drivers/net/pcnet.c
11ea26fd WD	173	pci_dev_t devbusfn;
	174	struct eth_device *dev;
	175	u16 command, status;
	176	int dev_nr = 0;
	177
	178	PCNET_DEBUG1 ("\npcnet_initialize...\n");
	179
	180	for (dev_nr = 0;; dev_nr++) {
	181
	182	/*
	183	* Find the PCnet PCI device(s).
	184	*/
	185	if ((devbusfn = pci_find_devices (supported, dev_nr)) < 0) {
	186	break;
	187	}
	188
	189	/*
	190	* Allocate and pre-fill the device structure.
	191	*/
	192	dev = (struct eth_device ) malloc (sizeof dev);
	193	dev->priv = (void *) devbusfn;
	194	sprintf (dev->name, "pcnet#%d", dev_nr);
	195
	196	/*
	197	* Setup the PCI device.
	198	*/
	199	pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0,
	200	(unsigned int *) &dev->iobase);
38656319	201	dev->iobase=pci_io_to_phys (devbusfn, dev->iobase);
11ea26fd WD	202	dev->iobase &= ~0xf;
	203
	204	PCNET_DEBUG1 ("%s: devbusfn=0x%x iobase=0x%x: ",
	205	dev->name, devbusfn, dev->iobase);
	206
	207	command = PCI_COMMAND_IO \| PCI_COMMAND_MASTER;
	208	pci_write_config_word (devbusfn, PCI_COMMAND, command);
	209	pci_read_config_word (devbusfn, PCI_COMMAND, &status);
	210	if ((status & command) != command) {
	211	printf ("%s: Couldn't enable IO access or Bus Mastering\n", dev->name);
	212	free (dev);
	213	continue;
	214	}
	215
	216	pci_write_config_byte (devbusfn, PCI_LATENCY_TIMER, 0x40);
	217
	218	/*
	219	* Probe the PCnet chip.
	220	*/
	221	if (pcnet_probe (dev, bis, dev_nr) < 0) {
	222	free (dev);
	223	continue;
	224	}
	225
	226	/*
	227	* Setup device structure and register the driver.
	228	*/
	229	dev->init = pcnet_init;
	230	dev->halt = pcnet_halt;
	231	dev->send = pcnet_send;
	232	dev->recv = pcnet_recv;
	233
	234	eth_register (dev);
38656319 VL	235	=======
	236	pci_dev_t devbusfn;
	237	struct eth_device* dev;
	238	u16 command, status;
	239	int dev_nr = 0;
	240
	241	PCNET_DEBUG1("\npcnet_initialize...\n");
	242
	243	for (dev_nr = 0; ; dev_nr++) {
	244
	245	/*
	246	* Find the PCnet PCI device(s).
	247	*/
	248	if ((devbusfn = pci_find_devices(supported, dev_nr)) < 0) {
	249	break;
	250	}
	251
	252	/*
	253	* Allocate and pre-fill the device structure.
	254	*/
	255	dev = (struct eth_device) malloc(sizeof dev);
	256	dev->priv = (void *)devbusfn;
	257	sprintf(dev->name, "pcnet#%d", dev_nr);
	258
	259	/*
	260	* Setup the PCI device.
	261	*/
	262	pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, (unsigned int *)&dev->iobase);
	263	dev->iobase=pci_io_to_phys(devbusfn,dev->iobase);
	264	dev->iobase &= ~0xf;
	265
	266	PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%x: ",
	267	dev->name, devbusfn, dev->iobase);
	268
	269	command = PCI_COMMAND_IO \| PCI_COMMAND_MASTER;
	270	pci_write_config_word(devbusfn, PCI_COMMAND, command);
	271	pci_read_config_word(devbusfn, PCI_COMMAND, &status);
	272	if ((status & command) != command) {
	273	printf("%s: Couldn't enable IO access or Bus Mastering\n",
	274	dev->name);
	275	free(dev);
	276	continue;
	277	}
	278
	279	pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x40);
	280
	281	/*
	282	* Probe the PCnet chip.
	283	*/
	284	if (pcnet_probe(dev, bis, dev_nr) < 0) {
	285	free(dev);
	286	continue;
	287	>>>>>>> Fixed pcnet io_base:drivers/net/pcnet.c
c609719b WD	288	}
c609719b WD	289
11ea26fd	290	udelay (10 * 1000);
c609719b	291
11ea26fd	292	return dev_nr;
c609719b WD	293	}
c609719b WD	294
11ea26fd	295	static int pcnet_probe (struct eth_device dev, bd_t bis, int dev_nr)
c609719b	296	{
11ea26fd WD	297	int chip_version;
	298	char *chipname;
	299
c609719b	300	#ifdef PCNET_HAS_PROM
11ea26fd	301	int i;
c609719b WD	302	#endif
c609719b WD	303
11ea26fd WD	304	/* Reset the PCnet controller */
	305	pcnet_reset (dev);
	306
	307	/* Check if register access is working */
	308	if (pcnet_read_csr (dev, 0) != 4 \|\| !pcnet_check (dev)) {
	309	printf ("%s: CSR register access check failed\n", dev->name);
	310	return -1;
	311	}
	312
	313	/* Identify the chip */
	314	chip_version =
	315	pcnet_read_csr (dev, 88) \| (pcnet_read_csr (dev, 89) << 16);
	316	if ((chip_version & 0xfff) != 0x003)
	317	return -1;
	318	chip_version = (chip_version >> 12) & 0xffff;
	319	switch (chip_version) {
	320	case 0x2621:
	321	chipname = "PCnet/PCI II 79C970A"; /* PCI */
	322	break;
c609719b	323	#ifdef CONFIG_PCNET_79C973
11ea26fd WD	324	case 0x2625:
	325	chipname = "PCnet/FAST III 79C973"; /* PCI */
	326	break;
c609719b WD	327	#endif
c609719b WD	328	#ifdef CONFIG_PCNET_79C975
11ea26fd WD	329	case 0x2627:
	330	chipname = "PCnet/FAST III 79C975"; /* PCI */
	331	break;
c609719b	332	#endif
11ea26fd WD	333	default:
	334	printf ("%s: PCnet version %#x not supported\n",
	335	dev->name, chip_version);
	336	return -1;
	337	}
c609719b	338
11ea26fd	339	PCNET_DEBUG1 ("AMD %s\n", chipname);
c609719b WD	340
c609719b WD	341	#ifdef PCNET_HAS_PROM
11ea26fd WD	342	/*
	343	* In most chips, after a chip reset, the ethernet address is read from
	344	* the station address PROM at the base address and programmed into the
	345	* "Physical Address Registers" CSR12-14.
	346	*/
	347	for (i = 0; i < 3; i++) {
	348	unsigned int val;
	349
	350	val = pcnet_read_csr (dev, i + 12) & 0x0ffff;
	351	/* There may be endianness issues here. */
	352	dev->enetaddr[2 * i] = val & 0x0ff;
	353	dev->enetaddr[2 * i + 1] = (val >> 8) & 0x0ff;
	354	}
c609719b WD	355	#endif /* PCNET_HAS_PROM */
c609719b WD	356
11ea26fd	357	return 0;
c609719b WD	358	}
c609719b WD	359
11ea26fd	360	static int pcnet_init (struct eth_device dev, bd_t bis)
c609719b	361	{
11ea26fd WD	362	int i, val;
11ea26fd WD	363	u32 addr;
c609719b	364
11ea26fd	365	PCNET_DEBUG1 ("%s: pcnet_init...\n", dev->name);
c609719b	366
11ea26fd WD	367	/* Switch pcnet to 32bit mode */
11ea26fd WD	368	pcnet_write_bcr (dev, 20, 2);
c609719b WD	369
c609719b WD	370	#ifdef CONFIG_PN62
11ea26fd WD	371	/* Setup LED registers */
	372	val = pcnet_read_bcr (dev, 2) \| 0x1000;
	373	pcnet_write_bcr (dev, 2, val); /* enable LEDPE */
	374	pcnet_write_bcr (dev, 4, 0x5080); /* 100MBit */
	375	pcnet_write_bcr (dev, 5, 0x40c0); /* LNKSE */
	376	pcnet_write_bcr (dev, 6, 0x4090); /* TX Activity */
	377	pcnet_write_bcr (dev, 7, 0x4084); /* RX Activity */
c609719b WD	378	#endif
c609719b WD	379
11ea26fd WD	380	/* Set/reset autoselect bit */
	381	val = pcnet_read_bcr (dev, 2) & ~2;
	382	val \|= 2;
	383	pcnet_write_bcr (dev, 2, val);
c609719b	384
11ea26fd WD	385	/* Enable auto negotiate, setup, disable fd */
	386	val = pcnet_read_bcr (dev, 32) & ~0x98;
	387	val \|= 0x20;
	388	pcnet_write_bcr (dev, 32, val);
c609719b	389
11ea26fd WD	390	/*
	391	* We only maintain one structure because the drivers will never
	392	* be used concurrently. In 32bit mode the RX and TX ring entries
	393	* must be aligned on 16-byte boundaries.
	394	*/
	395	if (lp == NULL) {
	396	addr = (u32) malloc (sizeof (pcnet_priv_t) + 0x10);
	397	addr = (addr + 0xf) & ~0xf;
	398	lp = (pcnet_priv_t *) addr;
	399	}
c609719b	400
11ea26fd WD	401	lp->init_block.mode = cpu_to_le16 (0x0000);
	402	lp->init_block.filter[0] = 0x00000000;
	403	lp->init_block.filter[1] = 0x00000000;
	404
	405	/*
	406	* Initialize the Rx ring.
	407	*/
	408	lp->cur_rx = 0;
	409	for (i = 0; i < RX_RING_SIZE; i++) {
	410	lp->rx_ring[i].base = PCI_TO_MEM_LE (dev, lp->rx_buf[i]);
	411	lp->rx_ring[i].buf_length = cpu_to_le16 (-PKT_BUF_SZ);
	412	lp->rx_ring[i].status = cpu_to_le16 (0x8000);
	413	PCNET_DEBUG1
	414	("Rx%d: base=0x%x buf_length=0x%hx status=0x%hx\n", i,
	415	lp->rx_ring[i].base, lp->rx_ring[i].buf_length,
	416	lp->rx_ring[i].status);
	417	}
	418
	419	/*
	420	* Initialize the Tx ring. The Tx buffer address is filled in as
	421	* needed, but we do need to clear the upper ownership bit.
	422	*/
c609719b	423	lp->cur_tx = 0;
11ea26fd WD	424	for (i = 0; i < TX_RING_SIZE; i++) {
	425	lp->tx_ring[i].base = 0;
	426	lp->tx_ring[i].status = 0;
	427	}
c609719b	428
11ea26fd WD	429	/*
	430	* Setup Init Block.
	431	*/
	432	PCNET_DEBUG1 ("Init block at 0x%p: MAC", &lp->init_block);
c609719b	433
11ea26fd WD	434	for (i = 0; i < 6; i++) {
	435	lp->init_block.phys_addr[i] = dev->enetaddr[i];
	436	PCNET_DEBUG1 (" %02x", lp->init_block.phys_addr[i]);
	437	}
	438
	439	lp->init_block.tlen_rlen = cpu_to_le16 (TX_RING_LEN_BITS \|
	440	RX_RING_LEN_BITS);
	441	lp->init_block.rx_ring = PCI_TO_MEM_LE (dev, lp->rx_ring);
	442	lp->init_block.tx_ring = PCI_TO_MEM_LE (dev, lp->tx_ring);
	443
	444	PCNET_DEBUG1 ("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n",
	445	lp->init_block.tlen_rlen,
	446	lp->init_block.rx_ring, lp->init_block.tx_ring);
c609719b	447
c609719b	448	/*
11ea26fd	449	* Tell the controller where the Init Block is located.
c609719b	450	*/
11ea26fd WD	451	addr = PCI_TO_MEM (dev, &lp->init_block);
	452	pcnet_write_csr (dev, 1, addr & 0xffff);
	453	pcnet_write_csr (dev, 2, (addr >> 16) & 0xffff);
	454
	455	pcnet_write_csr (dev, 4, 0x0915);
	456	pcnet_write_csr (dev, 0, 0x0001); /* start */
	457
	458	/* Wait for Init Done bit */
	459	for (i = 10000; i > 0; i--) {
	460	if (pcnet_read_csr (dev, 0) & 0x0100)
	461	break;
	462	udelay (10);
c609719b	463	}
11ea26fd WD	464	if (i <= 0) {
	465	printf ("%s: TIMEOUT: controller init failed\n", dev->name);
	466	pcnet_reset (dev);
	467	return -1;
c609719b	468	}
c609719b	469
11ea26fd WD	470	/*
	471	* Finally start network controller operation.
	472	*/
	473	pcnet_write_csr (dev, 0, 0x0002);
	474
	475	return 0;
c609719b WD	476	}
c609719b WD	477
11ea26fd WD	478	static int pcnet_send (struct eth_device dev, volatile void packet,
11ea26fd WD	479	int pkt_len)
c609719b	480	{
11ea26fd WD	481	int i, status;
	482	struct pcnet_tx_head *entry = &lp->tx_ring[lp->cur_tx];
	483
	484	PCNET_DEBUG2 ("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len,
	485	packet);
	486
	487	/* Wait for completion by testing the OWN bit */
	488	for (i = 1000; i > 0; i--) {
	489	status = le16_to_cpu (entry->status);
	490	if ((status & 0x8000) == 0)
	491	break;
	492	udelay (100);
	493	PCNET_DEBUG2 (".");
	494	}
	495	if (i <= 0) {
	496	printf ("%s: TIMEOUT: Tx%d failed (status = 0x%x)\n",
	497	dev->name, lp->cur_tx, status);
	498	pkt_len = 0;
	499	goto failure;
	500	}
	501
	502	/*
	503	* Setup Tx ring. Caution: the write order is important here,
	504	* set the status with the "ownership" bits last.
	505	*/
	506	status = 0x8300;
	507	entry->length = le16_to_cpu (-pkt_len);
	508	entry->misc = 0x00000000;
	509	entry->base = PCI_TO_MEM_LE (dev, packet);
	510	entry->status = le16_to_cpu (status);
	511
	512	/* Trigger an immediate send poll. */
	513	pcnet_write_csr (dev, 0, 0x0008);
	514
	515	failure:
	516	if (++lp->cur_tx >= TX_RING_SIZE)
	517	lp->cur_tx = 0;
	518
	519	PCNET_DEBUG2 ("done\n");
	520	return pkt_len;
	521	}
	522
	523	static int pcnet_recv (struct eth_device *dev)
	524	{
	525	struct pcnet_rx_head *entry;
	526	int pkt_len = 0;
	527	u16 status;
	528
	529	while (1) {
	530	entry = &lp->rx_ring[lp->cur_rx];
	531	/*
	532	* If we own the next entry, it's a new packet. Send it up.
	533	*/
	534	if (((status = le16_to_cpu (entry->status)) & 0x8000) != 0) {
	535	break;
	536	}
	537	status >>= 8;
	538
	539	if (status != 0x03) { /* There was an error. */
	540
	541	printf ("%s: Rx%d", dev->name, lp->cur_rx);
	542	PCNET_DEBUG1 (" (status=0x%x)", status);
	543	if (status & 0x20)
	544	printf (" Frame");
545	if (status & 0x10)
546	printf (" Overflow");
547	if (status & 0x08)
548	printf (" CRC");
549	if (status & 0x04)
550	printf (" Fifo");
551	printf (" Error\n");
552	entry->status &= le16_to_cpu (0x03ff);
553
554	} else {
555
556	pkt_len =
557	(le32_to_cpu (entry->msg_length) & 0xfff) - 4;
558	if (pkt_len < 60) {
559	printf ("%s: Rx%d: invalid packet length %d\n", dev->name, lp->cur_rx, pkt_len);
560	} else {
561	NetReceive (lp->rx_buf[lp->cur_rx], pkt_len);
562	PCNET_DEBUG2 ("Rx%d: %d bytes from 0x%p\n",
563	lp->cur_rx, pkt_len,
564	lp->rx_buf[lp->cur_rx]);
565	}
566	}
567	entry->status \|= cpu_to_le16 (0x8000);
568
569	if (++lp->cur_rx >= RX_RING_SIZE)
570	lp->cur_rx = 0;
571	}
572	return pkt_len;
c609719b WD	573	}
c609719b WD	574
11ea26fd WD	575	static void pcnet_halt (struct eth_device *dev)
	576	{
	577	int i;
	578
	579	PCNET_DEBUG1 ("%s: pcnet_halt...\n", dev->name);
	580
	581	/* Reset the PCnet controller */
	582	pcnet_reset (dev);
	583
	584	/* Wait for Stop bit */
	585	for (i = 1000; i > 0; i--) {
	586	if (pcnet_read_csr (dev, 0) & 0x4)
	587	break;
	588	udelay (10);
	589	}
	590	if (i <= 0) {
	591	printf ("%s: TIMEOUT: controller reset failed\n", dev->name);
	592	}
	593	}
c609719b	594	#endif