[J-u-boot.git] / cpu / mpc83xx / cpu_init.c

/*
 * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <mpc83xx.h>
#include <ioports.h>
#include <asm/io.h>
#ifdef CONFIG_USB_EHCI_FSL
#include <usb/ehci-fsl.h>
#endif

DECLARE_GLOBAL_DATA_PTR;

#ifdef CONFIG_QE
extern qe_iop_conf_t qe_iop_conf_tab[];
extern void qe_config_iopin(u8 port, u8 pin, int dir,
			 int open_drain, int assign);
extern void qe_init(uint qe_base);
extern void qe_reset(void);

static void config_qe_ioports(void)
{
	u8	port, pin;
	int	dir, open_drain, assign;
	int	i;

	for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
		port		= qe_iop_conf_tab[i].port;
		pin		= qe_iop_conf_tab[i].pin;
		dir		= qe_iop_conf_tab[i].dir;
		open_drain	= qe_iop_conf_tab[i].open_drain;
		assign		= qe_iop_conf_tab[i].assign;
		qe_config_iopin(port, pin, dir, open_drain, assign);
	}
}
#endif

/*
 * Breathe some life into the CPU...
 *
 * Set up the memory map,
 * initialize a bunch of registers,
 * initialize the UPM's
 */
void cpu_init_f (volatile immap_t * im)
{
	__be32 acr_mask =
#ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */
		(ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT) |
#endif
#ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */
		(ACR_RPTCNT << ACR_RPTCNT_SHIFT) |
#endif
		0;
	__be32 acr_val =
#ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */
		(CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT) |
#endif
#ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */
		(CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT) |
#endif
		0;
	__be32 spcr_mask =
#ifdef CONFIG_SYS_SPCR_OPT /* Optimize transactions between CSB and other dev */
		(SPCR_OPT << SPCR_OPT_SHIFT) |
#endif
#ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */
		(SPCR_TSECEP << SPCR_TSECEP_SHIFT) |
#endif
#ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */
		(SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT) |
#endif
#ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */
		(SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT) |
#endif
		0;
	__be32 spcr_val =
#ifdef CONFIG_SYS_SPCR_OPT
		(CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT) |
#endif
#ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */
		(CONFIG_SYS_SPCR_TSECEP << SPCR_TSECEP_SHIFT) |
#endif
#ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */
		(CONFIG_SYS_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT) |
#endif
#ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */
		(CONFIG_SYS_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT) |
#endif
		0;
	__be32 sccr_mask =
#ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
		(SCCR_ENCCM << SCCR_ENCCM_SHIFT) |
#endif
#ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
		(SCCR_PCICM << SCCR_PCICM_SHIFT) |
#endif
#ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
		(SCCR_TSECCM << SCCR_TSECCM_SHIFT) |
#endif
#ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
		(SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) |
#endif
#ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
		(SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) |
#endif
#ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
		(SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT) |
#endif
#ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */
		(SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT) |
#endif
#ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
		(SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT) |
#endif
#ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */
		(SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) |
#endif
#ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
		(SCCR_SATACM << SCCR_SATACM_SHIFT) |
#endif
		0;
	__be32 sccr_val =
#ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
		(CONFIG_SYS_SCCR_ENCCM << SCCR_ENCCM_SHIFT) |
#endif
#ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
		(CONFIG_SYS_SCCR_PCICM << SCCR_PCICM_SHIFT) |
#endif
#ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
		(CONFIG_SYS_SCCR_TSECCM << SCCR_TSECCM_SHIFT) |
#endif
#ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
		(CONFIG_SYS_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) |
#endif
#ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
		(CONFIG_SYS_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) |
#endif
#ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
		(CONFIG_SYS_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT) |
#endif
#ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */
		(CONFIG_SYS_SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT) |
#endif
#ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
		(CONFIG_SYS_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT) |
#endif
#ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */
		(CONFIG_SYS_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) |
#endif
#ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
		(CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT) |
#endif
		0;

	/* Pointer is writable since we allocated a register for it */
	gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);

	/* Clear initial global data */
	memset ((void *) gd, 0, sizeof (gd_t));

	/* system performance tweaking */
	clrsetbits_be32(&im->arbiter.acr, acr_mask, acr_val);

	clrsetbits_be32(&im->sysconf.spcr, spcr_mask, spcr_val);

	clrsetbits_be32(&im->clk.sccr, sccr_mask, sccr_val);

	/* RSR - Reset Status Register - clear all status (4.6.1.3) */
	gd->reset_status = __raw_readl(&im->reset.rsr);
	__raw_writel(~(RSR_RES), &im->reset.rsr);

	/* AER - Arbiter Event Register - store status */
	gd->arbiter_event_attributes = __raw_readl(&im->arbiter.aeatr);
	gd->arbiter_event_address = __raw_readl(&im->arbiter.aeadr);

	/*
	 * RMR - Reset Mode Register
	 * contains checkstop reset enable (4.6.1.4)
	 */
	__raw_writel(RMR_CSRE & (1<<RMR_CSRE_SHIFT), &im->reset.rmr);

	/* Enable Time Base & Decrementer ( so we will have udelay() )*/
	setbits_be32(&im->sysconf.spcr, SPCR_TBEN);

	/* System General Purpose Register */
#ifdef CONFIG_SYS_SICRH
#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC8313)
	/* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */
	__raw_writel((im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH,
		     &im->sysconf.sicrh);
#else
	__raw_writel(CONFIG_SYS_SICRH, &im->sysconf.sicrh);
#endif
#endif
#ifdef CONFIG_SYS_SICRL
	__raw_writel(CONFIG_SYS_SICRL, &im->sysconf.sicrl);
#endif
#ifdef CONFIG_SYS_DDRCDR /* DDR control driver register */
	__raw_writel(CONFIG_SYS_DDRCDR, &im->sysconf.ddrcdr);
#endif
#ifdef CONFIG_SYS_OBIR /* Output buffer impedance register */
	__raw_writel(CONFIG_SYS_OBIR, &im->sysconf.obir);
#endif

#ifdef CONFIG_QE
	/* Config QE ioports */
	config_qe_ioports();
#endif

	/*
	 * Memory Controller:
	 */

	/* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
	 * addresses - these have to be modified later when FLASH size
	 * has been determined
	 */

#if defined(CONFIG_SYS_BR0_PRELIM)  \
	&& defined(CONFIG_SYS_OR0_PRELIM) \
	&& defined(CONFIG_SYS_LBLAWBAR0_PRELIM) \
	&& defined(CONFIG_SYS_LBLAWAR0_PRELIM)
	im->lbus.bank[0].br = CONFIG_SYS_BR0_PRELIM;
	im->lbus.bank[0].or = CONFIG_SYS_OR0_PRELIM;
	im->sysconf.lblaw[0].bar = CONFIG_SYS_LBLAWBAR0_PRELIM;
	im->sysconf.lblaw[0].ar = CONFIG_SYS_LBLAWAR0_PRELIM;
#else
#error	CONFIG_SYS_BR0_PRELIM, CONFIG_SYS_OR0_PRELIM, CONFIG_SYS_LBLAWBAR0_PRELIM & CONFIG_SYS_LBLAWAR0_PRELIM must be defined
#endif

#if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM)
	im->lbus.bank[1].br = CONFIG_SYS_BR1_PRELIM;
	im->lbus.bank[1].or = CONFIG_SYS_OR1_PRELIM;
#endif
#if defined(CONFIG_SYS_LBLAWBAR1_PRELIM) && defined(CONFIG_SYS_LBLAWAR1_PRELIM)
	im->sysconf.lblaw[1].bar = CONFIG_SYS_LBLAWBAR1_PRELIM;
	im->sysconf.lblaw[1].ar = CONFIG_SYS_LBLAWAR1_PRELIM;
#endif
#if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM)
	im->lbus.bank[2].br = CONFIG_SYS_BR2_PRELIM;
	im->lbus.bank[2].or = CONFIG_SYS_OR2_PRELIM;
#endif
#if defined(CONFIG_SYS_LBLAWBAR2_PRELIM) && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
	im->sysconf.lblaw[2].bar = CONFIG_SYS_LBLAWBAR2_PRELIM;
	im->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2_PRELIM;
#endif
#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
	im->lbus.bank[3].br = CONFIG_SYS_BR3_PRELIM;
	im->lbus.bank[3].or = CONFIG_SYS_OR3_PRELIM;
#endif
#if defined(CONFIG_SYS_LBLAWBAR3_PRELIM) && defined(CONFIG_SYS_LBLAWAR3_PRELIM)
	im->sysconf.lblaw[3].bar = CONFIG_SYS_LBLAWBAR3_PRELIM;
	im->sysconf.lblaw[3].ar = CONFIG_SYS_LBLAWAR3_PRELIM;
#endif
#if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM)
	im->lbus.bank[4].br = CONFIG_SYS_BR4_PRELIM;
	im->lbus.bank[4].or = CONFIG_SYS_OR4_PRELIM;
#endif
#if defined(CONFIG_SYS_LBLAWBAR4_PRELIM) && defined(CONFIG_SYS_LBLAWAR4_PRELIM)
	im->sysconf.lblaw[4].bar = CONFIG_SYS_LBLAWBAR4_PRELIM;
	im->sysconf.lblaw[4].ar = CONFIG_SYS_LBLAWAR4_PRELIM;
#endif
#if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM)
	im->lbus.bank[5].br = CONFIG_SYS_BR5_PRELIM;
	im->lbus.bank[5].or = CONFIG_SYS_OR5_PRELIM;
#endif
#if defined(CONFIG_SYS_LBLAWBAR5_PRELIM) && defined(CONFIG_SYS_LBLAWAR5_PRELIM)
	im->sysconf.lblaw[5].bar = CONFIG_SYS_LBLAWBAR5_PRELIM;
	im->sysconf.lblaw[5].ar = CONFIG_SYS_LBLAWAR5_PRELIM;
#endif
#if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM)
	im->lbus.bank[6].br = CONFIG_SYS_BR6_PRELIM;
	im->lbus.bank[6].or = CONFIG_SYS_OR6_PRELIM;
#endif
#if defined(CONFIG_SYS_LBLAWBAR6_PRELIM) && defined(CONFIG_SYS_LBLAWAR6_PRELIM)
	im->sysconf.lblaw[6].bar = CONFIG_SYS_LBLAWBAR6_PRELIM;
	im->sysconf.lblaw[6].ar = CONFIG_SYS_LBLAWAR6_PRELIM;
#endif
#if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM)
	im->lbus.bank[7].br = CONFIG_SYS_BR7_PRELIM;
	im->lbus.bank[7].or = CONFIG_SYS_OR7_PRELIM;
#endif
#if defined(CONFIG_SYS_LBLAWBAR7_PRELIM) && defined(CONFIG_SYS_LBLAWAR7_PRELIM)
	im->sysconf.lblaw[7].bar = CONFIG_SYS_LBLAWBAR7_PRELIM;
	im->sysconf.lblaw[7].ar = CONFIG_SYS_LBLAWAR7_PRELIM;
#endif
#ifdef CONFIG_SYS_GPIO1_PRELIM
	im->gpio[0].dat = CONFIG_SYS_GPIO1_DAT;
	im->gpio[0].dir = CONFIG_SYS_GPIO1_DIR;
#endif
#ifdef CONFIG_SYS_GPIO2_PRELIM
	im->gpio[1].dat = CONFIG_SYS_GPIO2_DAT;
	im->gpio[1].dir = CONFIG_SYS_GPIO2_DIR;
#endif
#ifdef CONFIG_USB_EHCI_FSL
#ifndef CONFIG_MPC834x
	uint32_t temp;
	struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_MPC8xxx_USB_ADDR;

	/* Configure interface. */
	setbits_be32(&ehci->control, REFSEL_16MHZ | UTMI_PHY_EN);

	/* Wait for clock to stabilize */
	do {
		temp = __raw_readl(&ehci->control);
		udelay(1000);
	} while (!(temp & PHY_CLK_VALID));
#endif
#endif
}

int cpu_init_r (void)
{
	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
#ifdef CONFIG_QE
	uint qe_base = CONFIG_SYS_IMMR + 0x00100000; /* QE immr base */
#endif
	__be32 lcrr_mask =
#ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */
		LCRR_DBYP |
#endif
#ifdef CONFIG_SYS_LCRR_EADC /* external address delay */
		LCRR_EADC |
#endif
#ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */
		LCRR_CLKDIV |
#endif
		0;
	__be32 lcrr_val =
#ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */
		CONFIG_SYS_LCRR_DBYP |
#endif
#ifdef CONFIG_SYS_LCRR_EADC
		CONFIG_SYS_LCRR_EADC |
#endif
#ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */
		CONFIG_SYS_LCRR_CLKDIV |
#endif
		0;

	/* LCRR - Clock Ratio Register (10.3.1.16)
	 * write, read, and isync per MPC8379ERM rev.1 CLKDEV field description
	 */
	clrsetbits_be32(&im->lbus.lcrr, lcrr_mask, lcrr_val);
	__raw_readl(&im->lbus.lcrr);
	isync();

#ifdef CONFIG_QE
	qe_init(qe_base);
	qe_reset();
#endif
	return 0;
}

/*
 * Print out the bus arbiter event
 */
#if defined(CONFIG_DISPLAY_AER_FULL)
static int print_83xx_arb_event(int force)
{
	static char* event[] = {
		"Address Time Out",
		"Data Time Out",
		"Address Only Transfer Type",
		"External Control Word Transfer Type",
		"Reserved Transfer Type",
		"Transfer Error",
		"reserved",
		"reserved"
	};
	static char* master[] = {
		"e300 Core Data Transaction",
		"reserved",
		"e300 Core Instruction Fetch",
		"reserved",
		"TSEC1",
		"TSEC2",
		"USB MPH",
		"USB DR",
		"Encryption Core",
		"I2C Boot Sequencer",
		"JTAG",
		"reserved",
		"eSDHC",
		"PCI1",
		"PCI2",
		"DMA",
		"QUICC Engine 00",
		"QUICC Engine 01",
		"QUICC Engine 10",
		"QUICC Engine 11",
		"reserved",
		"reserved",
		"reserved",
		"reserved",
		"SATA1",
		"SATA2",
		"SATA3",
		"SATA4",
		"reserved",
		"PCI Express 1",
		"PCI Express 2",
		"TDM-DMAC"
	};
	static char *transfer[] = {
		"Address-only, Clean Block",
		"Address-only, lwarx reservation set",
		"Single-beat or Burst write",
		"reserved",
		"Address-only, Flush Block",
		"reserved",
		"Burst write",
		"reserved",
		"Address-only, sync",
		"Address-only, tlbsync",
		"Single-beat or Burst read",
		"Single-beat or Burst read",
		"Address-only, Kill Block",
		"Address-only, icbi",
		"Burst read",
		"reserved",
		"Address-only, eieio",
		"reserved",
		"Single-beat write",
		"reserved",
		"ecowx - Illegal single-beat write",
		"reserved",
		"reserved",
		"reserved",
		"Address-only, TLB Invalidate",
		"reserved",
		"Single-beat or Burst read",
		"reserved",
		"eciwx - Illegal single-beat read",
		"reserved",
		"Burst read",
		"reserved"
	};

	int etype = (gd->arbiter_event_attributes & AEATR_EVENT)
	            >> AEATR_EVENT_SHIFT;
	int mstr_id = (gd->arbiter_event_attributes & AEATR_MSTR_ID)
	              >> AEATR_MSTR_ID_SHIFT;
	int tbst = (gd->arbiter_event_attributes & AEATR_TBST)
	           >> AEATR_TBST_SHIFT;
	int tsize = (gd->arbiter_event_attributes & AEATR_TSIZE)
	            >> AEATR_TSIZE_SHIFT;
	int ttype = (gd->arbiter_event_attributes & AEATR_TTYPE)
	            >> AEATR_TTYPE_SHIFT;

	if (!force && !gd->arbiter_event_address)
		return 0;

	puts("Arbiter Event Status:\n");
	printf("       Event Address: 0x%08lX\n", gd->arbiter_event_address);
	printf("       Event Type:    0x%1x  = %s\n", etype, event[etype]);
	printf("       Master ID:     0x%02x = %s\n", mstr_id, master[mstr_id]);
	printf("       Transfer Size: 0x%1x  = %d bytes\n", (tbst<<3) | tsize,
				tbst ? (tsize ? tsize : 8) : 16 + 8 * tsize);
	printf("       Transfer Type: 0x%02x = %s\n", ttype, transfer[ttype]);

	return gd->arbiter_event_address;
}

#elif defined(CONFIG_DISPLAY_AER_BRIEF)

static int print_83xx_arb_event(int force)
{
	if (!force && !gd->arbiter_event_address)
		return 0;

	printf("Arbiter Event Status: AEATR=0x%08lX, AEADR=0x%08lX\n",
		gd->arbiter_event_attributes, gd->arbiter_event_address);

	return gd->arbiter_event_address;
}
#endif /* CONFIG_DISPLAY_AER_xxxx */

/*
 * Figure out the cause of the reset
 */
int prt_83xx_rsr(void)
{
	static struct {
		ulong mask;
		char *desc;
	} bits[] = {
		{
		RSR_SWSR, "Software Soft"}, {
		RSR_SWHR, "Software Hard"}, {
		RSR_JSRS, "JTAG Soft"}, {
		RSR_CSHR, "Check Stop"}, {
		RSR_SWRS, "Software Watchdog"}, {
		RSR_BMRS, "Bus Monitor"}, {
		RSR_SRS,  "External/Internal Soft"}, {
		RSR_HRS,  "External/Internal Hard"}
	};
	static int n = sizeof bits / sizeof bits[0];
	ulong rsr = gd->reset_status;
	int i;
	char *sep;

	puts("Reset Status:");

	sep = " ";
	for (i = 0; i < n; i++)
		if (rsr & bits[i].mask) {
			printf("%s%s", sep, bits[i].desc);
			sep = ", ";
		}
	puts("\n");

#if defined(CONFIG_DISPLAY_AER_FULL) || defined(CONFIG_DISPLAY_AER_BRIEF)
	print_83xx_arb_event(rsr & RSR_BMRS);
#endif
	puts("\n");

	return 0;
}
Commit	Line	Data
f046ccd1	1	/*
4ef01010	2	* Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
f046ccd1 EL	3	*
	4	* See file CREDITS for list of people who contributed to this
	5	* project.
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation; either version 2 of
	10	* the License, or (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	20	* MA 02111-1307 USA
f046ccd1 EL	21	*/
	22
	23	#include <common.h>
	24	#include <mpc83xx.h>
	25	#include <ioports.h>
4ef01010	26	#include <asm/io.h>
c7190f02	27	#ifdef CONFIG_USB_EHCI_FSL
4ef01010 VM	28	#include <usb/ehci-fsl.h>
4ef01010 VM	29	#endif
f046ccd1	30
d87080b7 WD	31	DECLARE_GLOBAL_DATA_PTR;
d87080b7 WD	32
7737d5c6 DL	33	#ifdef CONFIG_QE
	34	extern qe_iop_conf_t qe_iop_conf_tab[];
	35	extern void qe_config_iopin(u8 port, u8 pin, int dir,
	36	int open_drain, int assign);
	37	extern void qe_init(uint qe_base);
	38	extern void qe_reset(void);
	39
	40	static void config_qe_ioports(void)
	41	{
	42	u8 port, pin;
	43	int dir, open_drain, assign;
	44	int i;
	45
	46	for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
	47	port = qe_iop_conf_tab[i].port;
	48	pin = qe_iop_conf_tab[i].pin;
	49	dir = qe_iop_conf_tab[i].dir;
	50	open_drain = qe_iop_conf_tab[i].open_drain;
	51	assign = qe_iop_conf_tab[i].assign;
	52	qe_config_iopin(port, pin, dir, open_drain, assign);
	53	}
	54	}
	55	#endif
	56
f046ccd1 EL	57	/*
	58	* Breathe some life into the CPU...
	59	*
	60	* Set up the memory map,
	61	* initialize a bunch of registers,
	62	* initialize the UPM's
	63	*/
	64	void cpu_init_f (volatile immap_t * im)
	65	{
c7190f02 KP	66	__be32 acr_mask =
	67	#ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */
	68	(ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT) \|
2ad6b513	69	#endif
c7190f02 KP	70	#ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */
c7190f02 KP	71	(ACR_RPTCNT << ACR_RPTCNT_SHIFT) \|
9e896478	72	#endif
c7190f02 KP	73	0;
	74	__be32 acr_val =
	75	#ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */
	76	(CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT) \|
	77	#endif
	78	#ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */
	79	(CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT) \|
	80	#endif
	81	0;
	82	__be32 spcr_mask =
	83	#ifdef CONFIG_SYS_SPCR_OPT /* Optimize transactions between CSB and other dev */
	84	(SPCR_OPT << SPCR_OPT_SHIFT) \|
	85	#endif
	86	#ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */
	87	(SPCR_TSECEP << SPCR_TSECEP_SHIFT) \|
	88	#endif
	89	#ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */
	90	(SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT) \|
	91	#endif
	92	#ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */
	93	(SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT) \|
	94	#endif
	95	0;
	96	__be32 spcr_val =
6d0f6bcf	97	#ifdef CONFIG_SYS_SPCR_OPT
c7190f02	98	(CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT) \|
5bbeea86	99	#endif
c7190f02 KP	100	#ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */
c7190f02 KP	101	(CONFIG_SYS_SPCR_TSECEP << SPCR_TSECEP_SHIFT) \|
9e896478	102	#endif
c7190f02 KP	103	#ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */
c7190f02 KP	104	(CONFIG_SYS_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT) \|
2ad6b513	105	#endif
c7190f02 KP	106	#ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */
c7190f02 KP	107	(CONFIG_SYS_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT) \|
9e896478	108	#endif
c7190f02 KP	109	0;
	110	__be32 sccr_mask =
	111	#ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
	112	(SCCR_ENCCM << SCCR_ENCCM_SHIFT) \|
9e896478	113	#endif
c7190f02 KP	114	#ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
c7190f02 KP	115	(SCCR_PCICM << SCCR_PCICM_SHIFT) \|
9e896478	116	#endif
c7190f02 KP	117	#ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
c7190f02 KP	118	(SCCR_TSECCM << SCCR_TSECCM_SHIFT) \|
2ad6b513	119	#endif
c7190f02 KP	120	#ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
c7190f02 KP	121	(SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) \|
2ad6b513	122	#endif
c7190f02 KP	123	#ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
c7190f02 KP	124	(SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) \|
4feab4de	125	#endif
c7190f02 KP	126	#ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
c7190f02 KP	127	(SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT) \|
df33f6b4	128	#endif
c7190f02 KP	129	#ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */
c7190f02 KP	130	(SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT) \|
df33f6b4	131	#endif
c7190f02 KP	132	#ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
c7190f02 KP	133	(SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT) \|
4feab4de	134	#endif
c7190f02 KP	135	#ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */
c7190f02 KP	136	(SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) \|
4feab4de	137	#endif
c7190f02 KP	138	#ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
	139	(SCCR_SATACM << SCCR_SATACM_SHIFT) \|
	140	#endif
	141	0;
	142	__be32 sccr_val =
	143	#ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
	144	(CONFIG_SYS_SCCR_ENCCM << SCCR_ENCCM_SHIFT) \|
2ad6b513	145	#endif
c7190f02 KP	146	#ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
	147	(CONFIG_SYS_SCCR_PCICM << SCCR_PCICM_SHIFT) \|
	148	#endif
	149	#ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
	150	(CONFIG_SYS_SCCR_TSECCM << SCCR_TSECCM_SHIFT) \|
	151	#endif
	152	#ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
	153	(CONFIG_SYS_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) \|
	154	#endif
	155	#ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
	156	(CONFIG_SYS_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) \|
	157	#endif
	158	#ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
	159	(CONFIG_SYS_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT) \|
	160	#endif
	161	#ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */
	162	(CONFIG_SYS_SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT) \|
	163	#endif
	164	#ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
	165	(CONFIG_SYS_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT) \|
	166	#endif
	167	#ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */
	168	(CONFIG_SYS_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) \|
	169	#endif
	170	#ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
	171	(CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT) \|
	172	#endif
	173	0;
	174
	175	/* Pointer is writable since we allocated a register for it */
	176	gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
	177
	178	/* Clear initial global data */
	179	memset ((void *) gd, 0, sizeof (gd_t));
	180
	181	/* system performance tweaking */
	182	clrsetbits_be32(&im->arbiter.acr, acr_mask, acr_val);
	183
	184	clrsetbits_be32(&im->sysconf.spcr, spcr_mask, spcr_val);
	185
	186	clrsetbits_be32(&im->clk.sccr, sccr_mask, sccr_val);
2ad6b513	187
f046ccd1	188	/* RSR - Reset Status Register - clear all status (4.6.1.3) */
c7190f02 KP	189	gd->reset_status = __raw_readl(&im->reset.rsr);
c7190f02 KP	190	__raw_writel(~(RSR_RES), &im->reset.rsr);
f046ccd1	191
46497056	192	/* AER - Arbiter Event Register - store status */
c7190f02 KP	193	gd->arbiter_event_attributes = __raw_readl(&im->arbiter.aeatr);
c7190f02 KP	194	gd->arbiter_event_address = __raw_readl(&im->arbiter.aeadr);
46497056	195
f046ccd1 EL	196	/*
	197	* RMR - Reset Mode Register
	198	* contains checkstop reset enable (4.6.1.4)
	199	*/
c7190f02	200	__raw_writel(RMR_CSRE & (1<<RMR_CSRE_SHIFT), &im->reset.rmr);
f046ccd1	201
c7190f02 KP	202	/* Enable Time Base & Decrementer ( so we will have udelay() )*/
c7190f02 KP	203	setbits_be32(&im->sysconf.spcr, SPCR_TBEN);
f046ccd1 EL	204
f046ccd1 EL	205	/* System General Purpose Register */
6d0f6bcf	206	#ifdef CONFIG_SYS_SICRH
2c7920af	207	#if defined(CONFIG_MPC834x) \|\| defined(CONFIG_MPC8313)
846f1574	208	/* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */
c7190f02 KP	209	__raw_writel((im->sysconf.sicrh & 0x0000000C) \| CONFIG_SYS_SICRH,
c7190f02 KP	210	&im->sysconf.sicrh);
846f1574	211	#else
c7190f02	212	__raw_writel(CONFIG_SYS_SICRH, &im->sysconf.sicrh);
9260a561	213	#endif
846f1574	214	#endif
6d0f6bcf	215	#ifdef CONFIG_SYS_SICRL
c7190f02	216	__raw_writel(CONFIG_SYS_SICRL, &im->sysconf.sicrl);
9260a561	217	#endif
c7190f02 KP	218	#ifdef CONFIG_SYS_DDRCDR /* DDR control driver register */
c7190f02 KP	219	__raw_writel(CONFIG_SYS_DDRCDR, &im->sysconf.ddrcdr);
24c3aca3	220	#endif
c7190f02 KP	221	#ifdef CONFIG_SYS_OBIR /* Output buffer impedance register */
c7190f02 KP	222	__raw_writel(CONFIG_SYS_OBIR, &im->sysconf.obir);
19580e66	223	#endif
24c3aca3	224
7737d5c6 DL	225	#ifdef CONFIG_QE
	226	/* Config QE ioports */
	227	config_qe_ioports();
	228	#endif
f046ccd1 EL	229
	230	/*
	231	* Memory Controller:
	232	*/
	233
	234	/* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
	235	* addresses - these have to be modified later when FLASH size
	236	* has been determined
	237	*/
	238
6d0f6bcf JCPV	239	#if defined(CONFIG_SYS_BR0_PRELIM) \
	240	&& defined(CONFIG_SYS_OR0_PRELIM) \
	241	&& defined(CONFIG_SYS_LBLAWBAR0_PRELIM) \
	242	&& defined(CONFIG_SYS_LBLAWAR0_PRELIM)
	243	im->lbus.bank[0].br = CONFIG_SYS_BR0_PRELIM;
	244	im->lbus.bank[0].or = CONFIG_SYS_OR0_PRELIM;
	245	im->sysconf.lblaw[0].bar = CONFIG_SYS_LBLAWBAR0_PRELIM;
	246	im->sysconf.lblaw[0].ar = CONFIG_SYS_LBLAWAR0_PRELIM;
f046ccd1	247	#else
6d0f6bcf	248	#error CONFIG_SYS_BR0_PRELIM, CONFIG_SYS_OR0_PRELIM, CONFIG_SYS_LBLAWBAR0_PRELIM & CONFIG_SYS_LBLAWAR0_PRELIM must be defined
f046ccd1 EL	249	#endif
f046ccd1 EL	250
6d0f6bcf JCPV	251	#if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM)
	252	im->lbus.bank[1].br = CONFIG_SYS_BR1_PRELIM;
	253	im->lbus.bank[1].or = CONFIG_SYS_OR1_PRELIM;
c99f384d	254	#endif
6d0f6bcf JCPV	255	#if defined(CONFIG_SYS_LBLAWBAR1_PRELIM) && defined(CONFIG_SYS_LBLAWAR1_PRELIM)
	256	im->sysconf.lblaw[1].bar = CONFIG_SYS_LBLAWBAR1_PRELIM;
	257	im->sysconf.lblaw[1].ar = CONFIG_SYS_LBLAWAR1_PRELIM;
f046ccd1	258	#endif
6d0f6bcf JCPV	259	#if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM)
	260	im->lbus.bank[2].br = CONFIG_SYS_BR2_PRELIM;
	261	im->lbus.bank[2].or = CONFIG_SYS_OR2_PRELIM;
c99f384d	262	#endif
6d0f6bcf JCPV	263	#if defined(CONFIG_SYS_LBLAWBAR2_PRELIM) && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
	264	im->sysconf.lblaw[2].bar = CONFIG_SYS_LBLAWBAR2_PRELIM;
	265	im->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2_PRELIM;
f046ccd1	266	#endif
6d0f6bcf JCPV	267	#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
	268	im->lbus.bank[3].br = CONFIG_SYS_BR3_PRELIM;
	269	im->lbus.bank[3].or = CONFIG_SYS_OR3_PRELIM;
c99f384d	270	#endif
6d0f6bcf JCPV	271	#if defined(CONFIG_SYS_LBLAWBAR3_PRELIM) && defined(CONFIG_SYS_LBLAWAR3_PRELIM)
	272	im->sysconf.lblaw[3].bar = CONFIG_SYS_LBLAWBAR3_PRELIM;
	273	im->sysconf.lblaw[3].ar = CONFIG_SYS_LBLAWAR3_PRELIM;
f046ccd1	274	#endif
6d0f6bcf JCPV	275	#if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM)
	276	im->lbus.bank[4].br = CONFIG_SYS_BR4_PRELIM;
	277	im->lbus.bank[4].or = CONFIG_SYS_OR4_PRELIM;
c99f384d	278	#endif
6d0f6bcf JCPV	279	#if defined(CONFIG_SYS_LBLAWBAR4_PRELIM) && defined(CONFIG_SYS_LBLAWAR4_PRELIM)
	280	im->sysconf.lblaw[4].bar = CONFIG_SYS_LBLAWBAR4_PRELIM;
	281	im->sysconf.lblaw[4].ar = CONFIG_SYS_LBLAWAR4_PRELIM;
f046ccd1	282	#endif
6d0f6bcf JCPV	283	#if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM)
	284	im->lbus.bank[5].br = CONFIG_SYS_BR5_PRELIM;
	285	im->lbus.bank[5].or = CONFIG_SYS_OR5_PRELIM;
c99f384d	286	#endif
6d0f6bcf JCPV	287	#if defined(CONFIG_SYS_LBLAWBAR5_PRELIM) && defined(CONFIG_SYS_LBLAWAR5_PRELIM)
	288	im->sysconf.lblaw[5].bar = CONFIG_SYS_LBLAWBAR5_PRELIM;
	289	im->sysconf.lblaw[5].ar = CONFIG_SYS_LBLAWAR5_PRELIM;
f046ccd1	290	#endif
6d0f6bcf JCPV	291	#if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM)
	292	im->lbus.bank[6].br = CONFIG_SYS_BR6_PRELIM;
	293	im->lbus.bank[6].or = CONFIG_SYS_OR6_PRELIM;
c99f384d	294	#endif
6d0f6bcf JCPV	295	#if defined(CONFIG_SYS_LBLAWBAR6_PRELIM) && defined(CONFIG_SYS_LBLAWAR6_PRELIM)
	296	im->sysconf.lblaw[6].bar = CONFIG_SYS_LBLAWBAR6_PRELIM;
	297	im->sysconf.lblaw[6].ar = CONFIG_SYS_LBLAWAR6_PRELIM;
f046ccd1	298	#endif
6d0f6bcf JCPV	299	#if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM)
	300	im->lbus.bank[7].br = CONFIG_SYS_BR7_PRELIM;
	301	im->lbus.bank[7].or = CONFIG_SYS_OR7_PRELIM;
c99f384d	302	#endif
6d0f6bcf JCPV	303	#if defined(CONFIG_SYS_LBLAWBAR7_PRELIM) && defined(CONFIG_SYS_LBLAWAR7_PRELIM)
	304	im->sysconf.lblaw[7].bar = CONFIG_SYS_LBLAWBAR7_PRELIM;
	305	im->sysconf.lblaw[7].ar = CONFIG_SYS_LBLAWAR7_PRELIM;
f046ccd1	306	#endif
6d0f6bcf JCPV	307	#ifdef CONFIG_SYS_GPIO1_PRELIM
	308	im->gpio[0].dat = CONFIG_SYS_GPIO1_DAT;
	309	im->gpio[0].dir = CONFIG_SYS_GPIO1_DIR;
a15b44db	310	#endif
6d0f6bcf JCPV	311	#ifdef CONFIG_SYS_GPIO2_PRELIM
	312	im->gpio[1].dat = CONFIG_SYS_GPIO2_DAT;
	313	im->gpio[1].dir = CONFIG_SYS_GPIO2_DIR;
a15b44db	314	#endif
4ef01010	315	#ifdef CONFIG_USB_EHCI_FSL
d89e1c36	316	#ifndef CONFIG_MPC834x
4ef01010 VM	317	uint32_t temp;
	318	struct usb_ehci ehci = (struct usb_ehci )CONFIG_SYS_MPC8xxx_USB_ADDR;
	319
	320	/* Configure interface. */
db7b43e4	321	setbits_be32(&ehci->control, REFSEL_16MHZ \| UTMI_PHY_EN);
4ef01010 VM	322
	323	/* Wait for clock to stabilize */
	324	do {
c7190f02	325	temp = __raw_readl(&ehci->control);
4ef01010 VM	326	udelay(1000);
	327	} while (!(temp & PHY_CLK_VALID));
	328	#endif
d89e1c36	329	#endif
f046ccd1 EL	330	}
f046ccd1 EL	331
f046ccd1 EL	332	int cpu_init_r (void)
f046ccd1 EL	333	{
c7190f02	334	volatile immap_t im = (volatile immap_t )CONFIG_SYS_IMMR;
7737d5c6	335	#ifdef CONFIG_QE
6d0f6bcf	336	uint qe_base = CONFIG_SYS_IMMR + 0x00100000; /* QE immr base */
c7190f02 KP	337	#endif
	338	__be32 lcrr_mask =
	339	#ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */
	340	LCRR_DBYP \|
	341	#endif
	342	#ifdef CONFIG_SYS_LCRR_EADC /* external address delay */
	343	LCRR_EADC \|
	344	#endif
	345	#ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */
	346	LCRR_CLKDIV \|
	347	#endif
	348	0;
	349	__be32 lcrr_val =
	350	#ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */
	351	CONFIG_SYS_LCRR_DBYP \|
	352	#endif
	353	#ifdef CONFIG_SYS_LCRR_EADC
	354	CONFIG_SYS_LCRR_EADC \|
	355	#endif
	356	#ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */
	357	CONFIG_SYS_LCRR_CLKDIV \|
	358	#endif
	359	0;
	360
	361	/* LCRR - Clock Ratio Register (10.3.1.16)
	362	* write, read, and isync per MPC8379ERM rev.1 CLKDEV field description
	363	*/
	364	clrsetbits_be32(&im->lbus.lcrr, lcrr_mask, lcrr_val);
	365	__raw_readl(&im->lbus.lcrr);
	366	isync();
	367
	368	#ifdef CONFIG_QE
7737d5c6 DL	369	qe_init(qe_base);
	370	qe_reset();
	371	#endif
f046ccd1 EL	372	return 0;
f046ccd1 EL	373	}
9be39a67	374
46497056 NS	375	/*
	376	* Print out the bus arbiter event
	377	*/
	378	#if defined(CONFIG_DISPLAY_AER_FULL)
	379	static int print_83xx_arb_event(int force)
	380	{
	381	static char* event[] = {
	382	"Address Time Out",
	383	"Data Time Out",
	384	"Address Only Transfer Type",
	385	"External Control Word Transfer Type",
	386	"Reserved Transfer Type",
	387	"Transfer Error",
	388	"reserved",
	389	"reserved"
	390	};
	391	static char* master[] = {
	392	"e300 Core Data Transaction",
	393	"reserved",
	394	"e300 Core Instruction Fetch",
	395	"reserved",
	396	"TSEC1",
	397	"TSEC2",
	398	"USB MPH",
	399	"USB DR",
	400	"Encryption Core",
	401	"I2C Boot Sequencer",
	402	"JTAG",
	403	"reserved",
	404	"eSDHC",
	405	"PCI1",
	406	"PCI2",
	407	"DMA",
	408	"QUICC Engine 00",
	409	"QUICC Engine 01",
	410	"QUICC Engine 10",
	411	"QUICC Engine 11",
	412	"reserved",
	413	"reserved",
	414	"reserved",
	415	"reserved",
	416	"SATA1",
	417	"SATA2",
	418	"SATA3",
	419	"SATA4",
	420	"reserved",
	421	"PCI Express 1",
	422	"PCI Express 2",
	423	"TDM-DMAC"
	424	};
	425	static char *transfer[] = {
	426	"Address-only, Clean Block",
	427	"Address-only, lwarx reservation set",
	428	"Single-beat or Burst write",
	429	"reserved",
	430	"Address-only, Flush Block",
	431	"reserved",
	432	"Burst write",
	433	"reserved",
	434	"Address-only, sync",
	435	"Address-only, tlbsync",
	436	"Single-beat or Burst read",
	437	"Single-beat or Burst read",
	438	"Address-only, Kill Block",
439	"Address-only, icbi",
440	"Burst read",
441	"reserved",
442	"Address-only, eieio",
443	"reserved",
444	"Single-beat write",
445	"reserved",
446	"ecowx - Illegal single-beat write",
447	"reserved",
448	"reserved",
449	"reserved",
450	"Address-only, TLB Invalidate",
451	"reserved",
452	"Single-beat or Burst read",
453	"reserved",
454	"eciwx - Illegal single-beat read",
455	"reserved",
456	"Burst read",
457	"reserved"
458	};
459
460	int etype = (gd->arbiter_event_attributes & AEATR_EVENT)
461	>> AEATR_EVENT_SHIFT;
462	int mstr_id = (gd->arbiter_event_attributes & AEATR_MSTR_ID)
463	>> AEATR_MSTR_ID_SHIFT;
464	int tbst = (gd->arbiter_event_attributes & AEATR_TBST)
465	>> AEATR_TBST_SHIFT;
466	int tsize = (gd->arbiter_event_attributes & AEATR_TSIZE)
467	>> AEATR_TSIZE_SHIFT;
468	int ttype = (gd->arbiter_event_attributes & AEATR_TTYPE)
469	>> AEATR_TTYPE_SHIFT;
470
471	if (!force && !gd->arbiter_event_address)
472	return 0;
473
474	puts("Arbiter Event Status:\n");
475	printf(" Event Address: 0x%08lX\n", gd->arbiter_event_address);
476	printf(" Event Type: 0x%1x = %s\n", etype, event[etype]);
477	printf(" Master ID: 0x%02x = %s\n", mstr_id, master[mstr_id]);
478	printf(" Transfer Size: 0x%1x = %d bytes\n", (tbst<<3) \| tsize,
479	tbst ? (tsize ? tsize : 8) : 16 + 8 * tsize);
480	printf(" Transfer Type: 0x%02x = %s\n", ttype, transfer[ttype]);
481
482	return gd->arbiter_event_address;
483	}
484
485	#elif defined(CONFIG_DISPLAY_AER_BRIEF)
486
487	static int print_83xx_arb_event(int force)
488	{
489	if (!force && !gd->arbiter_event_address)
490	return 0;
491
492	printf("Arbiter Event Status: AEATR=0x%08lX, AEADR=0x%08lX\n",
493	gd->arbiter_event_attributes, gd->arbiter_event_address);
494
495	return gd->arbiter_event_address;
496	}
497	#endif /* CONFIG_DISPLAY_AER_xxxx */
498
9be39a67 DL	499	/*
	500	* Figure out the cause of the reset
	501	*/
	502	int prt_83xx_rsr(void)
	503	{
	504	static struct {
	505	ulong mask;
	506	char *desc;
	507	} bits[] = {
	508	{
	509	RSR_SWSR, "Software Soft"}, {
	510	RSR_SWHR, "Software Hard"}, {
	511	RSR_JSRS, "JTAG Soft"}, {
	512	RSR_CSHR, "Check Stop"}, {
	513	RSR_SWRS, "Software Watchdog"}, {
	514	RSR_BMRS, "Bus Monitor"}, {
	515	RSR_SRS, "External/Internal Soft"}, {
	516	RSR_HRS, "External/Internal Hard"}
	517	};
	518	static int n = sizeof bits / sizeof bits[0];
	519	ulong rsr = gd->reset_status;
	520	int i;
	521	char *sep;
	522
	523	puts("Reset Status:");
	524
	525	sep = " ";
	526	for (i = 0; i < n; i++)
	527	if (rsr & bits[i].mask) {
	528	printf("%s%s", sep, bits[i].desc);
	529	sep = ", ";
	530	}
46497056 NS	531	puts("\n");
	532
	533	#if defined(CONFIG_DISPLAY_AER_FULL) \|\| defined(CONFIG_DISPLAY_AER_BRIEF)
	534	print_83xx_arb_event(rsr & RSR_BMRS);
	535	#endif
	536	puts("\n");
	537
9be39a67 DL	538	return 0;
9be39a67 DL	539	}