[J-u-boot.git] / board / engicam / isiotmx6ul / isiotmx6ul.c

/*
 * Copyright (C) 2016 Amarula Solutions B.V.
 * Copyright (C) 2016 Engicam S.r.l.
 * Author: Jagan Teki <[email protected]>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <mmc.h>

#include <asm/io.h>
#include <asm/gpio.h>
#include <linux/sizes.h>

#include <asm/arch/clock.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/iomux-v3.h>

#include "../common/board.h"

DECLARE_GLOBAL_DATA_PTR;

#ifdef CONFIG_NAND_MXS

#define GPMI_PAD_CTRL0		(PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
#define GPMI_PAD_CTRL1		(PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
				PAD_CTL_SRE_FAST)
#define GPMI_PAD_CTRL2		(GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)

static iomux_v3_cfg_t const nand_pads[] = {
	IOMUX_PADS(PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	IOMUX_PADS(PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	IOMUX_PADS(PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	IOMUX_PADS(PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	IOMUX_PADS(PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	IOMUX_PADS(PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	IOMUX_PADS(PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	IOMUX_PADS(PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	IOMUX_PADS(PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	IOMUX_PADS(PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	IOMUX_PADS(PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	IOMUX_PADS(PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	IOMUX_PADS(PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	IOMUX_PADS(PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	IOMUX_PADS(PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
};

void setup_gpmi_nand(void)
{
	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;

	/* config gpmi nand iomux */
	SETUP_IOMUX_PADS(nand_pads);

	clrbits_le32(&mxc_ccm->CCGR4,
		     MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
		     MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);

	/*
	 * config gpmi and bch clock to 100 MHz
	 * bch/gpmi select PLL2 PFD2 400M
	 * 100M = 400M / 4
	 */
	clrbits_le32(&mxc_ccm->cscmr1,
		     MXC_CCM_CSCMR1_BCH_CLK_SEL |
		     MXC_CCM_CSCMR1_GPMI_CLK_SEL);
	clrsetbits_le32(&mxc_ccm->cscdr1,
			MXC_CCM_CSCDR1_BCH_PODF_MASK |
			MXC_CCM_CSCDR1_GPMI_PODF_MASK,
			(3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) |
			(3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));

	/* enable gpmi and bch clock gating */
	setbits_le32(&mxc_ccm->CCGR4,
		     MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
		     MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);

	/* enable apbh clock gating */
	setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
}
#endif /* CONFIG_NAND_MXS */

#ifdef CONFIG_ENV_IS_IN_MMC
int board_mmc_get_env_dev(int devno)
{
	/* dev 0 for SD/eSD, dev 1 for MMC/eMMC */
	return (devno == 0) ? 0 : 1;
}
#endif

void setenv_fdt_file(void)
{
	if (is_mx6ul()) {
#ifdef CONFIG_ENV_IS_IN_MMC
		env_set("fdt_file", "imx6ul-isiot-emmc.dtb");
#else
		env_set("fdt_file", "imx6ul-isiot-nand.dtb");
#endif
	}
}

#ifdef CONFIG_SPL_BUILD
#include <spl.h>

/* MMC board initialization is needed till adding DM support in SPL */
#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
#include <mmc.h>
#include <fsl_esdhc.h>

#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
	PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |               \
	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)

static iomux_v3_cfg_t const usdhc1_pads[] = {
	IOMUX_PADS(PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),

	/* VSELECT */
	IOMUX_PADS(PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	/* CD */
	IOMUX_PADS(PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
	/* RST_B */
	IOMUX_PADS(PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
};

static iomux_v3_cfg_t const usdhc2_pads[] = {
	IOMUX_PADS(PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
};

#define USDHC1_CD_GPIO	IMX_GPIO_NR(1, 19)
#define USDHC2_CD_GPIO	IMX_GPIO_NR(4, 5)

struct fsl_esdhc_cfg usdhc_cfg[2] = {
	{USDHC1_BASE_ADDR, 0, 4},
	{USDHC2_BASE_ADDR, 0, 8},
};

int board_mmc_getcd(struct mmc *mmc)
{
	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
	int ret = 0;

	switch (cfg->esdhc_base) {
	case USDHC1_BASE_ADDR:
		ret = !gpio_get_value(USDHC1_CD_GPIO);
		break;
	case USDHC2_BASE_ADDR:
		ret = !gpio_get_value(USDHC2_CD_GPIO);
		break;
	}

	return ret;
}

int board_mmc_init(bd_t *bis)
{
	int i, ret;

	/*
	* According to the board_mmc_init() the following map is done:
	* (U-boot device node)    (Physical Port)
	* mmc0				USDHC1
	* mmc1				USDHC2
	*/
	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
		switch (i) {
		case 0:
			SETUP_IOMUX_PADS(usdhc1_pads);
			gpio_direction_input(USDHC1_CD_GPIO);
			usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
			break;
		case 1:
			SETUP_IOMUX_PADS(usdhc2_pads);
			gpio_direction_input(USDHC2_CD_GPIO);
			usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
			break;
		default:
			printf("Warning - USDHC%d controller not supporting\n",
			       i + 1);
			return 0;
		}

		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
		if (ret) {
			printf("Warning: failed to initialize mmc dev %d\n", i);
			return ret;
		}
	}

	return 0;
}

#ifdef CONFIG_ENV_IS_IN_MMC
void board_boot_order(u32 *spl_boot_list)
{
	u32 bmode = imx6_src_get_boot_mode();
	u8 boot_dev = BOOT_DEVICE_MMC1;

	switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) {
	case IMX6_BMODE_SD:
	case IMX6_BMODE_ESD:
		/* SD/eSD - BOOT_DEVICE_MMC1 */
		break;
	case IMX6_BMODE_MMC:
	case IMX6_BMODE_EMMC:
		/* MMC/eMMC */
		boot_dev = BOOT_DEVICE_MMC2;
		break;
	default:
		/* Default - BOOT_DEVICE_MMC1 */
		printf("Wrong board boot order\n");
		break;
	}

	spl_boot_list[0] = boot_dev;
}
#endif
#endif /* CONFIG_FSL_ESDHC */
#endif /* CONFIG_SPL_BUILD */
Commit	Line	Data
e9dfa1e1 JT	1	/*
	2	* Copyright (C) 2016 Amarula Solutions B.V.
	3	* Copyright (C) 2016 Engicam S.r.l.
	4	* Author: Jagan Teki <[email protected]>
	5	*
	6	* SPDX-License-Identifier: GPL-2.0+
	7	*/
	8
	9	#include <common.h>
0dd259a1	10	#include <mmc.h>
e9dfa1e1 JT	11
	12	#include <asm/io.h>
	13	#include <asm/gpio.h>
	14	#include <linux/sizes.h>
	15
	16	#include <asm/arch/clock.h>
	17	#include <asm/arch/crm_regs.h>
	18	#include <asm/arch/iomux.h>
	19	#include <asm/arch/mx6-pins.h>
	20	#include <asm/arch/sys_proto.h>
552a848e	21	#include <asm/mach-imx/iomux-v3.h>
e9dfa1e1	22
ac880e77 JT	23	#include "../common/board.h"
ac880e77 JT	24
e9dfa1e1 JT	25	DECLARE_GLOBAL_DATA_PTR;
e9dfa1e1 JT	26
6788a7e4 JT	27	#ifdef CONFIG_NAND_MXS
	28
	29	#define GPMI_PAD_CTRL0 (PAD_CTL_PKE \| PAD_CTL_PUE \| PAD_CTL_PUS_100K_UP)
	30	#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm \| PAD_CTL_SPEED_MED \| \
	31	PAD_CTL_SRE_FAST)
	32	#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 \| GPMI_PAD_CTRL1)
	33
	34	static iomux_v3_cfg_t const nand_pads[] = {
534bf2cc JT	35	IOMUX_PADS(PAD_NAND_DATA00__RAWNAND_DATA00 \| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	36	IOMUX_PADS(PAD_NAND_DATA01__RAWNAND_DATA01 \| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	37	IOMUX_PADS(PAD_NAND_DATA02__RAWNAND_DATA02 \| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	38	IOMUX_PADS(PAD_NAND_DATA03__RAWNAND_DATA03 \| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	39	IOMUX_PADS(PAD_NAND_DATA04__RAWNAND_DATA04 \| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	40	IOMUX_PADS(PAD_NAND_DATA05__RAWNAND_DATA05 \| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	41	IOMUX_PADS(PAD_NAND_DATA06__RAWNAND_DATA06 \| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	42	IOMUX_PADS(PAD_NAND_DATA07__RAWNAND_DATA07 \| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	43	IOMUX_PADS(PAD_NAND_CLE__RAWNAND_CLE \| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	44	IOMUX_PADS(PAD_NAND_ALE__RAWNAND_ALE \| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	45	IOMUX_PADS(PAD_NAND_CE0_B__RAWNAND_CE0_B \| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	46	IOMUX_PADS(PAD_NAND_RE_B__RAWNAND_RE_B \| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	47	IOMUX_PADS(PAD_NAND_WE_B__RAWNAND_WE_B \| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	48	IOMUX_PADS(PAD_NAND_WP_B__RAWNAND_WP_B \| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	49	IOMUX_PADS(PAD_NAND_READY_B__RAWNAND_READY_B \| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
6788a7e4 JT	50	};
6788a7e4 JT	51
ac880e77	52	void setup_gpmi_nand(void)
6788a7e4 JT	53	{
	54	struct mxc_ccm_reg mxc_ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
	55
	56	/* config gpmi nand iomux */
534bf2cc	57	SETUP_IOMUX_PADS(nand_pads);
6788a7e4 JT	58
	59	clrbits_le32(&mxc_ccm->CCGR4,
	60	MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK \|
	61	MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK \|
	62	MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK \|
	63	MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK \|
	64	MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
	65
	66	/*
	67	* config gpmi and bch clock to 100 MHz
	68	* bch/gpmi select PLL2 PFD2 400M
	69	* 100M = 400M / 4
	70	*/
	71	clrbits_le32(&mxc_ccm->cscmr1,
	72	MXC_CCM_CSCMR1_BCH_CLK_SEL \|
	73	MXC_CCM_CSCMR1_GPMI_CLK_SEL);
	74	clrsetbits_le32(&mxc_ccm->cscdr1,
	75	MXC_CCM_CSCDR1_BCH_PODF_MASK \|
	76	MXC_CCM_CSCDR1_GPMI_PODF_MASK,
	77	(3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) \|
	78	(3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));
	79
	80	/* enable gpmi and bch clock gating */
	81	setbits_le32(&mxc_ccm->CCGR4,
	82	MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK \|
	83	MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK \|
	84	MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK \|
	85	MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK \|
	86	MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
	87
	88	/* enable apbh clock gating */
	89	setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
	90	}
	91	#endif /* CONFIG_NAND_MXS */
	92
0dd259a1	93	#ifdef CONFIG_ENV_IS_IN_MMC
e9685967 JT	94	int board_mmc_get_env_dev(int devno)
	95	{
	96	/* dev 0 for SD/eSD, dev 1 for MMC/eMMC */
	97	return (devno == 0) ? 0 : 1;
	98	}
0dd259a1 JT	99	#endif
0dd259a1 JT	100
f9247569	101	void setenv_fdt_file(void)
2e2a8dc6	102	{
6f1f3f59 JT	103	if (is_mx6ul()) {
6f1f3f59 JT	104	#ifdef CONFIG_ENV_IS_IN_MMC
382bee57	105	env_set("fdt_file", "imx6ul-isiot-emmc.dtb");
6f1f3f59	106	#else
382bee57	107	env_set("fdt_file", "imx6ul-isiot-nand.dtb");
6f1f3f59 JT	108	#endif
6f1f3f59 JT	109	}
2e2a8dc6 JT	110	}
2e2a8dc6 JT	111
e9dfa1e1	112	#ifdef CONFIG_SPL_BUILD
e9dfa1e1 JT	113	#include <spl.h>
e9dfa1e1 JT	114
e9dfa1e1 JT	115	/* MMC board initialization is needed till adding DM support in SPL */
	116	#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
	117	#include <mmc.h>
	118	#include <fsl_esdhc.h>
	119
	120	#define USDHC_PAD_CTRL (PAD_CTL_PKE \| PAD_CTL_PUE \| \
	121	PAD_CTL_PUS_22K_UP \| PAD_CTL_SPEED_LOW \| \
	122	PAD_CTL_DSE_80ohm \| PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
	123
	124	static iomux_v3_cfg_t const usdhc1_pads[] = {
534bf2cc JT	125	IOMUX_PADS(PAD_SD1_CLK__USDHC1_CLK \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	126	IOMUX_PADS(PAD_SD1_CMD__USDHC1_CMD \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	127	IOMUX_PADS(PAD_SD1_DATA0__USDHC1_DATA0 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	128	IOMUX_PADS(PAD_SD1_DATA1__USDHC1_DATA1 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	129	IOMUX_PADS(PAD_SD1_DATA2__USDHC1_DATA2 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	130	IOMUX_PADS(PAD_SD1_DATA3__USDHC1_DATA3 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
e9dfa1e1 JT	131
e9dfa1e1 JT	132	/* VSELECT */
534bf2cc	133	IOMUX_PADS(PAD_GPIO1_IO05__USDHC1_VSELECT \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
e9dfa1e1	134	/* CD */
534bf2cc	135	IOMUX_PADS(PAD_UART1_RTS_B__GPIO1_IO19 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
e9dfa1e1	136	/* RST_B */
534bf2cc	137	IOMUX_PADS(PAD_GPIO1_IO09__GPIO1_IO09 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
e9dfa1e1 JT	138	};
e9dfa1e1 JT	139
7cf22dc8	140	static iomux_v3_cfg_t const usdhc2_pads[] = {
534bf2cc JT	141	IOMUX_PADS(PAD_NAND_ALE__USDHC2_RESET_B \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	142	IOMUX_PADS(PAD_NAND_RE_B__USDHC2_CLK \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	143	IOMUX_PADS(PAD_NAND_WE_B__USDHC2_CMD \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	144	IOMUX_PADS(PAD_NAND_DATA00__USDHC2_DATA0 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	145	IOMUX_PADS(PAD_NAND_DATA01__USDHC2_DATA1 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	146	IOMUX_PADS(PAD_NAND_DATA02__USDHC2_DATA2 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	147	IOMUX_PADS(PAD_NAND_DATA03__USDHC2_DATA3 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	148	IOMUX_PADS(PAD_NAND_DATA04__USDHC2_DATA4 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	149	IOMUX_PADS(PAD_NAND_DATA05__USDHC2_DATA5 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
7cf22dc8 JT	150	};
7cf22dc8 JT	151
e9dfa1e1	152	#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19)
7cf22dc8	153	#define USDHC2_CD_GPIO IMX_GPIO_NR(4, 5)
e9dfa1e1	154
7cf22dc8	155	struct fsl_esdhc_cfg usdhc_cfg[2] = {
e9dfa1e1	156	{USDHC1_BASE_ADDR, 0, 4},
7cf22dc8	157	{USDHC2_BASE_ADDR, 0, 8},
e9dfa1e1 JT	158	};
	159
	160	int board_mmc_getcd(struct mmc *mmc)
	161	{
	162	struct fsl_esdhc_cfg cfg = (struct fsl_esdhc_cfg )mmc->priv;
	163	int ret = 0;
	164
	165	switch (cfg->esdhc_base) {
	166	case USDHC1_BASE_ADDR:
	167	ret = !gpio_get_value(USDHC1_CD_GPIO);
	168	break;
7cf22dc8 JT	169	case USDHC2_BASE_ADDR:
	170	ret = !gpio_get_value(USDHC2_CD_GPIO);
	171	break;
e9dfa1e1 JT	172	}
	173
	174	return ret;
	175	}
	176
	177	int board_mmc_init(bd_t *bis)
	178	{
	179	int i, ret;
	180
	181	/*
	182	* According to the board_mmc_init() the following map is done:
	183	* (U-boot device node) (Physical Port)
	184	* mmc0 USDHC1
7cf22dc8	185	* mmc1 USDHC2
e9dfa1e1 JT	186	*/
	187	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
	188	switch (i) {
	189	case 0:
534bf2cc	190	SETUP_IOMUX_PADS(usdhc1_pads);
e9dfa1e1 JT	191	gpio_direction_input(USDHC1_CD_GPIO);
	192	usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
	193	break;
7cf22dc8	194	case 1:
534bf2cc	195	SETUP_IOMUX_PADS(usdhc2_pads);
7cf22dc8 JT	196	gpio_direction_input(USDHC2_CD_GPIO);
	197	usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
	198	break;
e9dfa1e1 JT	199	default:
	200	printf("Warning - USDHC%d controller not supporting\n",
	201	i + 1);
	202	return 0;
	203	}
	204
	205	ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
	206	if (ret) {
	207	printf("Warning: failed to initialize mmc dev %d\n", i);
	208	return ret;
	209	}
	210	}
	211
	212	return 0;
	213	}
cde5aa37 JT	214
	215	#ifdef CONFIG_ENV_IS_IN_MMC
	216	void board_boot_order(u32 *spl_boot_list)
	217	{
	218	u32 bmode = imx6_src_get_boot_mode();
	219	u8 boot_dev = BOOT_DEVICE_MMC1;
	220
	221	switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) {
	222	case IMX6_BMODE_SD:
	223	case IMX6_BMODE_ESD:
	224	/* SD/eSD - BOOT_DEVICE_MMC1 */
	225	break;
	226	case IMX6_BMODE_MMC:
	227	case IMX6_BMODE_EMMC:
	228	/* MMC/eMMC */
	229	boot_dev = BOOT_DEVICE_MMC2;
	230	break;
	231	default:
	232	/* Default - BOOT_DEVICE_MMC1 */
	233	printf("Wrong board boot order\n");
	234	break;
	235	}
	236
	237	spl_boot_list[0] = boot_dev;
	238	}
	239	#endif
e9dfa1e1	240	#endif /* CONFIG_FSL_ESDHC */
e9dfa1e1	241	#endif /* CONFIG_SPL_BUILD */