[J-u-boot.git] / include / configs / cm41xx.h

/*
 * (C) Copyright 2005
 * Greg Ungerer <[email protected]>.
 * Wolfgang Denk, DENX Software Engineering, [email protected].
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_KS8695	1		/* it is a KS8695 CPU */
#define CONFIG_CM41xx	1		/* it is an OpenGear CM41xx boad */

#define CONFIG_CMDLINE_TAG	 1	/* enable passing of ATAGs	*/
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG	 1

#define CONFIG_DRIVER_KS8695ETH		/* use KS8695 ethernet driver	*/

/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)

/*
 * Hardware drivers
 */

/*
 * select serial console configuration
 */
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_KS8695_SERIAL
#define	CONFIG_SERIAL1
#define CONFIG_CONS_INDEX	1
#define CONFIG_BAUDRATE		115200

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#undef CONFIG_CMD_SAVEENV


#define CONFIG_BOOTDELAY	0
#define CONFIG_BOOTARGS		"mem=32M console=ttyAM0,115200"
#define CONFIG_BOOTCOMMAND	"gofsk 0x02200000"

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP				/* undef to save memory		*/
#define CONFIG_SYS_PROMPT		"boot > "	/* Monitor Command Prompt	*/
#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x00800000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x01000000	/* 16 MB in DRAM	*/

#define CONFIG_SYS_LOAD_ADDR		0x00008000	/* default load address */

#define CONFIG_SYS_HZ			(1000)		/* 1ms resolution ticks */

/*-----------------------------------------------------------------------
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	1	   /* we have 1 bank of DRAM */
#define PHYS_SDRAM_1		0x00000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE	0x02000000 /* 32 MB */
#define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM_1

#define CONFIG_SYS_INIT_SP_ADDR	0x00020000 /* lowest 128k of RAM */

#define PHYS_FLASH_1		0x02000000 /* Flash Bank #1 */
#define PHYS_FLASH_SECT_SIZE    0x00020000 /* 128 KB sectors (x1) */
#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of flash banks */
#define CONFIG_SYS_MAX_FLASH_SECT	(128)	/* max number of sectors on one chip */

/* timeout values are in ticks */
#define CONFIG_SYS_FLASH_ERASE_TOUT	(20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
#define CONFIG_SYS_FLASH_WRITE_TOUT	(20*CONFIG_SYS_HZ) /* Timeout for Flash Write */

#define CONFIG_ENV_SIZE		0x20000     /* Total Size of Environment */

#endif	/* __CONFIG_H */
Commit	Line	Data
16b013e7 WD	1	/*
	2	* (C) Copyright 2005
	3	* Greg Ungerer <[email protected]>.
	4	* Wolfgang Denk, DENX Software Engineering, [email protected].
	5	*
3765b3e7	6	* SPDX-License-Identifier: GPL-2.0+
16b013e7 WD	7	*/
	8	#ifndef __CONFIG_H
	9	#define __CONFIG_H
	10
	11	/*
	12	* High Level Configuration Options
	13	* (easy to change)
	14	*/
	15	#define CONFIG_KS8695 1 /* it is a KS8695 CPU */
	16	#define CONFIG_CM41xx 1 /* it is an OpenGear CM41xx boad */
	17
16b013e7 WD	18	#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
	19	#define CONFIG_SETUP_MEMORY_TAGS 1
	20	#define CONFIG_INITRD_TAG 1
	21
2eab48f5 WD	22	#define CONFIG_DRIVER_KS8695ETH /* use KS8695 ethernet driver */
2eab48f5 WD	23
16b013e7 WD	24	/*
	25	* Size of malloc() pool
	26	*/
6d0f6bcf	27	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
16b013e7 WD	28
	29	/*
	30	* Hardware drivers
	31	*/
	32
	33	/*
	34	* select serial console configuration
	35	*/
93f6d725	36	#define CONFIG_ENV_IS_NOWHERE
176a600d	37	#define CONFIG_KS8695_SERIAL
16b013e7 WD	38	#define CONFIG_SERIAL1
	39	#define CONFIG_CONS_INDEX 1
	40	#define CONFIG_BAUDRATE 115200
37e4f24b	41
80ff4f99 JL	42	/*
	43	* BOOTP options
	44	*/
	45	#define CONFIG_BOOTP_BOOTFILESIZE
	46	#define CONFIG_BOOTP_BOOTPATH
	47	#define CONFIG_BOOTP_GATEWAY
	48	#define CONFIG_BOOTP_HOSTNAME
	49
	50
37e4f24b JL	51	/*
	52	* Command line configuration.
	53	*/
	54	#include <config_cmd_default.h>
	55
bdab39d3	56	#undef CONFIG_CMD_SAVEENV
37e4f24b	57
16b013e7 WD	58
	59	#define CONFIG_BOOTDELAY 0
	60	#define CONFIG_BOOTARGS "mem=32M console=ttyAM0,115200"
	61	#define CONFIG_BOOTCOMMAND "gofsk 0x02200000"
	62
	63	/*
	64	* Miscellaneous configurable options
	65	*/
6d0f6bcf JCPV	66	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	67	#define CONFIG_SYS_PROMPT "boot > " /* Monitor Command Prompt */
	68	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	69	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	70	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	71	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
16b013e7	72
6d0f6bcf JCPV	73	#define CONFIG_SYS_MEMTEST_START 0x00800000 /* memtest works on */
6d0f6bcf JCPV	74	#define CONFIG_SYS_MEMTEST_END 0x01000000 /* 16 MB in DRAM */
16b013e7	75
6d0f6bcf	76	#define CONFIG_SYS_LOAD_ADDR 0x00008000 /* default load address */
16b013e7	77
6d0f6bcf	78	#define CONFIG_SYS_HZ (1000) /* 1ms resolution ticks */
16b013e7	79
16b013e7 WD	80	/*-----------------------------------------------------------------------
	81	* Physical Memory Map
	82	*/
	83	#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
	84	#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
	85	#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
a34ebbda GU	86	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
	87
	88	#define CONFIG_SYS_INIT_SP_ADDR 0x00020000 /* lowest 128k of RAM */
16b013e7 WD	89
	90	#define PHYS_FLASH_1 0x02000000 /* Flash Bank #1 */
	91	#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 128 KB sectors (x1) */
6d0f6bcf	92	#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
16b013e7 WD	93
	94	/*-----------------------------------------------------------------------
	95	* FLASH and environment organization
	96	*/
6d0f6bcf JCPV	97	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
6d0f6bcf JCPV	98	#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
16b013e7 WD	99
16b013e7 WD	100	/* timeout values are in ticks */
6d0f6bcf JCPV	101	#define CONFIG_SYS_FLASH_ERASE_TOUT (20CONFIG_SYS_HZ) / Timeout for Flash Erase */
6d0f6bcf JCPV	102	#define CONFIG_SYS_FLASH_WRITE_TOUT (20CONFIG_SYS_HZ) / Timeout for Flash Write */
16b013e7	103
0e8d1586	104	#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment */
16b013e7 WD	105
16b013e7 WD	106	#endif /* __CONFIG_H */