[J-u-boot.git] / include / configs / ASH405.h

/*
 * (C) Copyright 2001-2003
 * Stefan Roese, esd gmbh germany, [email protected]
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
#define CONFIG_ASH405		1	/* ...on a ASH405 board		*/

#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000

#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/

#define CONFIG_SYS_CLK_FREQ	33333300 /* external frequency to pll	*/

#define CONFIG_BAUDRATE		9600
#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/

#undef	CONFIG_BOOTARGS
#undef  CONFIG_BOOTCOMMAND

#define CONFIG_PREBOOT                  /* enable preboot variable      */

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/

#undef  CONFIG_HAS_ETH1

#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII		1	/* MII PHY management		*/
#define CONFIG_PHY_ADDR		0	/* PHY address			*/
#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
#define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */

#define CONFIG_PHY_CLK_FREQ	EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_DHCP
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_ELF
#define CONFIG_CMD_NAND
#define CONFIG_CMD_DATE
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_EEPROM


#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/

#define CONFIG_RTC_MC146818		/* DS1685 is MC146818 compatible*/
#define CONFIG_SYS_RTC_REG_BASE_ADDR	 0xF0000500 /* RTC Base Address		*/

#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/

#undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/

#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/

#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_serial_clock()

#undef	CONFIG_SYS_EXT_SERIAL_CLOCK	       /* no external serial clock used */
#define CONFIG_SYS_BASE_BAUD	    691200

/* The following table includes the supported baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE	\
	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
	 57600, 115200, 230400, 460800, 921600 }

#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */

#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */

#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */

#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */

#define CONFIG_SYS_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */

/*-----------------------------------------------------------------------
 * NAND-FLASH stuff
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE	1         /* Max number of NAND devices */
#define NAND_BIG_DELAY_US	25

#define CONFIG_SYS_NAND_CE             (0x80000000 >> 1)   /* our CE is GPIO1  */
#define CONFIG_SYS_NAND_RDY            (0x80000000 >> 4)   /* our RDY is GPIO4 */
#define CONFIG_SYS_NAND_CLE            (0x80000000 >> 2)   /* our CLE is GPIO2 */
#define CONFIG_SYS_NAND_ALE            (0x80000000 >> 3)   /* our ALE is GPIO3 */

#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I	1	/* ".i" read skips bad blocks   */
#define CONFIG_SYS_NAND_QUIET		1

/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
#define PCI_HOST_ADAPTER 0		/* configure as pci adapter	*/
#define PCI_HOST_FORCE	1		/* configure as pci host	*/
#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/

#define CONFIG_PCI			/* include pci support		*/
#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
#define CONFIG_PCI_HOST PCI_HOST_HOST	/* select pci host function	*/
#undef	CONFIG_PCI_PNP			/* do pci plug-and-play		*/
					/* resource configuration	*/

#undef	CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/

#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405	/* PCI Device ID: CPCI-405	*/
#define CONFIG_SYS_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
#define CONFIG_SYS_PCI_PTM1LA	0x00000000	/* point to sdram		*/
#define CONFIG_SYS_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
#define CONFIG_SYS_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
#define CONFIG_SYS_PCI_PTM2LA	0xffc00000	/* point to flash		*/
#define CONFIG_SYS_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
#define CONFIG_SYS_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_FLASH_BASE		0xFFFC0000
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/

#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
/*
 * The following defines are added for buggy IOP480 byte interface.
 * All other boards should use the standard values (CPCI405 etc.)
 */
#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/

#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */

#if 0 /* test-only */
#define CONFIG_SYS_JFFS2_FIRST_BANK	0	    /* use for JFFS2 */
#define CONFIG_SYS_JFFS2_NUM_BANKS	1	    /* ! second bank contains U-Boot */
#endif

/*-----------------------------------------------------------------------
 * Environment Variable setup
 */
#define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
#define CONFIG_ENV_OFFSET		0x100	/* environment starts at the beginning of the EEPROM */
#define CONFIG_ENV_SIZE		0x700	/* 2048 bytes may be used for env vars*/
				   /* total size of a CAT24WC16 is 2048 bytes */

#define CONFIG_SYS_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
#define CONFIG_SYS_NVRAM_SIZE		242			/* NVRAM size		*/

/*-----------------------------------------------------------------------
 * I2C EEPROM (CAT24WC16) for environment
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_PPC4XX
#define CONFIG_SYS_I2C_PPC4XX_CH0
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F

#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
/* mask of address bits that overflow into the "EEPROM chip address"	*/
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
					/* 16 byte page write mode using*/
					/* last 4 bits of the address	*/
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */

/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */

#define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/

/*-----------------------------------------------------------------------
 * External Bus Controller (EBC) Setup
 */

/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
#define CONFIG_SYS_EBC_PB0AP		0x92015480
/*#define CONFIG_SYS_EBC_PB0AP		  0x08055880  /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
#define CONFIG_SYS_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */

/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization			*/
#define CONFIG_SYS_EBC_PB1AP		0x92015480
#define CONFIG_SYS_EBC_PB1CR		0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit	*/

/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization		*/
#define CONFIG_SYS_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
#define CONFIG_SYS_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/

/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization	*/
#define CONFIG_SYS_EBC_PB3AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
#define CONFIG_SYS_EBC_PB3CR		0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */

#define CAN_BA		0xF0000000	    /* CAN Base Address			*/
#define DUART0_BA	0xF0000400	    /* DUART Base Address		*/
#define DUART1_BA	0xF0000408	    /* DUART Base Address		*/
#define DUART2_BA	0xF0000410	    /* DUART Base Address		*/
#define DUART3_BA	0xF0000418	    /* DUART Base Address		*/
#define RTC_BA		0xF0000500	    /* RTC Base Address			*/
#define CONFIG_SYS_NAND_BASE	0xF4000000

/*-----------------------------------------------------------------------
 * FPGA stuff
 */
#define CONFIG_SYS_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
#define CONFIG_SYS_FPGA_MAX_SIZE	128*1024    /* 128kByte is enough for XC2S50E*/

/* FPGA program pin configuration */
#define CONFIG_SYS_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
#define CONFIG_SYS_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
#define CONFIG_SYS_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
#define CONFIG_SYS_FPGA_INIT		0x00010000  /* FPGA init pin (ppc input)     */
#define CONFIG_SYS_FPGA_DONE		0x00008000  /* FPGA done pin (ppc input)     */

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in data cache)
 */
/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
#define CONFIG_SYS_TEMP_STACK_OCM	  1

/* On Chip Memory location */
#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/

#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Definitions for GPIO setup (PPC405EP specific)
 *
 * GPIO0[0]	- External Bus Controller BLAST output
 * GPIO0[1-9]	- Instruction trace outputs -> GPIO
 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
 * GPIO0[24-27] - UART0 control signal inputs/outputs
 * GPIO0[28-29] - UART1 data signal input/output
 * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
 */
#define CONFIG_SYS_GPIO0_OSRL		0x40000550
#define CONFIG_SYS_GPIO0_OSRH		0x00000110
#define CONFIG_SYS_GPIO0_ISR1L		0x00000000
#define CONFIG_SYS_GPIO0_ISR1H		0x15555445
#define CONFIG_SYS_GPIO0_TSRL		0x00000000
#define CONFIG_SYS_GPIO0_TSRH		0x00000000
#define CONFIG_SYS_GPIO0_TCR		0xF7FE0014

#define CONFIG_SYS_DUART_RST		(0x80000000 >> 14)

/*
 * Default speed selection (cpu_plb_opb_ebc) in mhz.
 * This value will be set if iic boot eprom is disabled.
 */
#if 0
#define PLLMR0_DEFAULT	 PLLMR0_266_133_66_33
#define PLLMR1_DEFAULT	 PLLMR1_266_133_66_33
#endif
#if 1
#define PLLMR0_DEFAULT	 PLLMR0_200_100_50_33
#define PLLMR1_DEFAULT	 PLLMR1_200_100_50_33
#endif
#if 0
#define PLLMR0_DEFAULT	 PLLMR0_133_66_66_33
#define PLLMR1_DEFAULT	 PLLMR1_133_66_66_33
#endif

#endif	/* __CONFIG_H */
Commit	Line	Data
c93f7096 SR	1	/*
	2	* (C) Copyright 2001-2003
	3	* Stefan Roese, esd gmbh germany, [email protected]
	4	*
3765b3e7	5	* SPDX-License-Identifier: GPL-2.0+
c93f7096 SR	6	*/
	7
	8	/*
	9	* board/config.h - configuration options, board specific
	10	*/
	11
	12	#ifndef __CONFIG_H
	13	#define __CONFIG_H
	14
	15	/*
	16	* High Level Configuration Options
	17	* (easy to change)
	18	*/
	19
	20	#define CONFIG_405EP 1 /* This is a PPC405 CPU */
c837dcb1 WD	21	#define CONFIG_4xx 1 /* ...member of PPC4xx family */
c837dcb1 WD	22	#define CONFIG_ASH405 1 /* ...on a ASH405 board */
c93f7096	23
2ae18241 WD	24	#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
2ae18241 WD	25
c837dcb1 WD	26	#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
c837dcb1 WD	27	#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
c93f7096	28
a20b27a3	29	#define CONFIG_SYS_CLK_FREQ 33333300 /* external frequency to pll */
c93f7096 SR	30
	31	#define CONFIG_BAUDRATE 9600
	32	#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
	33
	34	#undef CONFIG_BOOTARGS
a20b27a3 SR	35	#undef CONFIG_BOOTCOMMAND
	36
	37	#define CONFIG_PREBOOT /* enable preboot variable */
c93f7096 SR	38
c93f7096 SR	39	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	40	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
c93f7096	41
bd84ee4c MF	42	#undef CONFIG_HAS_ETH1
bd84ee4c MF	43
96e21f86	44	#define CONFIG_PPC4xx_EMAC
c93f7096	45	#define CONFIG_MII 1 /* MII PHY management */
c837dcb1	46	#define CONFIG_PHY_ADDR 0 /* PHY address */
a20b27a3	47	#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
bd84ee4c	48	#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
a20b27a3 SR	49
a20b27a3 SR	50	#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
c93f7096	51
498ff9a2	52
11799434 JL	53	/*
	54	* BOOTP options
	55	*/
	56	#define CONFIG_BOOTP_BOOTFILESIZE
	57	#define CONFIG_BOOTP_BOOTPATH
	58	#define CONFIG_BOOTP_GATEWAY
	59	#define CONFIG_BOOTP_HOSTNAME
	60
	61
498ff9a2 JL	62	/*
	63	* Command line configuration.
	64	*/
	65	#include <config_cmd_default.h>
	66
	67	#define CONFIG_CMD_DHCP
	68	#define CONFIG_CMD_IRQ
	69	#define CONFIG_CMD_ELF
	70	#define CONFIG_CMD_NAND
	71	#define CONFIG_CMD_DATE
	72	#define CONFIG_CMD_I2C
	73	#define CONFIG_CMD_MII
	74	#define CONFIG_CMD_PING
	75	#define CONFIG_CMD_EEPROM
	76
c93f7096	77
c837dcb1	78	#undef CONFIG_WATCHDOG /* watchdog disabled */
c93f7096	79
c837dcb1	80	#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
6d0f6bcf	81	#define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */
c93f7096	82
c837dcb1	83	#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
c93f7096 SR	84
	85	/*
	86	* Miscellaneous configurable options
	87	*/
6d0f6bcf JCPV	88	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	89	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
c93f7096	90
6d0f6bcf	91	#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
c93f7096	92
498ff9a2	93	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	94	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
c93f7096	95	#else
6d0f6bcf	96	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
c93f7096	97	#endif
6d0f6bcf JCPV	98	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	99	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	100	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
c93f7096	101
6d0f6bcf	102	#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
c93f7096	103
6d0f6bcf	104	#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
c93f7096	105
6d0f6bcf JCPV	106	#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
6d0f6bcf JCPV	107	#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
c93f7096	108
550650dd SR	109	#define CONFIG_CONS_INDEX 1 /* Use UART0 */
	110	#define CONFIG_SYS_NS16550
	111	#define CONFIG_SYS_NS16550_SERIAL
	112	#define CONFIG_SYS_NS16550_REG_SIZE 1
	113	#define CONFIG_SYS_NS16550_CLK get_serial_clock()
	114
6d0f6bcf	115	#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
6d0f6bcf	116	#define CONFIG_SYS_BASE_BAUD 691200
c93f7096 SR	117
c93f7096 SR	118	/* The following table includes the supported baudrates */
6d0f6bcf	119	#define CONFIG_SYS_BAUDRATE_TABLE \
8bde7f77 WD	120	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
8bde7f77 WD	121	57600, 115200, 230400, 460800, 921600 }
c93f7096	122
6d0f6bcf JCPV	123	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
6d0f6bcf JCPV	124	#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
c93f7096	125
6d0f6bcf	126	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
c93f7096 SR	127
	128	#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
	129
c837dcb1	130	#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
53cf9435	131
6d0f6bcf	132	#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
53cf9435	133
c93f7096 SR	134	/*-----------------------------------------------------------------------
	135	* NAND-FLASH stuff
	136	*-----------------------------------------------------------------------
	137	*/
6d0f6bcf	138	#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
6d0f6bcf	139	#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
bd84ee4c	140	#define NAND_BIG_DELAY_US 25
addb2e16	141
6d0f6bcf JCPV	142	#define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
	143	#define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
	144	#define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
	145	#define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
c93f7096	146
170c1972 WD	147	#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
	148	#define CONFIG_SYS_NAND_QUIET 1
	149
c93f7096 SR	150	/*-----------------------------------------------------------------------
	151	* PCI stuff
	152	*-----------------------------------------------------------------------
	153	*/
c837dcb1 WD	154	#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
	155	#define PCI_HOST_FORCE 1 /* configure as pci host */
	156	#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
	157
	158	#define CONFIG_PCI /* include pci support */
842033e6	159	#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
c837dcb1 WD	160	#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */
	161	#undef CONFIG_PCI_PNP /* do pci plug-and-play */
	162	/* resource configuration */
	163
	164	#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
	165
6d0f6bcf JCPV	166	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
	167	#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
	168	#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
	169	#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
	170	#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
	171	#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
	172	#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
	173	#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
	174	#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
c93f7096 SR	175
	176	/*-----------------------------------------------------------------------
	177	* Start addresses for the final memory configuration
	178	* (Set up by the startup code)
6d0f6bcf	179	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
c93f7096	180	*/
6d0f6bcf JCPV	181	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	182	#define CONFIG_SYS_FLASH_BASE 0xFFFC0000
	183	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	184	#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
	185	#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
c93f7096 SR	186
	187	/*
	188	* For booting Linux, the board info and command line data
	189	* have to be in the first 8 MB of memory, since this is
	190	* the maximum mapped by the Linux kernel during initialization.
	191	*/
6d0f6bcf	192	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
c93f7096 SR	193	/*-----------------------------------------------------------------------
	194	* FLASH organization
	195	*/
6d0f6bcf JCPV	196	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
6d0f6bcf JCPV	197	#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
c93f7096	198
6d0f6bcf JCPV	199	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	200	#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
c93f7096	201
6d0f6bcf JCPV	202	#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
	203	#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
	204	#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
c93f7096 SR	205	/*
	206	* The following defines are added for buggy IOP480 byte interface.
	207	* All other boards should use the standard values (CPCI405 etc.)
	208	*/
6d0f6bcf JCPV	209	#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
	210	#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
	211	#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
c93f7096	212
6d0f6bcf	213	#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
c93f7096 SR	214
c93f7096 SR	215	#if 0 /* test-only */
6d0f6bcf JCPV	216	#define CONFIG_SYS_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
6d0f6bcf JCPV	217	#define CONFIG_SYS_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
c93f7096 SR	218	#endif
	219
	220	/*-----------------------------------------------------------------------
	221	* Environment Variable setup
	222	*/
bb1f8b4f	223	#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
0e8d1586 JCPV	224	#define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
0e8d1586 JCPV	225	#define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
8bde7f77	226	/* total size of a CAT24WC16 is 2048 bytes */
c93f7096	227
6d0f6bcf JCPV	228	#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
6d0f6bcf JCPV	229	#define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */
c93f7096 SR	230
	231	/*-----------------------------------------------------------------------
	232	* I2C EEPROM (CAT24WC16) for environment
	233	*/
880540de DE	234	#define CONFIG_SYS_I2C
	235	#define CONFIG_SYS_I2C_PPC4XX
	236	#define CONFIG_SYS_I2C_PPC4XX_CH0
	237	#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
	238	#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
c93f7096	239
6d0f6bcf JCPV	240	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
6d0f6bcf JCPV	241	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
c837dcb1	242	/* mask of address bits that overflow into the "EEPROM chip address" */
6d0f6bcf JCPV	243	#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
6d0f6bcf JCPV	244	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
c93f7096	245	/* 16 byte page write mode using*/
c837dcb1	246	/* last 4 bits of the address */
6d0f6bcf	247	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
c93f7096	248
c93f7096 SR	249	/*
	250	* Init Memory Controller:
	251	*
	252	* BR0/1 and OR0/1 (FLASH)
	253	*/
	254
	255	#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
	256
	257	/*-----------------------------------------------------------------------
	258	* External Bus Controller (EBC) Setup
	259	*/
	260
c837dcb1	261	/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
6d0f6bcf JCPV	262	#define CONFIG_SYS_EBC_PB0AP 0x92015480
	263	/#define CONFIG_SYS_EBC_PB0AP 0x08055880 /XXX TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
	264	#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
c93f7096	265
c837dcb1	266	/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */
6d0f6bcf JCPV	267	#define CONFIG_SYS_EBC_PB1AP 0x92015480
6d0f6bcf JCPV	268	#define CONFIG_SYS_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */
c93f7096	269
c837dcb1	270	/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */
6d0f6bcf JCPV	271	#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
6d0f6bcf JCPV	272	#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
c93f7096	273
c837dcb1	274	/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */
6d0f6bcf JCPV	275	#define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
6d0f6bcf JCPV	276	#define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
c93f7096	277
c837dcb1 WD	278	#define CAN_BA 0xF0000000 /* CAN Base Address */
	279	#define DUART0_BA 0xF0000400 /* DUART Base Address */
	280	#define DUART1_BA 0xF0000408 /* DUART Base Address */
	281	#define DUART2_BA 0xF0000410 /* DUART Base Address */
	282	#define DUART3_BA 0xF0000418 /* DUART Base Address */
	283	#define RTC_BA 0xF0000500 /* RTC Base Address */
6d0f6bcf	284	#define CONFIG_SYS_NAND_BASE 0xF4000000
c93f7096 SR	285
	286	/*-----------------------------------------------------------------------
	287	* FPGA stuff
	288	*/
6d0f6bcf JCPV	289	#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
6d0f6bcf JCPV	290	#define CONFIG_SYS_FPGA_MAX_SIZE 1281024 / 128kByte is enough for XC2S50E*/
c93f7096 SR	291
c93f7096 SR	292	/* FPGA program pin configuration */
6d0f6bcf JCPV	293	#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
	294	#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
	295	#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
	296	#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
	297	#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
c93f7096 SR	298
	299	/*-----------------------------------------------------------------------
	300	* Definitions for initial stack pointer and data area (in data cache)
	301	*/
	302	/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
6d0f6bcf	303	#define CONFIG_SYS_TEMP_STACK_OCM 1
c93f7096 SR	304
c93f7096 SR	305	/* On Chip Memory location */
6d0f6bcf JCPV	306	#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
	307	#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
	308	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
553f0982	309	#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
c93f7096	310
25ddd1fb	311	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	312	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
c93f7096 SR	313
	314	/*-----------------------------------------------------------------------
	315	* Definitions for GPIO setup (PPC405EP specific)
	316	*
c837dcb1 WD	317	* GPIO0[0] - External Bus Controller BLAST output
c837dcb1 WD	318	* GPIO0[1-9] - Instruction trace outputs -> GPIO
c93f7096 SR	319	* GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
	320	* GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
	321	* GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
	322	* GPIO0[24-27] - UART0 control signal inputs/outputs
	323	* GPIO0[28-29] - UART1 data signal input/output
	324	* GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
	325	*/
afabb498 SR	326	#define CONFIG_SYS_GPIO0_OSRL 0x40000550
	327	#define CONFIG_SYS_GPIO0_OSRH 0x00000110
	328	#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
	329	#define CONFIG_SYS_GPIO0_ISR1H 0x15555445
6d0f6bcf	330	#define CONFIG_SYS_GPIO0_TSRL 0x00000000
afabb498	331	#define CONFIG_SYS_GPIO0_TSRH 0x00000000
6d0f6bcf JCPV	332	#define CONFIG_SYS_GPIO0_TCR 0xF7FE0014
	333
	334	#define CONFIG_SYS_DUART_RST (0x80000000 >> 14)
c93f7096	335
c93f7096 SR	336	/*
	337	* Default speed selection (cpu_plb_opb_ebc) in mhz.
	338	* This value will be set if iic boot eprom is disabled.
	339	*/
	340	#if 0
c837dcb1 WD	341	#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
c837dcb1 WD	342	#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
c93f7096 SR	343	#endif
c93f7096 SR	344	#if 1
c837dcb1 WD	345	#define PLLMR0_DEFAULT PLLMR0_200_100_50_33
c837dcb1 WD	346	#define PLLMR1_DEFAULT PLLMR1_200_100_50_33
c93f7096 SR	347	#endif
c93f7096 SR	348	#if 0
c837dcb1 WD	349	#define PLLMR0_DEFAULT PLLMR0_133_66_66_33
c837dcb1 WD	350	#define PLLMR1_DEFAULT PLLMR1_133_66_66_33
c93f7096 SR	351	#endif
	352
	353	#endif /* __CONFIG_H */