projects / J-u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| ab4c62c1 DE |
1 | /* |
| 2 | * (C) Copyright 2009 | |
| 3 | * Dirk Eibach, Guntermann & Drunck GmbH, [email protected] | |
| 4 | * | |
| 5 | * Based on board/amcc/canyonlands/init.S | |
| 6 | * (C) Copyright 2008 | |
| 7 | * Stefan Roese, DENX Software Engineering, [email protected]. | |
| 8 | * | |
| 3765b3e7 | 9 | * SPDX-License-Identifier: GPL-2.0+ |
| ab4c62c1 DE |
10 | */ |
| 11 | ||
| 25ddd1fb | 12 | #include <asm-offsets.h> |
| ab4c62c1 DE |
13 | #include <ppc_asm.tmpl> |
| 14 | #include <config.h> | |
| 61f2b38a | 15 | #include <asm/mmu.h> |
| ab4c62c1 DE |
16 | |
| 17 | /************************************************************************** | |
| 18 | * TLB TABLE | |
| 19 | * | |
| 20 | * This table is used by the cpu boot code to setup the initial tlb | |
| 21 | * entries. Rather than make broad assumptions in the cpu source tree, | |
| 22 | * this table lets each board set things up however they like. | |
| 23 | * | |
| 24 | * Pointer to the table is returned in r1 | |
| 25 | * | |
| 26 | *************************************************************************/ | |
| 27 | .section .bootpg,"ax" | |
| 28 | .globl tlbtab | |
| 29 | ||
| 30 | tlbtab: | |
| 31 | tlbtab_start | |
| 32 | ||
| 33 | /* | |
| 34 | * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to | |
| 35 | * use the speed up boot process. It is patched after relocation to | |
| 36 | * enable SA_I | |
| 37 | */ | |
| 38 | tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR, | |
| cf6eb6da | 39 | 4, AC_RWX | SA_G) /* TLB 0 */ |
| ab4c62c1 DE |
40 | |
| 41 | /* | |
| 42 | * TLB entries for SDRAM are not needed on this platform. | |
| 43 | * They are dynamically generated in the SPD DDR(2) detection | |
| 44 | * routine. | |
| 45 | */ | |
| 46 | ||
| 47 | #ifdef CONFIG_SYS_INIT_RAM_DCACHE | |
| 48 | /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ | |
| 49 | tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, | |
| cf6eb6da | 50 | 0, AC_RWX | SA_G) |
| ab4c62c1 DE |
51 | #endif |
| 52 | ||
| 53 | tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, | |
| cf6eb6da | 54 | AC_RW | SA_IG) |
| ab4c62c1 | 55 | tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x20000000, 0xC, |
| cf6eb6da | 56 | AC_RW | SA_IG) |
| ab4c62c1 DE |
57 | |
| 58 | /* TLB-entry for NVRAM */ | |
| 59 | tlbentry(CONFIG_SYS_NVRAM_BASE, SZ_1M, CONFIG_SYS_NVRAM_BASE, 4, | |
| cf6eb6da | 60 | AC_RW | SA_IG) |
| ab4c62c1 DE |
61 | |
| 62 | /* TLB-entry for UART */ | |
| 63 | tlbentry(CONFIG_SYS_UART_BASE, SZ_16K, CONFIG_SYS_UART_BASE, 4, | |
| cf6eb6da | 64 | AC_RW | SA_IG) |
| ab4c62c1 DE |
65 | |
| 66 | /* TLB-entry for IO */ | |
| 67 | tlbentry(CONFIG_SYS_IO_BASE, SZ_16K, CONFIG_SYS_IO_BASE, 4, | |
| cf6eb6da | 68 | AC_RW | SA_IG) |
| ab4c62c1 DE |
69 | |
| 70 | /* TLB-entry for OCM */ | |
| 71 | tlbentry(CONFIG_SYS_OCM_BASE, SZ_1M, 0x00000000, 4, | |
| cf6eb6da | 72 | AC_RWX | SA_I) |
| ab4c62c1 DE |
73 | |
| 74 | /* TLB-entry for Local Configuration registers => peripherals */ | |
| 75 | tlbentry(CONFIG_SYS_LOCAL_CONF_REGS, SZ_16M, CONFIG_SYS_LOCAL_CONF_REGS, | |
| cf6eb6da | 76 | 4, AC_RWX | SA_IG) |
| ab4c62c1 DE |
77 | |
| 78 | /* AHB: Internal USB Peripherals (USB, SATA) */ | |
| 79 | tlbentry(CONFIG_SYS_AHB_BASE, SZ_1M, 0xbff00000, 4, | |
| cf6eb6da | 80 | AC_RWX | SA_IG) |
| ab4c62c1 DE |
81 | |
| 82 | tlbtab_end |