[J-u-boot.git] / board / amcc / ocotea / ocotea.c

/*
 *  Copyright (C) 2004 [email protected]
 *
 * (C) Copyright 2005
 * Stefan Roese, DENX Software Engineering, [email protected].
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */


#include <common.h>
#include "ocotea.h"
#include <asm/processor.h>
#include <spd_sdram.h>
#include <asm/ppc4xx-emac.h>

DECLARE_GLOBAL_DATA_PTR;

#define BOOT_SMALL_FLASH	32	/* 00100000 */
#define FLASH_ONBD_N		2	/* 00000010 */
#define FLASH_SRAM_SEL		1	/* 00000001 */

long int fixed_sdram (void);
void fpga_init (void);

int board_early_init_f (void)
{
	unsigned long mfr;
	unsigned char *fpga_base = (unsigned char *) CONFIG_SYS_FPGA_BASE;
	unsigned char switch_status;
	unsigned long cs0_base;
	unsigned long cs0_size;
	unsigned long cs0_twt;
	unsigned long cs2_base;
	unsigned long cs2_size;
	unsigned long cs2_twt;

	/*-------------------------------------------------------------------------+
	  | Initialize EBC CONFIG
	  +-------------------------------------------------------------------------*/
	mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK |
	      EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK |
	      EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS |
	      EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT |
	      EBC_CFG_PME_DISABLE | EBC_CFG_PR_32);

	/*-------------------------------------------------------------------------+
	  | FPGA. Initialize bank 7 with default values.
	  +-------------------------------------------------------------------------*/
	mtebc(PB7AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)|
	      EBC_BXAP_BCE_DISABLE|
	      EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
	      EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
	      EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
	      EBC_BXAP_BEM_WRITEONLY|
	      EBC_BXAP_PEN_DISABLED);
	mtebc(PB7CR, EBC_BXCR_BAS_ENCODE(0x48300000)|
	      EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);

	/* read FPGA base register FPGA_REG0 */
	switch_status = *fpga_base;

	if (switch_status & 0x40) {
		cs0_base = 0xFFE00000;
		cs0_size = EBC_BXCR_BS_2MB;
		cs0_twt = 8;
		cs2_base = 0xFF800000;
		cs2_size = EBC_BXCR_BS_4MB;
		cs2_twt = 10;
	} else {
		cs0_base = 0xFFC00000;
		cs0_size = EBC_BXCR_BS_4MB;
		cs0_twt = 10;
		cs2_base = 0xFF800000;
		cs2_size = EBC_BXCR_BS_2MB;
		cs2_twt = 8;
	}

	/*-------------------------------------------------------------------------+
	  | 1 MB FLASH / 1 MB SRAM. Initialize bank 0 with default values.
	  +-------------------------------------------------------------------------*/
	mtebc(PB0AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs0_twt)|
	      EBC_BXAP_BCE_DISABLE|
	      EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
	      EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
	      EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
	      EBC_BXAP_BEM_WRITEONLY|
	      EBC_BXAP_PEN_DISABLED);
	mtebc(PB0CR, EBC_BXCR_BAS_ENCODE(cs0_base)|
	      cs0_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);

	/*-------------------------------------------------------------------------+
	  | 8KB NVRAM/RTC. Initialize bank 1 with default values.
	  +-------------------------------------------------------------------------*/
	mtebc(PB1AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(10)|
	      EBC_BXAP_BCE_DISABLE|
	      EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
	      EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
	      EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
	      EBC_BXAP_BEM_WRITEONLY|
	      EBC_BXAP_PEN_DISABLED);
	mtebc(PB1CR, EBC_BXCR_BAS_ENCODE(0x48000000)|
	      EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);

	/*-------------------------------------------------------------------------+
	  | 4 MB FLASH. Initialize bank 2 with default values.
	  +-------------------------------------------------------------------------*/
	mtebc(PB2AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs2_twt)|
	      EBC_BXAP_BCE_DISABLE|
	      EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
	      EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
	      EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
	      EBC_BXAP_BEM_WRITEONLY|
	      EBC_BXAP_PEN_DISABLED);
	mtebc(PB2CR, EBC_BXCR_BAS_ENCODE(cs2_base)|
	      cs2_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);

	/*-------------------------------------------------------------------------+
	  | FPGA. Initialize bank 7 with default values.
	  +-------------------------------------------------------------------------*/
	mtebc(PB7AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)|
	      EBC_BXAP_BCE_DISABLE|
	      EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
	      EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
	      EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
	      EBC_BXAP_BEM_WRITEONLY|
	      EBC_BXAP_PEN_DISABLED);
	mtebc(PB7CR, EBC_BXCR_BAS_ENCODE(0x48300000)|
	      EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);

	/*--------------------------------------------------------------------
	 * Setup the interrupt controller polarities, triggers, etc.
	 *-------------------------------------------------------------------*/
	/*
	 * Because of the interrupt handling rework to handle 440GX interrupts
	 * with the common code, we needed to change names of the UIC registers.
	 * Here the new relationship:
	 *
	 * U-Boot name	440GX name
	 * -----------------------
	 * UIC0		UICB0
	 * UIC1		UIC0
	 * UIC2		UIC1
	 * UIC3		UIC2
	 */
	mtdcr (UIC1SR, 0xffffffff);	/* clear all */
	mtdcr (UIC1ER, 0x00000000);	/* disable all */
	mtdcr (UIC1CR, 0x00000009);	/* SMI & UIC1 crit are critical */
	mtdcr (UIC1PR, 0xfffffe13);	/* per ref-board manual */
	mtdcr (UIC1TR, 0x01c00008);	/* per ref-board manual */
	mtdcr (UIC1VR, 0x00000001);	/* int31 highest, base=0x000 */
	mtdcr (UIC1SR, 0xffffffff);	/* clear all */

	mtdcr (UIC2SR, 0xffffffff);	/* clear all */
	mtdcr (UIC2ER, 0x00000000);	/* disable all */
	mtdcr (UIC2CR, 0x00000000);	/* all non-critical */
	mtdcr (UIC2PR, 0xffffe0ff);	/* per ref-board manual */
	mtdcr (UIC2TR, 0x00ffc000);	/* per ref-board manual */
	mtdcr (UIC2VR, 0x00000001);	/* int31 highest, base=0x000 */
	mtdcr (UIC2SR, 0xffffffff);	/* clear all */

	mtdcr (UIC3SR, 0xffffffff);	/* clear all */
	mtdcr (UIC3ER, 0x00000000);	/* disable all */
	mtdcr (UIC3CR, 0x00000000);	/* all non-critical */
	mtdcr (UIC3PR, 0xffffffff);	/* per ref-board manual */
	mtdcr (UIC3TR, 0x00ff8c0f);	/* per ref-board manual */
	mtdcr (UIC3VR, 0x00000001);	/* int31 highest, base=0x000 */
	mtdcr (UIC3SR, 0xffffffff);	/* clear all */

	mtdcr (UIC0SR, 0xfc000000); /* clear all */
	mtdcr (UIC0ER, 0x00000000); /* disable all */
	mtdcr (UIC0CR, 0x00000000); /* all non-critical */
	mtdcr (UIC0PR, 0xfc000000); /* */
	mtdcr (UIC0TR, 0x00000000); /* */
	mtdcr (UIC0VR, 0x00000001); /* */
	mfsdr (SDR0_MFR, mfr);
	mfr &= ~SDR0_MFR_ECS_MASK;
/*	mtsdr(SDR0_MFR, mfr); */
	fpga_init();

	return 0;
}


int checkboard (void)
{
	char buf[64];
	int i = getenv_f("serial#", buf, sizeof(buf));

	printf ("Board: Ocotea - AMCC PPC440GX Evaluation Board");
	if (i > 0) {
		puts(", serial# ");
		puts(buf);
	}
	putc ('\n');

	return (0);
}


phys_size_t initdram (int board_type)
{
	long dram_size = 0;

#if defined(CONFIG_SPD_EEPROM)
	dram_size = spd_sdram ();
#else
	dram_size = fixed_sdram ();
#endif
	return dram_size;
}


#if !defined(CONFIG_SPD_EEPROM)
/*************************************************************************
 *  fixed sdram init -- doesn't use serial presence detect.
 *
 *  Assumes:    128 MB, non-ECC, non-registered
 *              PLB @ 133 MHz
 *
 ************************************************************************/
long int fixed_sdram (void)
{
	uint reg;

	/*--------------------------------------------------------------------
	 * Setup some default
	 *------------------------------------------------------------------*/
	mtsdram (SDRAM0_UABBA, 0x00000000);	/* ubba=0 (default)             */
	mtsdram (SDRAM0_SLIO, 0x00000000);		/* rdre=0 wrre=0 rarw=0         */
	mtsdram (SDRAM0_DEVOPT, 0x00000000);	/* dll=0 ds=0 (normal)          */
	mtsdram (SDRAM0_WDDCTR, 0x00000000);	/* wrcp=0 dcd=0                 */
	mtsdram (SDRAM0_CLKTR, 0x40000000);	/* clkp=1 (90 deg wr) dcdt=0    */

	/*--------------------------------------------------------------------
	 * Setup for board-specific specific mem
	 *------------------------------------------------------------------*/
	/*
	 * Following for CAS Latency = 2.5 @ 133 MHz PLB
	 */
	mtsdram (SDRAM0_B0CR, 0x000a4001);	/* SDBA=0x000 128MB, Mode 3, enabled */
	mtsdram (SDRAM0_TR0, 0x410a4012);	/* WR=2  WD=1 CL=2.5 PA=3 CP=4 LD=2 */
	/* RA=10 RD=3                       */
	mtsdram (SDRAM0_TR1, 0x8080082f);	/* SS=T2 SL=STAGE 3 CD=1 CT=0x02f   */
	mtsdram (SDRAM0_RTR, 0x08200000);	/* Rate 15.625 ns @ 133 MHz PLB     */
	mtsdram (SDRAM0_CFG1, 0x00000000);	/* Self-refresh exit, disable PM    */
	udelay (400);			/* Delay 200 usecs (min)            */

	/*--------------------------------------------------------------------
	 * Enable the controller, then wait for DCEN to complete
	 *------------------------------------------------------------------*/
	mtsdram (SDRAM0_CFG0, 0x86000000);	/* DCEN=1, PMUD=1, 64-bit           */
	for (;;) {
		mfsdram (SDRAM0_MCSTS, reg);
		if (reg & 0x80000000)
			break;
	}

	return (128 * 1024 * 1024);	/* 128 MB                           */
}
#endif	/* !defined(CONFIG_SPD_EEPROM) */

void fpga_init(void)
{
	unsigned long group;
	unsigned long sdr0_pfc0;
	unsigned long sdr0_pfc1;
	unsigned long sdr0_cust0;
	unsigned long pvr;

	mfsdr (SDR0_PFC0, sdr0_pfc0);
	mfsdr (SDR0_PFC1, sdr0_pfc1);
	group = SDR0_PFC1_EPS_DECODE(sdr0_pfc1);
	pvr = get_pvr ();

	sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_GEIE_MASK) | SDR0_PFC0_GEIE_TRE;
	if ( ((pvr == PVR_440GX_RA) || (pvr == PVR_440GX_RB)) && ((group == 4) || (group == 5))) {
		sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) | SDR0_PFC0_TRE_DISABLE;
		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS;
		out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
		     FPGA_REG2_EXT_INTFACE_ENABLE);
		mtsdr (SDR0_PFC0, sdr0_pfc0);
		mtsdr (SDR0_PFC1, sdr0_pfc1);
	} else {
		sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) | SDR0_PFC0_TRE_ENABLE;
		switch (group)
		{
		case 0:
		case 1:
		case 2:
			/* CPU trace A */
			out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
			     FPGA_REG2_EXT_INTFACE_ENABLE);
			sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS;
			mtsdr (SDR0_PFC0, sdr0_pfc0);
			mtsdr (SDR0_PFC1, sdr0_pfc1);
			break;
		case 3:
		case 4:
		case 5:
		case 6:
			/* CPU trace B - Over EBMI */
			sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_CPUTRACE;
			mtsdr (SDR0_PFC0, sdr0_pfc0);
			mtsdr (SDR0_PFC1, sdr0_pfc1);
			out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
			     FPGA_REG2_EXT_INTFACE_DISABLE);
			break;
		}
	}

	/* Initialize the ethernet specific functions in the fpga */
	mfsdr(SDR0_PFC1, sdr0_pfc1);
	mfsdr(SDR0_CUST0, sdr0_cust0);
	if ( (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) == 4) &&
	    ((SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII) ||
	     (SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_TBI)))
	{
		if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
		{
			out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK1) |
			     FPGA_REG3_ENET_GROUP7);
		}
		else
		{
			if (SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII)
			{
				out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) |
				     FPGA_REG3_ENET_GROUP7);
			}
			else
			{
				out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) |
				     FPGA_REG3_ENET_GROUP8);
			}
		}
	}
	else
	{
		if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
		{
			out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK1) |
			     FPGA_REG3_ENET_ENCODE1(SDR0_PFC1_EPS_DECODE(sdr0_pfc1)));
		}
		else
		{
			out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) |
			     FPGA_REG3_ENET_ENCODE2(SDR0_PFC1_EPS_DECODE(sdr0_pfc1)));
		}
	}
	out8(FPGA_REG4, FPGA_REG4_GPHY_MODE10 |
	     FPGA_REG4_GPHY_MODE100 | FPGA_REG4_GPHY_MODE1000 |
	     FPGA_REG4_GPHY_FRC_DPLX | FPGA_REG4_CONNECT_PHYS);

	/* reset the gigabyte phy if necessary */
	if (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) >= 3)
	{
		if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
		{
			out8(FPGA_REG3, in8(FPGA_REG3) & ~FPGA_REG3_GIGABIT_RESET_DISABLE);
			udelay(10000);
			out8(FPGA_REG3, in8(FPGA_REG3) | FPGA_REG3_GIGABIT_RESET_DISABLE);
		}
		else
		{
			out8(FPGA_REG2, in8(FPGA_REG2) & ~FPGA_REG2_GIGABIT_RESET_DISABLE);
			udelay(10000);
			out8(FPGA_REG2, in8(FPGA_REG2) | FPGA_REG2_GIGABIT_RESET_DISABLE);
		}
	}

	/*
	 * new Ocotea with Rev. F (pass 3) chips has SMII PHY reset
	 */
	if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER2) {
		out8(FPGA_REG2, in8(FPGA_REG2) & ~FPGA_REG2_SMII_RESET_DISABLE);
		udelay(10000);
		out8(FPGA_REG2, in8(FPGA_REG2) | FPGA_REG2_SMII_RESET_DISABLE);
	}

	/* Turn off the LED's */
	out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_STAT_MASK) |
	     FPGA_REG3_STAT_LED8_DISAB | FPGA_REG3_STAT_LED4_DISAB |
	     FPGA_REG3_STAT_LED2_DISAB | FPGA_REG3_STAT_LED1_DISAB);

	return;
}
Commit	Line	Data
0e6d798c WD	1	/*
	2	* Copyright (C) 2004 [email protected]
	3	*
8a316c9b SR	4	* (C) Copyright 2005
	5	* Stefan Roese, DENX Software Engineering, [email protected].
	6	*
3765b3e7	7	* SPDX-License-Identifier: GPL-2.0+
0e6d798c WD	8	*/
	9
	10
	11	#include <common.h>
	12	#include "ocotea.h"
	13	#include <asm/processor.h>
	14	#include <spd_sdram.h>
b36df561	15	#include <asm/ppc4xx-emac.h>
0e6d798c	16
d87080b7 WD	17	DECLARE_GLOBAL_DATA_PTR;
d87080b7 WD	18
0e6d798c WD	19	#define BOOT_SMALL_FLASH 32 /* 00100000 */
	20	#define FLASH_ONBD_N 2 /* 00000010 */
	21	#define FLASH_SRAM_SEL 1 /* 00000001 */
	22
	23	long int fixed_sdram (void);
	24	void fpga_init (void);
	25
	26	int board_early_init_f (void)
	27	{
4b248f3f	28	unsigned long mfr;
6d0f6bcf	29	unsigned char fpga_base = (unsigned char ) CONFIG_SYS_FPGA_BASE;
7ec25502 SR	30	unsigned char switch_status;
	31	unsigned long cs0_base;
	32	unsigned long cs0_size;
	33	unsigned long cs0_twt;
	34	unsigned long cs2_base;
	35	unsigned long cs2_size;
	36	unsigned long cs2_twt;
	37
0e6d798c WD	38	/*-------------------------------------------------------------------------+
	39	\| Initialize EBC CONFIG
	40	+-------------------------------------------------------------------------*/
d1c3b275	41	mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK \|
0e6d798c WD	42	EBC_CFG_PTD_ENABLE \| EBC_CFG_RTC_64PERCLK \|
	43	EBC_CFG_ATC_PREVIOUS \| EBC_CFG_DTC_PREVIOUS \|
	44	EBC_CFG_CTC_PREVIOUS \| EBC_CFG_EMC_NONDEFAULT \|
	45	EBC_CFG_PME_DISABLE \| EBC_CFG_PR_32);
	46
7ec25502 SR	47	/*-------------------------------------------------------------------------+
	48	\| FPGA. Initialize bank 7 with default values.
	49	+-------------------------------------------------------------------------*/
d1c3b275	50	mtebc(PB7AP, EBC_BXAP_BME_DISABLED\|EBC_BXAP_TWT_ENCODE(7)\|
7ec25502 SR	51	EBC_BXAP_BCE_DISABLE\|
	52	EBC_BXAP_CSN_ENCODE(1)\|EBC_BXAP_OEN_ENCODE(1)\|
	53	EBC_BXAP_WBN_ENCODE(1)\|EBC_BXAP_WBF_ENCODE(1)\|
	54	EBC_BXAP_TH_ENCODE(1)\|EBC_BXAP_RE_DISABLED\|
	55	EBC_BXAP_BEM_WRITEONLY\|
	56	EBC_BXAP_PEN_DISABLED);
d1c3b275	57	mtebc(PB7CR, EBC_BXCR_BAS_ENCODE(0x48300000)\|
7ec25502 SR	58	EBC_BXCR_BS_1MB\|EBC_BXCR_BU_RW\|EBC_BXCR_BW_8BIT);
	59
	60	/* read FPGA base register FPGA_REG0 */
	61	switch_status = *fpga_base;
	62
	63	if (switch_status & 0x40) {
	64	cs0_base = 0xFFE00000;
	65	cs0_size = EBC_BXCR_BS_2MB;
	66	cs0_twt = 8;
	67	cs2_base = 0xFF800000;
	68	cs2_size = EBC_BXCR_BS_4MB;
	69	cs2_twt = 10;
	70	} else {
	71	cs0_base = 0xFFC00000;
	72	cs0_size = EBC_BXCR_BS_4MB;
	73	cs0_twt = 10;
	74	cs2_base = 0xFF800000;
	75	cs2_size = EBC_BXCR_BS_2MB;
	76	cs2_twt = 8;
	77	}
	78
0e6d798c WD	79	/*-------------------------------------------------------------------------+
	80	\| 1 MB FLASH / 1 MB SRAM. Initialize bank 0 with default values.
	81	+-------------------------------------------------------------------------*/
d1c3b275	82	mtebc(PB0AP, EBC_BXAP_BME_DISABLED\|EBC_BXAP_TWT_ENCODE(cs0_twt)\|
0e6d798c WD	83	EBC_BXAP_BCE_DISABLE\|
	84	EBC_BXAP_CSN_ENCODE(1)\|EBC_BXAP_OEN_ENCODE(1)\|
	85	EBC_BXAP_WBN_ENCODE(1)\|EBC_BXAP_WBF_ENCODE(1)\|
	86	EBC_BXAP_TH_ENCODE(1)\|EBC_BXAP_RE_DISABLED\|
	87	EBC_BXAP_BEM_WRITEONLY\|
	88	EBC_BXAP_PEN_DISABLED);
d1c3b275	89	mtebc(PB0CR, EBC_BXCR_BAS_ENCODE(cs0_base)\|
7ec25502	90	cs0_size\|EBC_BXCR_BU_RW\|EBC_BXCR_BW_8BIT);
0e6d798c WD	91
	92	/*-------------------------------------------------------------------------+
	93	\| 8KB NVRAM/RTC. Initialize bank 1 with default values.
	94	+-------------------------------------------------------------------------*/
d1c3b275	95	mtebc(PB1AP, EBC_BXAP_BME_DISABLED\|EBC_BXAP_TWT_ENCODE(10)\|
0e6d798c WD	96	EBC_BXAP_BCE_DISABLE\|
	97	EBC_BXAP_CSN_ENCODE(1)\|EBC_BXAP_OEN_ENCODE(1)\|
	98	EBC_BXAP_WBN_ENCODE(1)\|EBC_BXAP_WBF_ENCODE(1)\|
	99	EBC_BXAP_TH_ENCODE(1)\|EBC_BXAP_RE_DISABLED\|
	100	EBC_BXAP_BEM_WRITEONLY\|
	101	EBC_BXAP_PEN_DISABLED);
d1c3b275	102	mtebc(PB1CR, EBC_BXCR_BAS_ENCODE(0x48000000)\|
0e6d798c WD	103	EBC_BXCR_BS_1MB\|EBC_BXCR_BU_RW\|EBC_BXCR_BW_8BIT);
	104
	105	/*-------------------------------------------------------------------------+
	106	\| 4 MB FLASH. Initialize bank 2 with default values.
	107	+-------------------------------------------------------------------------*/
d1c3b275	108	mtebc(PB2AP, EBC_BXAP_BME_DISABLED\|EBC_BXAP_TWT_ENCODE(cs2_twt)\|
0e6d798c WD	109	EBC_BXAP_BCE_DISABLE\|
	110	EBC_BXAP_CSN_ENCODE(1)\|EBC_BXAP_OEN_ENCODE(1)\|
	111	EBC_BXAP_WBN_ENCODE(1)\|EBC_BXAP_WBF_ENCODE(1)\|
	112	EBC_BXAP_TH_ENCODE(1)\|EBC_BXAP_RE_DISABLED\|
	113	EBC_BXAP_BEM_WRITEONLY\|
	114	EBC_BXAP_PEN_DISABLED);
d1c3b275	115	mtebc(PB2CR, EBC_BXCR_BAS_ENCODE(cs2_base)\|
7ec25502	116	cs2_size\|EBC_BXCR_BU_RW\|EBC_BXCR_BW_8BIT);
0e6d798c WD	117
	118	/*-------------------------------------------------------------------------+
	119	\| FPGA. Initialize bank 7 with default values.
	120	+-------------------------------------------------------------------------*/
d1c3b275	121	mtebc(PB7AP, EBC_BXAP_BME_DISABLED\|EBC_BXAP_TWT_ENCODE(7)\|
0e6d798c WD	122	EBC_BXAP_BCE_DISABLE\|
	123	EBC_BXAP_CSN_ENCODE(1)\|EBC_BXAP_OEN_ENCODE(1)\|
	124	EBC_BXAP_WBN_ENCODE(1)\|EBC_BXAP_WBF_ENCODE(1)\|
	125	EBC_BXAP_TH_ENCODE(1)\|EBC_BXAP_RE_DISABLED\|
	126	EBC_BXAP_BEM_WRITEONLY\|
	127	EBC_BXAP_PEN_DISABLED);
d1c3b275	128	mtebc(PB7CR, EBC_BXCR_BAS_ENCODE(0x48300000)\|
0e6d798c WD	129	EBC_BXCR_BS_1MB\|EBC_BXCR_BU_RW\|EBC_BXCR_BW_8BIT);
	130
	131	/*--------------------------------------------------------------------
	132	* Setup the interrupt controller polarities, triggers, etc.
	133	-------------------------------------------------------------------/
5de85140 SR	134	/*
	135	* Because of the interrupt handling rework to handle 440GX interrupts
	136	* with the common code, we needed to change names of the UIC registers.
	137	* Here the new relationship:
	138	*
	139	* U-Boot name 440GX name
	140	* -----------------------
	141	* UIC0 UICB0
	142	* UIC1 UIC0
	143	* UIC2 UIC1
	144	* UIC3 UIC2
	145	*/
952e7760 SR	146	mtdcr (UIC1SR, 0xffffffff); /* clear all */
	147	mtdcr (UIC1ER, 0x00000000); /* disable all */
	148	mtdcr (UIC1CR, 0x00000009); /* SMI & UIC1 crit are critical */
	149	mtdcr (UIC1PR, 0xfffffe13); /* per ref-board manual */
	150	mtdcr (UIC1TR, 0x01c00008); /* per ref-board manual */
	151	mtdcr (UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
	152	mtdcr (UIC1SR, 0xffffffff); /* clear all */
	153
	154	mtdcr (UIC2SR, 0xffffffff); /* clear all */
	155	mtdcr (UIC2ER, 0x00000000); /* disable all */
	156	mtdcr (UIC2CR, 0x00000000); /* all non-critical */
	157	mtdcr (UIC2PR, 0xffffe0ff); /* per ref-board manual */
	158	mtdcr (UIC2TR, 0x00ffc000); /* per ref-board manual */
	159	mtdcr (UIC2VR, 0x00000001); /* int31 highest, base=0x000 */
	160	mtdcr (UIC2SR, 0xffffffff); /* clear all */
	161
	162	mtdcr (UIC3SR, 0xffffffff); /* clear all */
	163	mtdcr (UIC3ER, 0x00000000); /* disable all */
	164	mtdcr (UIC3CR, 0x00000000); /* all non-critical */
	165	mtdcr (UIC3PR, 0xffffffff); /* per ref-board manual */
	166	mtdcr (UIC3TR, 0x00ff8c0f); /* per ref-board manual */
	167	mtdcr (UIC3VR, 0x00000001); /* int31 highest, base=0x000 */
	168	mtdcr (UIC3SR, 0xffffffff); /* clear all */
	169
	170	mtdcr (UIC0SR, 0xfc000000); /* clear all */
	171	mtdcr (UIC0ER, 0x00000000); /* disable all */
	172	mtdcr (UIC0CR, 0x00000000); /* all non-critical */
	173	mtdcr (UIC0PR, 0xfc000000); /* */
	174	mtdcr (UIC0TR, 0x00000000); /* */
	175	mtdcr (UIC0VR, 0x00000001); /* */
d1c3b275	176	mfsdr (SDR0_MFR, mfr);
4b248f3f	177	mfr &= ~SDR0_MFR_ECS_MASK;
d1c3b275	178	/* mtsdr(SDR0_MFR, mfr); */
0e6d798c WD	179	fpga_init();
	180
	181	return 0;
	182	}
	183
	184
	185	int checkboard (void)
	186	{
f0c0b3a9 WD	187	char buf[64];
f0c0b3a9 WD	188	int i = getenv_f("serial#", buf, sizeof(buf));
0e6d798c	189
8a316c9b	190	printf ("Board: Ocotea - AMCC PPC440GX Evaluation Board");
f0c0b3a9 WD	191	if (i > 0) {
	192	puts(", serial# ");
	193	puts(buf);
8a316c9b SR	194	}
	195	putc ('\n');
	196
0e6d798c WD	197	return (0);
	198	}
	199
	200
9973e3c6	201	phys_size_t initdram (int board_type)
0e6d798c WD	202	{
	203	long dram_size = 0;
	204
	205	#if defined(CONFIG_SPD_EEPROM)
d87080b7	206	dram_size = spd_sdram ();
0e6d798c WD	207	#else
	208	dram_size = fixed_sdram ();
	209	#endif
	210	return dram_size;
	211	}
	212
	213
0e6d798c WD	214	#if !defined(CONFIG_SPD_EEPROM)
	215	/*************************************************************************
	216	* fixed sdram init -- doesn't use serial presence detect.
	217	*
	218	* Assumes: 128 MB, non-ECC, non-registered
	219	* PLB @ 133 MHz
	220	*
	221	************************************************************************/
	222	long int fixed_sdram (void)
	223	{
	224	uint reg;
	225
	226	/*--------------------------------------------------------------------
	227	* Setup some default
	228	------------------------------------------------------------------/
95b602ba SR	229	mtsdram (SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */
	230	mtsdram (SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
	231	mtsdram (SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */
	232	mtsdram (SDRAM0_WDDCTR, 0x00000000); /* wrcp=0 dcd=0 */
	233	mtsdram (SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
0e6d798c WD	234
	235	/*--------------------------------------------------------------------
	236	* Setup for board-specific specific mem
	237	------------------------------------------------------------------/
	238	/*
	239	* Following for CAS Latency = 2.5 @ 133 MHz PLB
	240	*/
95b602ba SR	241	mtsdram (SDRAM0_B0CR, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
95b602ba SR	242	mtsdram (SDRAM0_TR0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
0e6d798c	243	/* RA=10 RD=3 */
95b602ba SR	244	mtsdram (SDRAM0_TR1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
	245	mtsdram (SDRAM0_RTR, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */
	246	mtsdram (SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM */
0e6d798c WD	247	udelay (400); /* Delay 200 usecs (min) */
	248
	249	/*--------------------------------------------------------------------
	250	* Enable the controller, then wait for DCEN to complete
	251	------------------------------------------------------------------/
95b602ba	252	mtsdram (SDRAM0_CFG0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
0e6d798c	253	for (;;) {
95b602ba	254	mfsdram (SDRAM0_MCSTS, reg);
0e6d798c WD	255	if (reg & 0x80000000)
	256	break;
	257	}
	258
	259	return (128 * 1024 * 1024); /* 128 MB */
	260	}
	261	#endif /* !defined(CONFIG_SPD_EEPROM) */
	262
0e6d798c WD	263	void fpga_init(void)
	264	{
	265	unsigned long group;
	266	unsigned long sdr0_pfc0;
	267	unsigned long sdr0_pfc1;
	268	unsigned long sdr0_cust0;
	269	unsigned long pvr;
	270
d1c3b275 SR	271	mfsdr (SDR0_PFC0, sdr0_pfc0);
d1c3b275 SR	272	mfsdr (SDR0_PFC1, sdr0_pfc1);
0e6d798c WD	273	group = SDR0_PFC1_EPS_DECODE(sdr0_pfc1);
	274	pvr = get_pvr ();
	275
	276	sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_GEIE_MASK) \| SDR0_PFC0_GEIE_TRE;
	277	if ( ((pvr == PVR_440GX_RA) \|\| (pvr == PVR_440GX_RB)) && ((group == 4) \|\| (group == 5))) {
	278	sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) \| SDR0_PFC0_TRE_DISABLE;
	279	sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) \| SDR0_PFC1_CTEMS_EMS;
	280	out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) \|
	281	FPGA_REG2_EXT_INTFACE_ENABLE);
d1c3b275 SR	282	mtsdr (SDR0_PFC0, sdr0_pfc0);
d1c3b275 SR	283	mtsdr (SDR0_PFC1, sdr0_pfc1);
0e6d798c WD	284	} else {
	285	sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) \| SDR0_PFC0_TRE_ENABLE;
	286	switch (group)
	287	{
	288	case 0:
	289	case 1:
	290	case 2:
	291	/* CPU trace A */
	292	out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) \|
	293	FPGA_REG2_EXT_INTFACE_ENABLE);
	294	sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) \| SDR0_PFC1_CTEMS_EMS;
d1c3b275 SR	295	mtsdr (SDR0_PFC0, sdr0_pfc0);
d1c3b275 SR	296	mtsdr (SDR0_PFC1, sdr0_pfc1);
0e6d798c WD	297	break;
	298	case 3:
	299	case 4:
	300	case 5:
	301	case 6:
	302	/* CPU trace B - Over EBMI */
	303	sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) \| SDR0_PFC1_CTEMS_CPUTRACE;
d1c3b275 SR	304	mtsdr (SDR0_PFC0, sdr0_pfc0);
d1c3b275 SR	305	mtsdr (SDR0_PFC1, sdr0_pfc1);
0e6d798c WD	306	out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) \|
	307	FPGA_REG2_EXT_INTFACE_DISABLE);
	308	break;
	309	}
	310	}
	311
	312	/* Initialize the ethernet specific functions in the fpga */
d1c3b275 SR	313	mfsdr(SDR0_PFC1, sdr0_pfc1);
d1c3b275 SR	314	mfsdr(SDR0_CUST0, sdr0_cust0);
0e6d798c WD	315	if ( (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) == 4) &&
	316	((SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII) \|\|
	317	(SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_TBI)))
	318	{
	319	if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
	320	{
	321	out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK1) \|
	322	FPGA_REG3_ENET_GROUP7);
	323	}
	324	else
	325	{
	326	if (SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII)
	327	{
	328	out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) \|
	329	FPGA_REG3_ENET_GROUP7);
	330	}
	331	else
	332	{
	333	out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) \|
	334	FPGA_REG3_ENET_GROUP8);
	335	}
	336	}
	337	}
	338	else
	339	{
	340	if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
	341	{
	342	out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK1) \|
	343	FPGA_REG3_ENET_ENCODE1(SDR0_PFC1_EPS_DECODE(sdr0_pfc1)));
	344	}
	345	else
	346	{
	347	out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) \|
	348	FPGA_REG3_ENET_ENCODE2(SDR0_PFC1_EPS_DECODE(sdr0_pfc1)));
	349	}
	350	}
	351	out8(FPGA_REG4, FPGA_REG4_GPHY_MODE10 \|
	352	FPGA_REG4_GPHY_MODE100 \| FPGA_REG4_GPHY_MODE1000 \|
	353	FPGA_REG4_GPHY_FRC_DPLX \| FPGA_REG4_CONNECT_PHYS);
	354
	355	/* reset the gigabyte phy if necessary */
	356	if (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) >= 3)
	357	{
	358	if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
	359	{
	360	out8(FPGA_REG3, in8(FPGA_REG3) & ~FPGA_REG3_GIGABIT_RESET_DISABLE);
	361	udelay(10000);
	362	out8(FPGA_REG3, in8(FPGA_REG3) \| FPGA_REG3_GIGABIT_RESET_DISABLE);
	363	}
	364	else
	365	{
	366	out8(FPGA_REG2, in8(FPGA_REG2) & ~FPGA_REG2_GIGABIT_RESET_DISABLE);
	367	udelay(10000);
	368	out8(FPGA_REG2, in8(FPGA_REG2) \| FPGA_REG2_GIGABIT_RESET_DISABLE);
	369	}
	370	}
	371
57275b69 SR	372	/*
	373	* new Ocotea with Rev. F (pass 3) chips has SMII PHY reset
	374	*/
	375	if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER2) {
	376	out8(FPGA_REG2, in8(FPGA_REG2) & ~FPGA_REG2_SMII_RESET_DISABLE);
	377	udelay(10000);
	378	out8(FPGA_REG2, in8(FPGA_REG2) \| FPGA_REG2_SMII_RESET_DISABLE);
	379	}
	380
0e6d798c WD	381	/* Turn off the LED's */
	382	out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_STAT_MASK) \|
	383	FPGA_REG3_STAT_LED8_DISAB \| FPGA_REG3_STAT_LED4_DISAB \|
	384	FPGA_REG3_STAT_LED2_DISAB \| FPGA_REG3_STAT_LED1_DISAB);
	385
	386	return;
	387	}