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5b1d7137 WD |
1 | /* |
2 | * (C) Copyright 2001 | |
fa82f871 | 3 | * Stäubli Faverges - <www.staubli.com> |
5b1d7137 WD |
4 | * Pierre AUBERT [email protected] |
5 | * U-Boot port on RPXClassic LF (CLLF_BW31) board | |
6 | * | |
7 | * (C) Copyright 2000 | |
8 | * Wolfgang Denk, DENX Software Engineering, [email protected]. | |
9 | * | |
3765b3e7 | 10 | * SPDX-License-Identifier: GPL-2.0+ |
5b1d7137 WD |
11 | */ |
12 | ||
13 | #include <common.h> | |
14 | #include <i2c.h> | |
15 | #include <config.h> | |
16 | #include <mpc8xx.h> | |
76756e41 | 17 | #include <net.h> |
5b1d7137 WD |
18 | |
19 | /* ------------------------------------------------------------------------- */ | |
20 | ||
21 | static long int dram_size (long int, long int *, long int); | |
22 | static unsigned char aschex_to_byte (unsigned char *cp); | |
23 | ||
24 | /* ------------------------------------------------------------------------- */ | |
25 | ||
26 | #define _NOT_USED_ 0xFFFFCC25 | |
27 | ||
28 | const uint sdram_table[] = | |
29 | { | |
30 | /* | |
31 | * Single Read. (Offset 00h in UPMA RAM) | |
32 | */ | |
33 | 0xCFFFCC24, 0x0FFFCC04, 0X0CAFCC04, 0X03AFCC08, | |
34 | 0x3FBFCC27, /* last */ | |
35 | _NOT_USED_, _NOT_USED_, _NOT_USED_, | |
36 | ||
37 | /* | |
38 | * Burst Read. (Offset 08h in UPMA RAM) | |
39 | */ | |
40 | 0xCFFFCC24, 0x0FFFCC04, 0x0CAFCC84, 0x03AFCC88, | |
41 | 0x3FBFCC27, /* last */ | |
42 | _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, | |
43 | _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, | |
44 | _NOT_USED_, _NOT_USED_, _NOT_USED_, | |
45 | ||
46 | /* | |
47 | * Single Write. (Offset 18h in UPMA RAM) | |
48 | */ | |
49 | 0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC04, 0x03FFCC00, | |
50 | 0x3FFFCC27, /* last */ | |
51 | _NOT_USED_, _NOT_USED_, _NOT_USED_, | |
52 | ||
53 | /* | |
54 | * Burst Write. (Offset 20h in UPMA RAM) | |
55 | */ | |
56 | 0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC80, 0x03FFCC8C, | |
57 | 0x0CFFCC00, 0x33FFCC27, /* last */ | |
58 | _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, | |
59 | _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, | |
60 | _NOT_USED_, _NOT_USED_, | |
61 | ||
62 | /* | |
63 | * Refresh. (Offset 30h in UPMA RAM) | |
64 | */ | |
65 | 0xC0FFCC24, 0x03FFCC24, 0x0FFFCC24, 0x0FFFCC24, | |
66 | 0x3FFFCC27, /* last */ | |
67 | _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, | |
68 | _NOT_USED_, _NOT_USED_, _NOT_USED_, | |
69 | ||
70 | /* | |
71 | * Exception. (Offset 3Ch in UPMA RAM) | |
72 | */ | |
73 | _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_ | |
74 | }; | |
75 | ||
76 | /* ------------------------------------------------------------------------- */ | |
77 | ||
78 | ||
79 | /* | |
80 | * Check Board Identity: | |
81 | */ | |
82 | ||
83 | int checkboard (void) | |
84 | { | |
85 | puts ("Board: RPXClassic\n"); | |
86 | return (0); | |
87 | } | |
88 | ||
89 | /*----------------------------------------------------------------------------- | |
90 | * board_get_enetaddr -- Read the MAC Address in the I2C EEPROM | |
91 | *----------------------------------------------------------------------------- | |
92 | */ | |
d8d21e69 | 93 | static void board_get_enetaddr(uchar *enet) |
5b1d7137 WD |
94 | { |
95 | int i; | |
96 | char buff[256], *cp; | |
97 | ||
98 | /* Initialize I2C */ | |
6d0f6bcf | 99 | i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); |
5b1d7137 WD |
100 | |
101 | /* Read 256 bytes in EEPROM */ | |
77ddac94 WD |
102 | i2c_read (0x54, 0, 1, (uchar *)buff, 128); |
103 | i2c_read (0x54, 128, 1, (uchar *)buff + 128, 128); | |
5b1d7137 WD |
104 | |
105 | /* Retrieve MAC address in buffer (key EA) */ | |
106 | for (cp = buff;;) { | |
107 | if (cp[0] == 'E' && cp[1] == 'A') { | |
108 | cp += 3; | |
109 | /* Read MAC address */ | |
110 | for (i = 0; i < 6; i++, cp += 2) { | |
77ddac94 | 111 | enet[i] = aschex_to_byte ((unsigned char *)cp); |
5b1d7137 WD |
112 | } |
113 | } | |
114 | /* Scan to the end of the record */ | |
b2184c31 | 115 | while ((*cp != '\n') && (*cp != (char)0xff)) { |
5b1d7137 WD |
116 | cp++; |
117 | } | |
118 | /* If the next character is a \n, 0 or ff, we are done. */ | |
119 | cp++; | |
b2184c31 | 120 | if ((*cp == '\n') || (*cp == 0) || (*cp == (char)0xff)) |
5b1d7137 WD |
121 | break; |
122 | } | |
123 | ||
124 | #ifdef CONFIG_FEC_ENET | |
125 | /* The MAC address is the same as normal ethernet except the 3rd byte */ | |
126 | /* (See the E.P. Planet Core Overview manual */ | |
127 | enet[3] |= 0x80; | |
5b1d7137 WD |
128 | #endif |
129 | ||
d8d21e69 MF |
130 | printf("MAC address = %pM\n", enet); |
131 | } | |
132 | ||
133 | int misc_init_r(void) | |
134 | { | |
135 | uchar enetaddr[6]; | |
136 | ||
137 | if (!eth_getenv_enetaddr("ethaddr", enetaddr)) { | |
138 | board_get_enetaddr(enetaddr); | |
76756e41 | 139 | eth_setenv_enetaddr("ethaddr", enetaddr); |
d8d21e69 | 140 | } |
5b1d7137 | 141 | |
d8d21e69 | 142 | return 0; |
5b1d7137 WD |
143 | } |
144 | ||
145 | void rpxclassic_init (void) | |
146 | { | |
147 | /* Enable NVRAM */ | |
148 | *((uchar *) BCSR0) |= BCSR0_ENNVRAM; | |
149 | ||
b2184c31 WD |
150 | #ifdef CONFIG_FEC_ENET |
151 | ||
152 | /* Validate the fast ethernet tranceiver */ | |
153 | *((volatile uchar *) BCSR2) &= ~BCSR2_MIICTL; | |
154 | *((volatile uchar *) BCSR2) &= ~BCSR2_MIIPWRDWN; | |
155 | *((volatile uchar *) BCSR2) |= BCSR2_MIIRST; | |
156 | *((volatile uchar *) BCSR2) |= BCSR2_MIIPWRDWN; | |
157 | #endif | |
158 | ||
5b1d7137 WD |
159 | } |
160 | ||
161 | /* ------------------------------------------------------------------------- */ | |
162 | ||
9973e3c6 | 163 | phys_size_t initdram (int board_type) |
5b1d7137 | 164 | { |
6d0f6bcf | 165 | volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; |
5b1d7137 WD |
166 | volatile memctl8xx_t *memctl = &immap->im_memctl; |
167 | long int size10; | |
168 | ||
169 | upmconfig (UPMA, (uint *) sdram_table, | |
170 | sizeof (sdram_table) / sizeof (uint)); | |
171 | ||
172 | /* Refresh clock prescalar */ | |
6d0f6bcf | 173 | memctl->memc_mptpr = CONFIG_SYS_MPTPR; |
5b1d7137 WD |
174 | |
175 | memctl->memc_mar = 0x00000000; | |
176 | ||
177 | /* Map controller banks 1 to the SDRAM bank */ | |
6d0f6bcf JCPV |
178 | memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; |
179 | memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; | |
5b1d7137 | 180 | |
6d0f6bcf | 181 | memctl->memc_mamr = CONFIG_SYS_MAMR_10COL & (~(MAMR_PTAE)); /* no refresh yet */ |
5b1d7137 WD |
182 | |
183 | udelay (200); | |
184 | ||
185 | /* perform SDRAM initializsation sequence */ | |
186 | ||
187 | memctl->memc_mcr = 0x80002230; /* SDRAM bank 0 - refresh twice */ | |
188 | udelay (1); | |
189 | ||
190 | memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ | |
191 | ||
192 | udelay (1000); | |
193 | ||
194 | /* Check Bank 0 Memory Size | |
195 | * try 10 column mode | |
196 | */ | |
197 | ||
6d0f6bcf | 198 | size10 = dram_size (CONFIG_SYS_MAMR_10COL, SDRAM_BASE_PRELIM, |
5b1d7137 WD |
199 | SDRAM_MAX_SIZE); |
200 | ||
201 | return (size10); | |
202 | } | |
203 | ||
204 | /* ------------------------------------------------------------------------- */ | |
205 | ||
206 | /* | |
207 | * Check memory range for valid RAM. A simple memory test determines | |
208 | * the actually available RAM size between addresses `base' and | |
209 | * `base + maxsize'. Some (not all) hardware errors are detected: | |
210 | * - short between address lines | |
211 | * - short between data lines | |
212 | */ | |
213 | ||
214 | static long int dram_size (long int mamr_value, long int *base, long int maxsize) | |
215 | { | |
6d0f6bcf | 216 | volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; |
5b1d7137 | 217 | volatile memctl8xx_t *memctl = &immap->im_memctl; |
5b1d7137 WD |
218 | |
219 | memctl->memc_mamr = mamr_value; | |
220 | ||
c83bf6a2 | 221 | return (get_ram_size(base, maxsize)); |
5b1d7137 | 222 | } |
b2184c31 | 223 | /*----------------------------------------------------------------------------- |
8bde7f77 | 224 | * aschex_to_byte -- |
b2184c31 WD |
225 | *----------------------------------------------------------------------------- |
226 | */ | |
5b1d7137 WD |
227 | static unsigned char aschex_to_byte (unsigned char *cp) |
228 | { | |
229 | u_char byte, c; | |
230 | ||
231 | c = *cp++; | |
232 | ||
233 | if ((c >= 'A') && (c <= 'F')) { | |
234 | c -= 'A'; | |
235 | c += 10; | |
236 | } else if ((c >= 'a') && (c <= 'f')) { | |
237 | c -= 'a'; | |
238 | c += 10; | |
239 | } else { | |
240 | c -= '0'; | |
241 | } | |
242 | ||
243 | byte = c * 16; | |
244 | ||
245 | c = *cp; | |
246 | ||
247 | if ((c >= 'A') && (c <= 'F')) { | |
248 | c -= 'A'; | |
249 | c += 10; | |
250 | } else if ((c >= 'a') && (c <= 'f')) { | |
251 | c -= 'a'; | |
252 | c += 10; | |
253 | } else { | |
254 | c -= '0'; | |
255 | } | |
256 | ||
257 | byte += c; | |
258 | ||
259 | return (byte); | |
260 | } |