[J-u-boot.git] / board / grinn / liteboard / board.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
 * Copyright (C) 2016 Grinn
 */

#include <asm/arch/clock.h>
#include <asm/arch/iomux.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/litesom.h>
#include <asm/arch/mx6ul_pins.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/io.h>
#include <common.h>
#include <env.h>
#include <fsl_esdhc_imx.h>
#include <linux/sizes.h>
#include <linux/fb.h>
#include <miiphy.h>
#include <mmc.h>
#include <netdev.h>
#include <spl.h>

DECLARE_GLOBAL_DATA_PTR;

#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)

#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
	PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |		\
	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)

#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
	PAD_CTL_SPEED_HIGH   |                                   \
	PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST)

#define MDIO_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
	PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST | PAD_CTL_ODE)

#define ENET_CLK_PAD_CTRL  (PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)

static iomux_v3_cfg_t const uart1_pads[] = {
	MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
	MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
};

static iomux_v3_cfg_t const sd_pads[] = {
	MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

	/* CD */
	MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
};

static void setup_iomux_uart(void)
{
	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
}

#ifdef CONFIG_FSL_ESDHC_IMX
static struct fsl_esdhc_cfg sd_cfg = {USDHC1_BASE_ADDR, 0, 4};

#define SD_CD_GPIO	IMX_GPIO_NR(1, 19)

static int mmc_get_env_devno(void)
{
	u32 soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
	int dev_no;
	u32 bootsel;

	bootsel = (soc_sbmr & 0x000000FF) >> 6;

	/* If not boot from sd/mmc, use default value */
	if (bootsel != 1)
		return CONFIG_SYS_MMC_ENV_DEV;

	/* BOOT_CFG2[3] and BOOT_CFG2[4] */
	dev_no = (soc_sbmr & 0x00001800) >> 11;

	return dev_no;
}

int board_mmc_getcd(struct mmc *mmc)
{
	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
	int ret = 0;

	switch (cfg->esdhc_base) {
	case USDHC1_BASE_ADDR:
		ret = !gpio_get_value(SD_CD_GPIO);
		break;
	case USDHC2_BASE_ADDR:
		ret = 1;
		break;
	}

	return ret;
}

int board_mmc_init(bd_t *bis)
{
	int ret;

	/* SD */
	imx_iomux_v3_setup_multiple_pads(sd_pads, ARRAY_SIZE(sd_pads));
	gpio_direction_input(SD_CD_GPIO);
	sd_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);

	ret = fsl_esdhc_initialize(bis, &sd_cfg);
	if (ret) {
		printf("Warning: failed to initialize mmc dev 0 (SD)\n");
		return ret;
	}

	return litesom_mmc_init(bis);
}

static int check_mmc_autodetect(void)
{
	char *autodetect_str = env_get("mmcautodetect");

	if ((autodetect_str != NULL) &&
	    (strcmp(autodetect_str, "yes") == 0)) {
		return 1;
	}

	return 0;
}

void board_late_mmc_init(void)
{
	char cmd[32];
	char mmcblk[32];
	u32 dev_no = mmc_get_env_devno();

	if (!check_mmc_autodetect())
		return;

	env_set_ulong("mmcdev", dev_no);

	/* Set mmcblk env */
	sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw",
		dev_no);
	env_set("mmcroot", mmcblk);

	sprintf(cmd, "mmc dev %d", dev_no);
	run_command(cmd, 0);
}
#endif

#ifdef CONFIG_FEC_MXC
static int setup_fec(void)
{
	struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
	int ret;

	/* Use 50M anatop loopback REF_CLK1 for ENET1, clear gpr1[13],
	   set gpr1[17]*/
	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
			IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);

	ret = enable_fec_anatop_clock(0, ENET_50MHZ);
	if (ret)
		return ret;

	enable_enet_clk(1);

	return 0;
}
#endif

int board_early_init_f(void)
{
	setup_iomux_uart();

	return 0;
}

int board_init(void)
{
	/* Address of boot parameters */
	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;

#ifdef	CONFIG_FEC_MXC
	setup_fec();
#endif

	return 0;
}

#ifdef CONFIG_CMD_BMODE
static const struct boot_mode board_boot_modes[] = {
	/* 4 bit bus width */
	{"sd",   MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
	{"emmc", MAKE_CFGVAL(0x60, 0x48, 0x00, 0x00)},
	{NULL,	 0},
};
#endif

int board_late_init(void)
{
#ifdef CONFIG_CMD_BMODE
	add_board_boot_modes(board_boot_modes);
#endif

#ifdef CONFIG_ENV_IS_IN_MMC
	board_late_mmc_init();
#endif

	return 0;
}

int checkboard(void)
{
	puts("Board: Grinn liteBoard\n");

	return 0;
}

#ifdef CONFIG_SPL_BUILD
void board_boot_order(u32 *spl_boot_list)
{
	struct src *psrc = (struct src *)SRC_BASE_ADDR;
	unsigned gpr10_boot = readl(&psrc->gpr10) & (1 << 28);
	unsigned reg = gpr10_boot ? readl(&psrc->gpr9) : readl(&psrc->sbmr1);
	unsigned port = (reg >> 11) & 0x1;

	if (port == 0) {
		spl_boot_list[0] = BOOT_DEVICE_MMC1;
		spl_boot_list[1] = BOOT_DEVICE_MMC2;
	} else {
		spl_boot_list[0] = BOOT_DEVICE_MMC2;
		spl_boot_list[1] = BOOT_DEVICE_MMC1;
	}
}

void board_init_f(ulong dummy)
{
	litesom_init_f();
}
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
c9e40e65 MN	2	/*
	3	* Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
	4	* Copyright (C) 2016 Grinn
c9e40e65 MN	5	*/
	6
	7	#include <asm/arch/clock.h>
	8	#include <asm/arch/iomux.h>
	9	#include <asm/arch/imx-regs.h>
	10	#include <asm/arch/crm_regs.h>
d4b1b527	11	#include <asm/arch/litesom.h>
c9e40e65 MN	12	#include <asm/arch/mx6ul_pins.h>
	13	#include <asm/arch/mx6-pins.h>
	14	#include <asm/arch/sys_proto.h>
	15	#include <asm/gpio.h>
552a848e SB	16	#include <asm/mach-imx/iomux-v3.h>
552a848e SB	17	#include <asm/mach-imx/boot_mode.h>
c9e40e65 MN	18	#include <asm/io.h>
c9e40e65 MN	19	#include <common.h>
168068fb	20	#include <env.h>
e37ac717	21	#include <fsl_esdhc_imx.h>
c9e40e65 MN	22	#include <linux/sizes.h>
c9e40e65 MN	23	#include <linux/fb.h>
c9e40e65 MN	24	#include <miiphy.h>
	25	#include <mmc.h>
	26	#include <netdev.h>
	27	#include <spl.h>
c9e40e65 MN	28
	29	DECLARE_GLOBAL_DATA_PTR;
	30
	31	#define UART_PAD_CTRL (PAD_CTL_PKE \| PAD_CTL_PUE \| \
	32	PAD_CTL_PUS_100K_UP \| PAD_CTL_SPEED_MED \| \
	33	PAD_CTL_DSE_40ohm \| PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
	34
	35	#define USDHC_PAD_CTRL (PAD_CTL_PKE \| PAD_CTL_PUE \| \
	36	PAD_CTL_PUS_22K_UP \| PAD_CTL_SPEED_LOW \| \
	37	PAD_CTL_DSE_80ohm \| PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
	38
	39	#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP \| PAD_CTL_PUE \| \
	40	PAD_CTL_SPEED_HIGH \| \
	41	PAD_CTL_DSE_48ohm \| PAD_CTL_SRE_FAST)
	42
	43	#define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP \| PAD_CTL_PUE \| \
	44	PAD_CTL_DSE_48ohm \| PAD_CTL_SRE_FAST \| PAD_CTL_ODE)
	45
	46	#define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm \| PAD_CTL_SRE_FAST)
	47
	48	static iomux_v3_cfg_t const uart1_pads[] = {
	49	MX6_PAD_UART1_TX_DATA__UART1_DCE_TX \| MUX_PAD_CTRL(UART_PAD_CTRL),
	50	MX6_PAD_UART1_RX_DATA__UART1_DCE_RX \| MUX_PAD_CTRL(UART_PAD_CTRL),
	51	};
	52
	53	static iomux_v3_cfg_t const sd_pads[] = {
	54	MX6_PAD_SD1_CLK__USDHC1_CLK \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	55	MX6_PAD_SD1_CMD__USDHC1_CMD \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	56	MX6_PAD_SD1_DATA0__USDHC1_DATA0 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	57	MX6_PAD_SD1_DATA1__USDHC1_DATA1 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	58	MX6_PAD_SD1_DATA2__USDHC1_DATA2 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	59	MX6_PAD_SD1_DATA3__USDHC1_DATA3 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	60
	61	/* CD */
	62	MX6_PAD_UART1_RTS_B__GPIO1_IO19 \| MUX_PAD_CTRL(NO_PAD_CTRL),
	63	};
	64
c9e40e65 MN	65	static void setup_iomux_uart(void)
	66	{
	67	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
	68	}
	69
e37ac717	70	#ifdef CONFIG_FSL_ESDHC_IMX
c9e40e65 MN	71	static struct fsl_esdhc_cfg sd_cfg = {USDHC1_BASE_ADDR, 0, 4};
	72
	73	#define SD_CD_GPIO IMX_GPIO_NR(1, 19)
	74
	75	static int mmc_get_env_devno(void)
	76	{
	77	u32 soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
	78	int dev_no;
	79	u32 bootsel;
	80
	81	bootsel = (soc_sbmr & 0x000000FF) >> 6;
	82
	83	/* If not boot from sd/mmc, use default value */
	84	if (bootsel != 1)
	85	return CONFIG_SYS_MMC_ENV_DEV;
	86
	87	/* BOOT_CFG2[3] and BOOT_CFG2[4] */
	88	dev_no = (soc_sbmr & 0x00001800) >> 11;
	89
	90	return dev_no;
	91	}
	92
	93	int board_mmc_getcd(struct mmc *mmc)
	94	{
	95	struct fsl_esdhc_cfg cfg = (struct fsl_esdhc_cfg )mmc->priv;
	96	int ret = 0;
	97
	98	switch (cfg->esdhc_base) {
	99	case USDHC1_BASE_ADDR:
	100	ret = !gpio_get_value(SD_CD_GPIO);
	101	break;
	102	case USDHC2_BASE_ADDR:
	103	ret = 1;
	104	break;
	105	}
	106
	107	return ret;
	108	}
	109
	110	int board_mmc_init(bd_t *bis)
	111	{
	112	int ret;
	113
	114	/* SD */
	115	imx_iomux_v3_setup_multiple_pads(sd_pads, ARRAY_SIZE(sd_pads));
	116	gpio_direction_input(SD_CD_GPIO);
	117	sd_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
	118
	119	ret = fsl_esdhc_initialize(bis, &sd_cfg);
	120	if (ret) {
	121	printf("Warning: failed to initialize mmc dev 0 (SD)\n");
	122	return ret;
	123	}
	124
	125	return litesom_mmc_init(bis);
	126	}
	127
	128	static int check_mmc_autodetect(void)
	129	{
00caae6d	130	char *autodetect_str = env_get("mmcautodetect");
c9e40e65 MN	131
	132	if ((autodetect_str != NULL) &&
	133	(strcmp(autodetect_str, "yes") == 0)) {
	134	return 1;
	135	}
	136
	137	return 0;
	138	}
	139
	140	void board_late_mmc_init(void)
	141	{
	142	char cmd[32];
	143	char mmcblk[32];
	144	u32 dev_no = mmc_get_env_devno();
	145
	146	if (!check_mmc_autodetect())
	147	return;
	148
018f5303	149	env_set_ulong("mmcdev", dev_no);
c9e40e65 MN	150
	151	/* Set mmcblk env */
	152	sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw",
	153	dev_no);
382bee57	154	env_set("mmcroot", mmcblk);
c9e40e65 MN	155
	156	sprintf(cmd, "mmc dev %d", dev_no);
	157	run_command(cmd, 0);
	158	}
	159	#endif
	160
	161	#ifdef CONFIG_FEC_MXC
c9e40e65 MN	162	static int setup_fec(void)
	163	{
	164	struct iomuxc const iomuxc_regs = (struct iomuxc )IOMUXC_BASE_ADDR;
	165	int ret;
	166
	167	/* Use 50M anatop loopback REF_CLK1 for ENET1, clear gpr1[13],
	168	set gpr1[17]*/
	169	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
	170	IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
	171
	172	ret = enable_fec_anatop_clock(0, ENET_50MHZ);
	173	if (ret)
	174	return ret;
	175
	176	enable_enet_clk(1);
	177
	178	return 0;
	179	}
	180	#endif
	181
c9e40e65 MN	182	int board_early_init_f(void)
	183	{
	184	setup_iomux_uart();
	185
	186	return 0;
	187	}
	188
	189	int board_init(void)
	190	{
	191	/* Address of boot parameters */
	192	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
	193
	194	#ifdef CONFIG_FEC_MXC
	195	setup_fec();
	196	#endif
	197
	198	return 0;
	199	}
	200
	201	#ifdef CONFIG_CMD_BMODE
	202	static const struct boot_mode board_boot_modes[] = {
	203	/* 4 bit bus width */
	204	{"sd", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
	205	{"emmc", MAKE_CFGVAL(0x60, 0x48, 0x00, 0x00)},
	206	{NULL, 0},
	207	};
	208	#endif
	209
	210	int board_late_init(void)
	211	{
	212	#ifdef CONFIG_CMD_BMODE
	213	add_board_boot_modes(board_boot_modes);
	214	#endif
	215
	216	#ifdef CONFIG_ENV_IS_IN_MMC
	217	board_late_mmc_init();
	218	#endif
	219
	220	return 0;
	221	}
	222
	223	int checkboard(void)
	224	{
	225	puts("Board: Grinn liteBoard\n");
	226
	227	return 0;
	228	}
	229
	230	#ifdef CONFIG_SPL_BUILD
	231	void board_boot_order(u32 *spl_boot_list)
	232	{
	233	struct src psrc = (struct src )SRC_BASE_ADDR;
	234	unsigned gpr10_boot = readl(&psrc->gpr10) & (1 << 28);
	235	unsigned reg = gpr10_boot ? readl(&psrc->gpr9) : readl(&psrc->sbmr1);
	236	unsigned port = (reg >> 11) & 0x1;
	237
	238	if (port == 0) {
	239	spl_boot_list[0] = BOOT_DEVICE_MMC1;
	240	spl_boot_list[1] = BOOT_DEVICE_MMC2;
	241	} else {
	242	spl_boot_list[0] = BOOT_DEVICE_MMC2;
	243	spl_boot_list[1] = BOOT_DEVICE_MMC1;
	244	}
	245	}
246
247	void board_init_f(ulong dummy)
248	{
249	litesom_init_f();
250	}
251	#endif