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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
71ebb335 RS |
2 | /* |
3 | * (C) Copyright 2013 SAMSUNG Electronics | |
4 | * Rajeshwari Shinde <[email protected]> | |
71ebb335 RS |
5 | */ |
6 | ||
7 | #include <common.h> | |
8 | #include <cros_ec.h> | |
09140113 | 9 | #include <env.h> |
71ebb335 RS |
10 | #include <errno.h> |
11 | #include <fdtdec.h> | |
db41d65a | 12 | #include <hang.h> |
5255932f | 13 | #include <init.h> |
f7ae49fc | 14 | #include <log.h> |
90526e9f | 15 | #include <net.h> |
71ebb335 RS |
16 | #include <spi.h> |
17 | #include <tmu.h> | |
18 | #include <netdev.h> | |
401d1c4f | 19 | #include <asm/global_data.h> |
71ebb335 | 20 | #include <asm/io.h> |
903fd795 | 21 | #include <asm/gpio.h> |
71ebb335 RS |
22 | #include <asm/arch/board.h> |
23 | #include <asm/arch/cpu.h> | |
24 | #include <asm/arch/dwmmc.h> | |
71ebb335 RS |
25 | #include <asm/arch/mmc.h> |
26 | #include <asm/arch/pinmux.h> | |
27 | #include <asm/arch/power.h> | |
f0017175 | 28 | #include <asm/arch/system.h> |
622e5fee | 29 | #include <i2c.h> |
86c88711 MS |
30 | #include <mmc.h> |
31 | #include <stdio_dev.h> | |
28f393cd | 32 | #include <usb.h> |
302a7d00 | 33 | #include <dwc3-uboot.h> |
c05ed00a | 34 | #include <linux/delay.h> |
302a7d00 | 35 | #include <samsung/misc.h> |
6c15a2a9 TA |
36 | #include <dm/pinctrl.h> |
37 | #include <dm.h> | |
71ebb335 RS |
38 | |
39 | DECLARE_GLOBAL_DATA_PTR; | |
40 | ||
e7e60c13 | 41 | __weak int exynos_early_init_f(void) |
8e5e1e6a PW |
42 | { |
43 | return 0; | |
44 | } | |
8e5e1e6a | 45 | |
e7e60c13 | 46 | __weak int exynos_power_init(void) |
8e5e1e6a PW |
47 | { |
48 | return 0; | |
49 | } | |
8e5e1e6a | 50 | |
86c88711 MS |
51 | /** |
52 | * get_boot_mmc_dev() - read boot MMC device id from XOM[7:5] pins. | |
53 | */ | |
54 | static int get_boot_mmc_dev(void) | |
55 | { | |
56 | u32 mode = readl(EXYNOS4_OP_MODE) & 0x1C; | |
57 | ||
58 | if (mode == 0x04) | |
59 | return 2; /* MMC2: SD */ | |
60 | ||
61 | /* MMC0: eMMC or unknown */ | |
62 | return 0; | |
63 | } | |
64 | ||
71ebb335 RS |
65 | #if defined CONFIG_EXYNOS_TMU |
66 | /* Boot Time Thermal Analysis for SoC temperature threshold breach */ | |
67 | static void boot_temp_check(void) | |
68 | { | |
69 | int temp; | |
70 | ||
71 | switch (tmu_monitor(&temp)) { | |
72 | case TMU_STATUS_NORMAL: | |
73 | break; | |
74 | case TMU_STATUS_TRIPPED: | |
75 | /* | |
76 | * Status TRIPPED ans WARNING means corresponding threshold | |
77 | * breach | |
78 | */ | |
79 | puts("EXYNOS_TMU: TRIPPING! Device power going down ...\n"); | |
80 | set_ps_hold_ctrl(); | |
81 | hang(); | |
82 | break; | |
83 | case TMU_STATUS_WARNING: | |
84 | puts("EXYNOS_TMU: WARNING! Temperature very high\n"); | |
85 | break; | |
86 | case TMU_STATUS_INIT: | |
87 | /* | |
88 | * TMU_STATUS_INIT means something is wrong with temperature | |
89 | * sensing and TMU status was changed back from NORMAL to INIT. | |
90 | */ | |
91 | puts("EXYNOS_TMU: WARNING! Temperature sensing not done\n"); | |
92 | break; | |
93 | default: | |
94 | debug("EXYNOS_TMU: Unknown TMU state\n"); | |
95 | } | |
96 | } | |
97 | #endif | |
98 | ||
99 | int board_init(void) | |
100 | { | |
101 | gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL); | |
102 | #if defined CONFIG_EXYNOS_TMU | |
103 | if (tmu_init(gd->fdt_blob) != TMU_STATUS_NORMAL) { | |
104 | debug("%s: Failed to init TMU\n", __func__); | |
105 | return -1; | |
106 | } | |
107 | boot_temp_check(); | |
108 | #endif | |
24c904f3 | 109 | #if CONFIG_VAL(SYS_MEM_TOP_HIDE) |
a0643e22 | 110 | /* The last few MB of memory can be reserved for secure firmware */ |
24c904f3 | 111 | ulong size = CONFIG_SYS_MEM_TOP_HIDE; |
71ebb335 | 112 | |
a0643e22 PM |
113 | gd->ram_size -= size; |
114 | gd->bd->bi_dram[CONFIG_NR_DRAM_BANKS - 1].size -= size; | |
115 | #endif | |
71ebb335 RS |
116 | return exynos_init(); |
117 | } | |
118 | ||
119 | int dram_init(void) | |
120 | { | |
c8b71a35 | 121 | unsigned int i; |
6c15a2a9 | 122 | unsigned long addr; |
71ebb335 RS |
123 | |
124 | for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { | |
125 | addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); | |
126 | gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE); | |
127 | } | |
128 | return 0; | |
129 | } | |
130 | ||
76b00aca | 131 | int dram_init_banksize(void) |
71ebb335 | 132 | { |
c8b71a35 | 133 | unsigned int i; |
6c15a2a9 | 134 | unsigned long addr, size; |
71ebb335 RS |
135 | |
136 | for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { | |
137 | addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); | |
138 | size = get_ram_size((long *)addr, SDRAM_BANK_SIZE); | |
139 | ||
140 | gd->bd->bi_dram[i].start = addr; | |
141 | gd->bd->bi_dram[i].size = size; | |
142 | } | |
76b00aca SG |
143 | |
144 | return 0; | |
71ebb335 RS |
145 | } |
146 | ||
147 | static int board_uart_init(void) | |
148 | { | |
6c15a2a9 | 149 | #ifndef CONFIG_PINCTRL_EXYNOS |
71ebb335 RS |
150 | int err, uart_id, ret = 0; |
151 | ||
152 | for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) { | |
153 | err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE); | |
154 | if (err) { | |
155 | debug("UART%d not configured\n", | |
156 | (uart_id - PERIPH_ID_UART0)); | |
157 | ret |= err; | |
158 | } | |
159 | } | |
160 | return ret; | |
6c15a2a9 TA |
161 | #else |
162 | return 0; | |
163 | #endif | |
71ebb335 RS |
164 | } |
165 | ||
166 | #ifdef CONFIG_BOARD_EARLY_INIT_F | |
167 | int board_early_init_f(void) | |
168 | { | |
169 | int err; | |
d50c41ef PM |
170 | #ifdef CONFIG_BOARD_TYPES |
171 | set_board_type(); | |
172 | #endif | |
71ebb335 RS |
173 | err = board_uart_init(); |
174 | if (err) { | |
175 | debug("UART init failed\n"); | |
176 | return err; | |
177 | } | |
178 | ||
179 | #ifdef CONFIG_SYS_I2C_INIT_BOARD | |
180 | board_i2c_init(gd->fdt_blob); | |
181 | #endif | |
f0017175 | 182 | |
8e5e1e6a | 183 | return exynos_early_init_f(); |
71ebb335 RS |
184 | } |
185 | #endif | |
186 | ||
9d8665b7 | 187 | #if CONFIG_IS_ENABLED(POWER_LEGACY) || CONFIG_IS_ENABLED(DM_PMIC) |
71ebb335 RS |
188 | int power_init_board(void) |
189 | { | |
71ebb335 RS |
190 | set_ps_hold_ctrl(); |
191 | ||
8e5e1e6a | 192 | return exynos_power_init(); |
71ebb335 RS |
193 | } |
194 | #endif | |
195 | ||
345a5368 | 196 | #if defined(CONFIG_DISPLAY_BOARDINFO) || defined(CONFIG_DISPLAY_BOARDINFO_LATE) |
4c1dd998 PW |
197 | int checkboard(void) |
198 | { | |
a42ff927 | 199 | if (IS_ENABLED(CONFIG_BOARD_TYPES)) { |
e3ee4be3 KK |
200 | const char *board_info; |
201 | ||
202 | if (IS_ENABLED(CONFIG_DISPLAY_BOARDINFO_LATE)) { | |
203 | /* | |
204 | * Printing type requires having revision, although | |
205 | * this will succeed only if done late. | |
206 | * Otherwise revision will be set in misc_init_r(). | |
207 | */ | |
208 | set_board_revision(); | |
209 | } | |
210 | ||
211 | board_info = get_board_type(); | |
a42ff927 SG |
212 | |
213 | if (board_info) | |
214 | printf("Type: %s\n", board_info); | |
215 | } | |
4c1dd998 | 216 | |
4c1dd998 PW |
217 | return 0; |
218 | } | |
71ebb335 RS |
219 | #endif |
220 | ||
221 | #ifdef CONFIG_BOARD_LATE_INIT | |
222 | int board_late_init(void) | |
223 | { | |
a2a63a35 SG |
224 | struct udevice *dev; |
225 | int ret; | |
86c88711 MS |
226 | int mmcbootdev = get_boot_mmc_dev(); |
227 | char mmcbootdev_str[16]; | |
71ebb335 | 228 | |
a2a63a35 SG |
229 | ret = uclass_first_device_err(UCLASS_CROS_EC, &dev); |
230 | if (ret && ret != -ENODEV) { | |
71ebb335 RS |
231 | /* Force console on */ |
232 | gd->flags &= ~GD_FLG_SILENT; | |
233 | ||
a2a63a35 | 234 | printf("cros-ec communications failure %d\n", ret); |
71ebb335 RS |
235 | puts("\nPlease reset with Power+Refresh\n\n"); |
236 | panic("Cannot init cros-ec device"); | |
237 | return -1; | |
238 | } | |
86c88711 MS |
239 | |
240 | printf("Boot device: MMC(%u)\n", mmcbootdev); | |
241 | sprintf(mmcbootdev_str, "%u", mmcbootdev); | |
242 | env_set("mmcbootdev", mmcbootdev_str); | |
243 | ||
71ebb335 RS |
244 | return 0; |
245 | } | |
246 | #endif | |
247 | ||
431a1c56 PW |
248 | #ifdef CONFIG_MISC_INIT_R |
249 | int misc_init_r(void) | |
250 | { | |
e3ee4be3 KK |
251 | if (IS_ENABLED(CONFIG_BOARD_TYPES) && |
252 | !IS_ENABLED(CONFIG_DISPLAY_BOARDINFO_LATE)) { | |
253 | /* | |
254 | * If revision was not set by late display boardinfo, | |
255 | * set it here. At this point regulators should be already | |
256 | * available. | |
257 | */ | |
258 | set_board_revision(); | |
259 | } | |
260 | ||
431a1c56 PW |
261 | #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG |
262 | set_board_info(); | |
263 | #endif | |
431a1c56 PW |
264 | #ifdef CONFIG_CMD_BMP |
265 | if (panel_info.logo_on) | |
266 | draw_logo(); | |
267 | #endif | |
268 | return 0; | |
269 | } | |
270 | #endif | |
aa8e00fa JS |
271 | |
272 | void reset_misc(void) | |
273 | { | |
274 | struct gpio_desc gpio = {}; | |
275 | int node; | |
276 | ||
277 | node = fdt_node_offset_by_compatible(gd->fdt_blob, 0, | |
278 | "samsung,emmc-reset"); | |
279 | if (node < 0) | |
280 | return; | |
281 | ||
150c5afe SG |
282 | gpio_request_by_name_nodev(offset_to_ofnode(node), "reset-gpio", 0, |
283 | &gpio, GPIOD_IS_OUT); | |
aa8e00fa JS |
284 | |
285 | if (dm_gpio_is_valid(&gpio)) { | |
286 | /* | |
287 | * Reset eMMC | |
288 | * | |
289 | * FIXME: Need to optimize delay time. Minimum 1usec pulse is | |
290 | * required by 'JEDEC Standard No.84-A441' (eMMC) | |
291 | * document but real delay time is expected to greater | |
292 | * than 1usec. | |
293 | */ | |
294 | dm_gpio_set_value(&gpio, 0); | |
295 | mdelay(10); | |
296 | dm_gpio_set_value(&gpio, 1); | |
297 | } | |
298 | } | |
28f393cd ŁM |
299 | |
300 | int board_usb_cleanup(int index, enum usb_init_type init) | |
301 | { | |
302a7d00 JS |
302 | #ifdef CONFIG_USB_DWC3 |
303 | dwc3_uboot_exit(index); | |
304 | #endif | |
28f393cd ŁM |
305 | return 0; |
306 | } | |
86c88711 MS |
307 | |
308 | int mmc_get_env_dev(void) | |
309 | { | |
310 | return get_boot_mmc_dev(); | |
311 | } |