[J-u-boot.git] / arch / arm / dts / socfpga_arria10_socdk_sdmmc_handoff.dtsi

// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
 * Copyright (C) 2016-2017 Intel Corporation
 *
 *<auto-generated>
 *	This code was generated by a tool based on
 *	handoffs from both Qsys and Quartus.
 *
 *	Changes to this file may be lost if
 *	the code is regenerated.
 *</auto-generated>
 */

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	model = "SOCFPGA Arria10 Dev Kit";	/* Bootloader setting: uboot.model */

	/* Clock sources */
	clocks {
		#address-cells = <1>;
		#size-cells = <1>;

		/* Clock source: altera_arria10_hps_eosc1 */
		altera_arria10_hps_eosc1: altera_arria10_hps_eosc1 {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <25000000>;
			clock-output-names = "altera_arria10_hps_eosc1-clk";
		};

		/* Clock source: altera_arria10_hps_cb_intosc_ls */
		altera_arria10_hps_cb_intosc_ls: altera_arria10_hps_cb_intosc_ls {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <60000000>;
			clock-output-names = "altera_arria10_hps_cb_intosc_ls-clk";
		};

		/* Clock source: altera_arria10_hps_f2h_free */
		altera_arria10_hps_f2h_free: altera_arria10_hps_f2h_free {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <200000000>;
			clock-output-names = "altera_arria10_hps_f2h_free-clk";
		};
	};

	/*
	 * Driver: altera_arria10_soc_clock_manager_arria10_uboot_driver
	 * Version: 1.0
	 * Binding: device
	 */
	i_clk_mgr: clock_manager@0xffd04000 {
		compatible = "altr,socfpga-a10-clk-init";
		reg = <0xffd04000 0x00000200>;
		reg-names = "soc_clock_manager_OCP_SLV";

		/* Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_mainpllgrp */
		mainpll {
			vco0-psrc = <0>;	/* Field: vco0.psrc */
			vco1-denom = <1>;	/* Field: vco1.denom */
			vco1-numer = <191>;	/* Field: vco1.numer */
			mpuclk-cnt = <0>;	/* Field: mpuclk.cnt */
			mpuclk-src = <0>;	/* Field: mpuclk.src */
			nocclk-cnt = <0>;	/* Field: nocclk.cnt */
			nocclk-src = <0>;	/* Field: nocclk.src */
			cntr2clk-cnt = <900>;	/* Field: cntr2clk.cnt */
			cntr3clk-cnt = <900>;	/* Field: cntr3clk.cnt */
			cntr4clk-cnt = <900>;	/* Field: cntr4clk.cnt */
			cntr5clk-cnt = <900>;	/* Field: cntr5clk.cnt */
			cntr6clk-cnt = <900>;	/* Field: cntr6clk.cnt */
			cntr7clk-cnt = <900>;	/* Field: cntr7clk.cnt */
			cntr7clk-src = <0>;	/* Field: cntr7clk.src */
			cntr8clk-cnt = <900>;	/* Field: cntr8clk.cnt */
			cntr9clk-cnt = <900>;	/* Field: cntr9clk.cnt */
			cntr9clk-src = <0>;	/* Field: cntr9clk.src */
			cntr15clk-cnt = <900>;	/* Field: cntr15clk.cnt */
			nocdiv-l4mainclk = <0>;	/* Field: nocdiv.l4mainclk */
			nocdiv-l4mpclk = <0>;	/* Field: nocdiv.l4mpclk */
			nocdiv-l4spclk = <2>;	/* Field: nocdiv.l4spclk */
			nocdiv-csatclk = <0>;	/* Field: nocdiv.csatclk */
			nocdiv-cstraceclk = <1>;	/* Field: nocdiv.cstraceclk */
			nocdiv-cspdbgclk = <1>;	/* Field: nocdiv.cspdbgclk */
		};

		/* Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_perpllgrp */
		perpll {
			vco0-psrc = <0>;	/* Field: vco0.psrc */
			vco1-denom = <1>;	/* Field: vco1.denom */
			vco1-numer = <159>;	/* Field: vco1.numer */
			cntr2clk-cnt = <7>;	/* Field: cntr2clk.cnt */
			cntr2clk-src = <1>;	/* Field: cntr2clk.src */
			cntr3clk-cnt = <900>;	/* Field: cntr3clk.cnt */
			cntr3clk-src = <1>;	/* Field: cntr3clk.src */
			cntr4clk-cnt = <19>;	/* Field: cntr4clk.cnt */
			cntr4clk-src = <1>;	/* Field: cntr4clk.src */
			cntr5clk-cnt = <499>;	/* Field: cntr5clk.cnt */
			cntr5clk-src = <1>;	/* Field: cntr5clk.src */
			cntr6clk-cnt = <9>;	/* Field: cntr6clk.cnt */
			cntr6clk-src = <1>;	/* Field: cntr6clk.src */
			cntr7clk-cnt = <900>;	/* Field: cntr7clk.cnt */
			cntr8clk-cnt = <900>;	/* Field: cntr8clk.cnt */
			cntr8clk-src = <0>;	/* Field: cntr8clk.src */
			cntr9clk-cnt = <900>;	/* Field: cntr9clk.cnt */
			emacctl-emac0sel = <0>;	/* Field: emacctl.emac0sel */
			emacctl-emac1sel = <0>;	/* Field: emacctl.emac1sel */
			emacctl-emac2sel = <0>;	/* Field: emacctl.emac2sel */
			gpiodiv-gpiodbclk = <32000>;	/* Field: gpiodiv.gpiodbclk */
		};

		/* Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_alteragrp */
		alteragrp {
			nocclk = <0x0384000b>;	/* Register: nocclk */
			mpuclk = <0x03840001>;	/* Register: mpuclk */
		};
	};

	/*
	 * Driver: altera_arria10_soc_3v_io48_pin_mux_arria10_uboot_driver
	 * Version: 1.0
	 * Binding: pinmux
	 */
	i_io48_pin_mux: pinmux@0xffd07000 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "pinctrl-single";
		reg = <0xffd07000 0x00000800>;
		reg-names = "soc_3v_io48_pin_mux_OCP_SLV";

		/* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_shared_3v_io_grp */
		shared {
			reg = <0xffd07000 0x00000200>;
			pinctrl-single,register-width = <32>;
			pinctrl-single,function-mask = <0x0000000f>;
			pinctrl-single,pins =
				<0x00000000 0x00000008>,	/* Register: pinmux_shared_io_q1_1 */
				<0x00000004 0x00000008>,	/* Register: pinmux_shared_io_q1_2 */
				<0x00000008 0x00000008>,	/* Register: pinmux_shared_io_q1_3 */
				<0x0000000c 0x00000008>,	/* Register: pinmux_shared_io_q1_4 */
				<0x00000010 0x00000008>,	/* Register: pinmux_shared_io_q1_5 */
				<0x00000014 0x00000008>,	/* Register: pinmux_shared_io_q1_6 */
				<0x00000018 0x00000008>,	/* Register: pinmux_shared_io_q1_7 */
				<0x0000001c 0x00000008>,	/* Register: pinmux_shared_io_q1_8 */
				<0x00000020 0x00000008>,	/* Register: pinmux_shared_io_q1_9 */
				<0x00000024 0x00000008>,	/* Register: pinmux_shared_io_q1_10 */
				<0x00000028 0x00000008>,	/* Register: pinmux_shared_io_q1_11 */
				<0x0000002c 0x00000008>,	/* Register: pinmux_shared_io_q1_12 */
				<0x00000030 0x00000004>,	/* Register: pinmux_shared_io_q2_1 */
				<0x00000034 0x00000004>,	/* Register: pinmux_shared_io_q2_2 */
				<0x00000038 0x00000004>,	/* Register: pinmux_shared_io_q2_3 */
				<0x0000003c 0x00000004>,	/* Register: pinmux_shared_io_q2_4 */
				<0x00000040 0x00000004>,	/* Register: pinmux_shared_io_q2_5 */
				<0x00000044 0x00000004>,	/* Register: pinmux_shared_io_q2_6 */
				<0x00000048 0x00000004>,	/* Register: pinmux_shared_io_q2_7 */
				<0x0000004c 0x00000004>,	/* Register: pinmux_shared_io_q2_8 */
				<0x00000050 0x00000004>,	/* Register: pinmux_shared_io_q2_9 */
				<0x00000054 0x00000004>,	/* Register: pinmux_shared_io_q2_10 */
				<0x00000058 0x00000004>,	/* Register: pinmux_shared_io_q2_11 */
				<0x0000005c 0x00000004>,	/* Register: pinmux_shared_io_q2_12 */
				<0x00000060 0x00000003>,	/* Register: pinmux_shared_io_q3_1 */
				<0x00000064 0x00000003>,	/* Register: pinmux_shared_io_q3_2 */
				<0x00000068 0x00000003>,	/* Register: pinmux_shared_io_q3_3 */
				<0x0000006c 0x00000003>,	/* Register: pinmux_shared_io_q3_4 */
				<0x00000070 0x00000003>,	/* Register: pinmux_shared_io_q3_5 */
				<0x00000074 0x0000000f>,	/* Register: pinmux_shared_io_q3_6 */
				<0x00000078 0x0000000a>,	/* Register: pinmux_shared_io_q3_7 */
				<0x0000007c 0x0000000a>,	/* Register: pinmux_shared_io_q3_8 */
				<0x00000080 0x0000000a>,	/* Register: pinmux_shared_io_q3_9 */
				<0x00000084 0x0000000a>,	/* Register: pinmux_shared_io_q3_10 */
				<0x00000088 0x00000001>,	/* Register: pinmux_shared_io_q3_11 */
				<0x0000008c 0x00000001>,	/* Register: pinmux_shared_io_q3_12 */
				<0x00000090 0x00000000>,	/* Register: pinmux_shared_io_q4_1 */
				<0x00000094 0x00000000>,	/* Register: pinmux_shared_io_q4_2 */
				<0x00000098 0x0000000f>,	/* Register: pinmux_shared_io_q4_3 */
				<0x0000009c 0x0000000c>,	/* Register: pinmux_shared_io_q4_4 */
				<0x000000a0 0x0000000f>,	/* Register: pinmux_shared_io_q4_5 */
				<0x000000a4 0x0000000f>,	/* Register: pinmux_shared_io_q4_6 */
				<0x000000a8 0x0000000a>,	/* Register: pinmux_shared_io_q4_7 */
				<0x000000ac 0x0000000a>,	/* Register: pinmux_shared_io_q4_8 */
				<0x000000b0 0x0000000c>,	/* Register: pinmux_shared_io_q4_9 */
				<0x000000b4 0x0000000c>,	/* Register: pinmux_shared_io_q4_10 */
				<0x000000b8 0x0000000c>,	/* Register: pinmux_shared_io_q4_11 */
				<0x000000bc 0x0000000c>;	/* Register: pinmux_shared_io_q4_12 */
		};

		/* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_dedicated_io_grp */
		dedicated {
			reg = <0xffd07200 0x00000200>;
			pinctrl-single,register-width = <32>;
			pinctrl-single,function-mask = <0x0000000f>;
			pinctrl-single,pins =
				<0x0000000c 0x00000008>,	/* Register: pinmux_dedicated_io_4 */
				<0x00000010 0x00000008>,	/* Register: pinmux_dedicated_io_5 */
				<0x00000014 0x00000008>,	/* Register: pinmux_dedicated_io_6 */
				<0x00000018 0x00000008>,	/* Register: pinmux_dedicated_io_7 */
				<0x0000001c 0x00000008>,	/* Register: pinmux_dedicated_io_8 */
				<0x00000020 0x00000008>,	/* Register: pinmux_dedicated_io_9 */
				<0x00000024 0x0000000a>,	/* Register: pinmux_dedicated_io_10 */
				<0x00000028 0x0000000a>,	/* Register: pinmux_dedicated_io_11 */
				<0x0000002c 0x00000008>,	/* Register: pinmux_dedicated_io_12 */
				<0x00000030 0x00000008>,	/* Register: pinmux_dedicated_io_13 */
				<0x00000034 0x00000008>,	/* Register: pinmux_dedicated_io_14 */
				<0x00000038 0x00000008>,	/* Register: pinmux_dedicated_io_15 */
				<0x0000003c 0x0000000d>,	/* Register: pinmux_dedicated_io_16 */
				<0x00000040 0x0000000d>;	/* Register: pinmux_dedicated_io_17 */
		};

		/* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_dedicated_io_grp */
		dedicated_cfg {
			reg = <0xffd07200 0x00000200>;
			pinctrl-single,register-width = <32>;
			pinctrl-single,function-mask = <0x003f3f3f>;
			pinctrl-single,pins =
				<0x00000100 0x00000101>,	/* Register: configuration_dedicated_io_bank */
				<0x00000104 0x000b080a>,	/* Register: configuration_dedicated_io_1 */
				<0x00000108 0x000b080a>,	/* Register: configuration_dedicated_io_2 */
				<0x0000010c 0x000b080a>,	/* Register: configuration_dedicated_io_3 */
				<0x00000110 0x000a282a>,	/* Register: configuration_dedicated_io_4 */
				<0x00000114 0x000a282a>,	/* Register: configuration_dedicated_io_5 */
				<0x00000118 0x0008282a>,	/* Register: configuration_dedicated_io_6 */
				<0x0000011c 0x000a282a>,	/* Register: configuration_dedicated_io_7 */
				<0x00000120 0x000a282a>,	/* Register: configuration_dedicated_io_8 */
				<0x00000124 0x000a282a>,	/* Register: configuration_dedicated_io_9 */
				<0x00000128 0x00090000>,	/* Register: configuration_dedicated_io_10 */
				<0x0000012c 0x00090000>,	/* Register: configuration_dedicated_io_11 */
				<0x00000130 0x000b282a>,	/* Register: configuration_dedicated_io_12 */
				<0x00000134 0x000b282a>,	/* Register: configuration_dedicated_io_13 */
				<0x00000138 0x000b282a>,	/* Register: configuration_dedicated_io_14 */
				<0x0000013c 0x000b282a>,	/* Register: configuration_dedicated_io_15 */
				<0x00000140 0x0008282a>,	/* Register: configuration_dedicated_io_16 */
				<0x00000144 0x000a282a>;	/* Register: configuration_dedicated_io_17 */
		};

		/* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_fpga_interface_grp */
		fpga {
			reg = <0xffd07400 0x00000100>;
			pinctrl-single,register-width = <32>;
			pinctrl-single,function-mask = <0x00000001>;
			pinctrl-single,pins =
				<0x00000000 0x00000000>,	/* Register: pinmux_emac0_usefpga */
				<0x00000004 0x00000000>,	/* Register: pinmux_emac1_usefpga */
				<0x00000008 0x00000000>,	/* Register: pinmux_emac2_usefpga */
				<0x0000000c 0x00000000>,	/* Register: pinmux_i2c0_usefpga */
				<0x00000010 0x00000000>,	/* Register: pinmux_i2c1_usefpga */
				<0x00000014 0x00000000>,	/* Register: pinmux_i2c_emac0_usefpga */
				<0x00000018 0x00000000>,	/* Register: pinmux_i2c_emac1_usefpga */
				<0x0000001c 0x00000000>,	/* Register: pinmux_i2c_emac2_usefpga */
				<0x00000020 0x00000000>,	/* Register: pinmux_nand_usefpga */
				<0x00000024 0x00000000>,	/* Register: pinmux_qspi_usefpga */
				<0x00000028 0x00000000>,	/* Register: pinmux_sdmmc_usefpga */
				<0x0000002c 0x00000000>,	/* Register: pinmux_spim0_usefpga */
				<0x00000030 0x00000000>,	/* Register: pinmux_spim1_usefpga */
				<0x00000034 0x00000000>,	/* Register: pinmux_spis0_usefpga */
				<0x00000038 0x00000000>,	/* Register: pinmux_spis1_usefpga */
				<0x0000003c 0x00000000>,	/* Register: pinmux_uart0_usefpga */
				<0x00000040 0x00000000>;	/* Register: pinmux_uart1_usefpga */
		};
	};

	/*
	 * Driver: altera_arria10_soc_noc_arria10_uboot_driver
	 * Version: 1.0
	 * Binding: device
	 */
	i_noc: noc@0xffd10000 {
		compatible = "altr,socfpga-a10-noc";
		reg = <0xffd10000 0x00008000>;
		reg-names = "mpu_m0";

		firewall {
			/*
			 * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.mpuregion0addr.base
			 * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.mpuregion0addr.limit
			 */
			mpu0 = <0x00000000 0x0000ffff>;
			/*
			 * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.hpsregion0addr.base
			 * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.hpsregion0addr.limit
			 */
			l3-0 = <0x00000000 0x0000ffff>;
			/*
			 * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram0region0addr.base
			 * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram0region0addr.limit
			 */
			fpga2sdram0-0 = <0x00000000 0x0000ffff>;
			/*
			 * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram1region0addr.base
			 * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram1region0addr.limit
			 */
			fpga2sdram1-0 = <0x00000000 0x0000ffff>;
			/*
			 * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram2region0addr.base
			 * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram2region0addr.limit
			 */
			fpga2sdram2-0 = <0x00000000 0x0000ffff>;
		};
	};

	hps_fpgabridge0: fpgabridge@0 {
		compatible = "altr,socfpga-hps2fpga-bridge";
		init-val = <1>;
	};

	hps_fpgabridge1: fpgabridge@1 {
		compatible = "altr,socfpga-lwhps2fpga-bridge";
		init-val = <1>;
	};

	hps_fpgabridge2: fpgabridge@2 {
		compatible = "altr,socfpga-fpga2hps-bridge";
		init-val = <1>;
	};

	hps_fpgabridge3: fpgabridge@3 {
		compatible = "altr,socfpga-fpga2sdram0-bridge";
		init-val = <1>;
	};

	hps_fpgabridge4: fpgabridge@4 {
		compatible = "altr,socfpga-fpga2sdram1-bridge";
		init-val = <0>;
	};

	hps_fpgabridge5: fpgabridge@5 {
		compatible = "altr,socfpga-fpga2sdram2-bridge";
		init-val = <1>;
	};
};
Commit	Line	Data
4549e789	1	// SPDX-License-Identifier: GPL-2.0+ OR X11
3d5f7c5a LFT	2	/*
	3	* Copyright (C) 2016-2017 Intel Corporation
	4	*
3d5f7c5a LFT	5	*<auto-generated>
	6	* This code was generated by a tool based on
	7	* handoffs from both Qsys and Quartus.
	8	*
	9	* Changes to this file may be lost if
	10	* the code is regenerated.
	11	*</auto-generated>
	12	*/
	13
3d5f7c5a	14	/ {
6b49cdd2 MV	15	#address-cells = <1>;
	16	#size-cells = <1>;
	17	model = "SOCFPGA Arria10 Dev Kit"; /* Bootloader setting: uboot.model */
3d5f7c5a	18
6b49cdd2 MV	19	/* Clock sources */
6b49cdd2 MV	20	clocks {
6b49cdd2 MV	21	#address-cells = <1>;
	22	#size-cells = <1>;
	23
	24	/* Clock source: altera_arria10_hps_eosc1 */
	25	altera_arria10_hps_eosc1: altera_arria10_hps_eosc1 {
6b49cdd2 MV	26	compatible = "fixed-clock";
	27	#clock-cells = <0>;
	28	clock-frequency = <25000000>;
	29	clock-output-names = "altera_arria10_hps_eosc1-clk";
	30	};
	31
	32	/* Clock source: altera_arria10_hps_cb_intosc_ls */
	33	altera_arria10_hps_cb_intosc_ls: altera_arria10_hps_cb_intosc_ls {
6b49cdd2 MV	34	compatible = "fixed-clock";
	35	#clock-cells = <0>;
	36	clock-frequency = <60000000>;
	37	clock-output-names = "altera_arria10_hps_cb_intosc_ls-clk";
	38	};
	39
	40	/* Clock source: altera_arria10_hps_f2h_free */
	41	altera_arria10_hps_f2h_free: altera_arria10_hps_f2h_free {
6b49cdd2 MV	42	compatible = "fixed-clock";
	43	#clock-cells = <0>;
	44	clock-frequency = <200000000>;
	45	clock-output-names = "altera_arria10_hps_f2h_free-clk";
	46	};
	47	};
	48
	49	/*
	50	* Driver: altera_arria10_soc_clock_manager_arria10_uboot_driver
	51	* Version: 1.0
	52	* Binding: device
	53	*/
	54	i_clk_mgr: clock_manager@0xffd04000 {
6b49cdd2 MV	55	compatible = "altr,socfpga-a10-clk-init";
	56	reg = <0xffd04000 0x00000200>;
	57	reg-names = "soc_clock_manager_OCP_SLV";
	58
	59	/* Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_mainpllgrp */
	60	mainpll {
6b49cdd2 MV	61	vco0-psrc = <0>; /* Field: vco0.psrc */
	62	vco1-denom = <1>; /* Field: vco1.denom */
	63	vco1-numer = <191>; /* Field: vco1.numer */
	64	mpuclk-cnt = <0>; /* Field: mpuclk.cnt */
	65	mpuclk-src = <0>; /* Field: mpuclk.src */
	66	nocclk-cnt = <0>; /* Field: nocclk.cnt */
	67	nocclk-src = <0>; /* Field: nocclk.src */
	68	cntr2clk-cnt = <900>; /* Field: cntr2clk.cnt */
	69	cntr3clk-cnt = <900>; /* Field: cntr3clk.cnt */
	70	cntr4clk-cnt = <900>; /* Field: cntr4clk.cnt */
	71	cntr5clk-cnt = <900>; /* Field: cntr5clk.cnt */
	72	cntr6clk-cnt = <900>; /* Field: cntr6clk.cnt */
	73	cntr7clk-cnt = <900>; /* Field: cntr7clk.cnt */
	74	cntr7clk-src = <0>; /* Field: cntr7clk.src */
	75	cntr8clk-cnt = <900>; /* Field: cntr8clk.cnt */
	76	cntr9clk-cnt = <900>; /* Field: cntr9clk.cnt */
	77	cntr9clk-src = <0>; /* Field: cntr9clk.src */
	78	cntr15clk-cnt = <900>; /* Field: cntr15clk.cnt */
	79	nocdiv-l4mainclk = <0>; /* Field: nocdiv.l4mainclk */
	80	nocdiv-l4mpclk = <0>; /* Field: nocdiv.l4mpclk */
	81	nocdiv-l4spclk = <2>; /* Field: nocdiv.l4spclk */
	82	nocdiv-csatclk = <0>; /* Field: nocdiv.csatclk */
	83	nocdiv-cstraceclk = <1>; /* Field: nocdiv.cstraceclk */
	84	nocdiv-cspdbgclk = <1>; /* Field: nocdiv.cspdbgclk */
	85	};
3d5f7c5a	86
6b49cdd2 MV	87	/* Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_perpllgrp */
6b49cdd2 MV	88	perpll {
6b49cdd2 MV	89	vco0-psrc = <0>; /* Field: vco0.psrc */
	90	vco1-denom = <1>; /* Field: vco1.denom */
	91	vco1-numer = <159>; /* Field: vco1.numer */
	92	cntr2clk-cnt = <7>; /* Field: cntr2clk.cnt */
	93	cntr2clk-src = <1>; /* Field: cntr2clk.src */
	94	cntr3clk-cnt = <900>; /* Field: cntr3clk.cnt */
	95	cntr3clk-src = <1>; /* Field: cntr3clk.src */
	96	cntr4clk-cnt = <19>; /* Field: cntr4clk.cnt */
	97	cntr4clk-src = <1>; /* Field: cntr4clk.src */
	98	cntr5clk-cnt = <499>; /* Field: cntr5clk.cnt */
	99	cntr5clk-src = <1>; /* Field: cntr5clk.src */
	100	cntr6clk-cnt = <9>; /* Field: cntr6clk.cnt */
	101	cntr6clk-src = <1>; /* Field: cntr6clk.src */
	102	cntr7clk-cnt = <900>; /* Field: cntr7clk.cnt */
	103	cntr8clk-cnt = <900>; /* Field: cntr8clk.cnt */
	104	cntr8clk-src = <0>; /* Field: cntr8clk.src */
	105	cntr9clk-cnt = <900>; /* Field: cntr9clk.cnt */
	106	emacctl-emac0sel = <0>; /* Field: emacctl.emac0sel */
	107	emacctl-emac1sel = <0>; /* Field: emacctl.emac1sel */
	108	emacctl-emac2sel = <0>; /* Field: emacctl.emac2sel */
	109	gpiodiv-gpiodbclk = <32000>; /* Field: gpiodiv.gpiodbclk */
	110	};
3d5f7c5a	111
6b49cdd2 MV	112	/* Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_alteragrp */
6b49cdd2 MV	113	alteragrp {
6b49cdd2 MV	114	nocclk = <0x0384000b>; /* Register: nocclk */
	115	mpuclk = <0x03840001>; /* Register: mpuclk */
	116	};
	117	};
3d5f7c5a	118
6b49cdd2 MV	119	/*
	120	* Driver: altera_arria10_soc_3v_io48_pin_mux_arria10_uboot_driver
	121	* Version: 1.0
	122	* Binding: pinmux
	123	*/
	124	i_io48_pin_mux: pinmux@0xffd07000 {
6b49cdd2 MV	125	#address-cells = <1>;
	126	#size-cells = <1>;
	127	compatible = "pinctrl-single";
	128	reg = <0xffd07000 0x00000800>;
	129	reg-names = "soc_3v_io48_pin_mux_OCP_SLV";
3d5f7c5a	130
6b49cdd2 MV	131	/* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_shared_3v_io_grp */
6b49cdd2 MV	132	shared {
6b49cdd2 MV	133	reg = <0xffd07000 0x00000200>;
	134	pinctrl-single,register-width = <32>;
	135	pinctrl-single,function-mask = <0x0000000f>;
	136	pinctrl-single,pins =
	137	<0x00000000 0x00000008>, /* Register: pinmux_shared_io_q1_1 */
	138	<0x00000004 0x00000008>, /* Register: pinmux_shared_io_q1_2 */
	139	<0x00000008 0x00000008>, /* Register: pinmux_shared_io_q1_3 */
	140	<0x0000000c 0x00000008>, /* Register: pinmux_shared_io_q1_4 */
	141	<0x00000010 0x00000008>, /* Register: pinmux_shared_io_q1_5 */
	142	<0x00000014 0x00000008>, /* Register: pinmux_shared_io_q1_6 */
	143	<0x00000018 0x00000008>, /* Register: pinmux_shared_io_q1_7 */
	144	<0x0000001c 0x00000008>, /* Register: pinmux_shared_io_q1_8 */
	145	<0x00000020 0x00000008>, /* Register: pinmux_shared_io_q1_9 */
	146	<0x00000024 0x00000008>, /* Register: pinmux_shared_io_q1_10 */
	147	<0x00000028 0x00000008>, /* Register: pinmux_shared_io_q1_11 */
	148	<0x0000002c 0x00000008>, /* Register: pinmux_shared_io_q1_12 */
	149	<0x00000030 0x00000004>, /* Register: pinmux_shared_io_q2_1 */
	150	<0x00000034 0x00000004>, /* Register: pinmux_shared_io_q2_2 */
	151	<0x00000038 0x00000004>, /* Register: pinmux_shared_io_q2_3 */
	152	<0x0000003c 0x00000004>, /* Register: pinmux_shared_io_q2_4 */
	153	<0x00000040 0x00000004>, /* Register: pinmux_shared_io_q2_5 */
	154	<0x00000044 0x00000004>, /* Register: pinmux_shared_io_q2_6 */
	155	<0x00000048 0x00000004>, /* Register: pinmux_shared_io_q2_7 */
	156	<0x0000004c 0x00000004>, /* Register: pinmux_shared_io_q2_8 */
	157	<0x00000050 0x00000004>, /* Register: pinmux_shared_io_q2_9 */
	158	<0x00000054 0x00000004>, /* Register: pinmux_shared_io_q2_10 */
	159	<0x00000058 0x00000004>, /* Register: pinmux_shared_io_q2_11 */
	160	<0x0000005c 0x00000004>, /* Register: pinmux_shared_io_q2_12 */
	161	<0x00000060 0x00000003>, /* Register: pinmux_shared_io_q3_1 */
	162	<0x00000064 0x00000003>, /* Register: pinmux_shared_io_q3_2 */
	163	<0x00000068 0x00000003>, /* Register: pinmux_shared_io_q3_3 */
	164	<0x0000006c 0x00000003>, /* Register: pinmux_shared_io_q3_4 */
	165	<0x00000070 0x00000003>, /* Register: pinmux_shared_io_q3_5 */
	166	<0x00000074 0x0000000f>, /* Register: pinmux_shared_io_q3_6 */
	167	<0x00000078 0x0000000a>, /* Register: pinmux_shared_io_q3_7 */
	168	<0x0000007c 0x0000000a>, /* Register: pinmux_shared_io_q3_8 */
	169	<0x00000080 0x0000000a>, /* Register: pinmux_shared_io_q3_9 */
	170	<0x00000084 0x0000000a>, /* Register: pinmux_shared_io_q3_10 */
	171	<0x00000088 0x00000001>, /* Register: pinmux_shared_io_q3_11 */
	172	<0x0000008c 0x00000001>, /* Register: pinmux_shared_io_q3_12 */
	173	<0x00000090 0x00000000>, /* Register: pinmux_shared_io_q4_1 */
	174	<0x00000094 0x00000000>, /* Register: pinmux_shared_io_q4_2 */
	175	<0x00000098 0x0000000f>, /* Register: pinmux_shared_io_q4_3 */
	176	<0x0000009c 0x0000000c>, /* Register: pinmux_shared_io_q4_4 */
	177	<0x000000a0 0x0000000f>, /* Register: pinmux_shared_io_q4_5 */
	178	<0x000000a4 0x0000000f>, /* Register: pinmux_shared_io_q4_6 */
	179	<0x000000a8 0x0000000a>, /* Register: pinmux_shared_io_q4_7 */
	180	<0x000000ac 0x0000000a>, /* Register: pinmux_shared_io_q4_8 */
	181	<0x000000b0 0x0000000c>, /* Register: pinmux_shared_io_q4_9 */
	182	<0x000000b4 0x0000000c>, /* Register: pinmux_shared_io_q4_10 */
	183	<0x000000b8 0x0000000c>, /* Register: pinmux_shared_io_q4_11 */
	184	<0x000000bc 0x0000000c>; /* Register: pinmux_shared_io_q4_12 */
	185	};
	186
	187	/* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_dedicated_io_grp */
	188	dedicated {
6b49cdd2 MV	189	reg = <0xffd07200 0x00000200>;
	190	pinctrl-single,register-width = <32>;
	191	pinctrl-single,function-mask = <0x0000000f>;
	192	pinctrl-single,pins =
	193	<0x0000000c 0x00000008>, /* Register: pinmux_dedicated_io_4 */
	194	<0x00000010 0x00000008>, /* Register: pinmux_dedicated_io_5 */
	195	<0x00000014 0x00000008>, /* Register: pinmux_dedicated_io_6 */
	196	<0x00000018 0x00000008>, /* Register: pinmux_dedicated_io_7 */
	197	<0x0000001c 0x00000008>, /* Register: pinmux_dedicated_io_8 */
	198	<0x00000020 0x00000008>, /* Register: pinmux_dedicated_io_9 */
	199	<0x00000024 0x0000000a>, /* Register: pinmux_dedicated_io_10 */
	200	<0x00000028 0x0000000a>, /* Register: pinmux_dedicated_io_11 */
	201	<0x0000002c 0x00000008>, /* Register: pinmux_dedicated_io_12 */
	202	<0x00000030 0x00000008>, /* Register: pinmux_dedicated_io_13 */
	203	<0x00000034 0x00000008>, /* Register: pinmux_dedicated_io_14 */
	204	<0x00000038 0x00000008>, /* Register: pinmux_dedicated_io_15 */
	205	<0x0000003c 0x0000000d>, /* Register: pinmux_dedicated_io_16 */
	206	<0x00000040 0x0000000d>; /* Register: pinmux_dedicated_io_17 */
	207	};
3d5f7c5a	208
6b49cdd2 MV	209	/* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_dedicated_io_grp */
6b49cdd2 MV	210	dedicated_cfg {
6b49cdd2 MV	211	reg = <0xffd07200 0x00000200>;
	212	pinctrl-single,register-width = <32>;
	213	pinctrl-single,function-mask = <0x003f3f3f>;
	214	pinctrl-single,pins =
	215	<0x00000100 0x00000101>, /* Register: configuration_dedicated_io_bank */
	216	<0x00000104 0x000b080a>, /* Register: configuration_dedicated_io_1 */
	217	<0x00000108 0x000b080a>, /* Register: configuration_dedicated_io_2 */
	218	<0x0000010c 0x000b080a>, /* Register: configuration_dedicated_io_3 */
	219	<0x00000110 0x000a282a>, /* Register: configuration_dedicated_io_4 */
	220	<0x00000114 0x000a282a>, /* Register: configuration_dedicated_io_5 */
	221	<0x00000118 0x0008282a>, /* Register: configuration_dedicated_io_6 */
	222	<0x0000011c 0x000a282a>, /* Register: configuration_dedicated_io_7 */
	223	<0x00000120 0x000a282a>, /* Register: configuration_dedicated_io_8 */
	224	<0x00000124 0x000a282a>, /* Register: configuration_dedicated_io_9 */
	225	<0x00000128 0x00090000>, /* Register: configuration_dedicated_io_10 */
	226	<0x0000012c 0x00090000>, /* Register: configuration_dedicated_io_11 */
	227	<0x00000130 0x000b282a>, /* Register: configuration_dedicated_io_12 */
	228	<0x00000134 0x000b282a>, /* Register: configuration_dedicated_io_13 */
	229	<0x00000138 0x000b282a>, /* Register: configuration_dedicated_io_14 */
	230	<0x0000013c 0x000b282a>, /* Register: configuration_dedicated_io_15 */
	231	<0x00000140 0x0008282a>, /* Register: configuration_dedicated_io_16 */
	232	<0x00000144 0x000a282a>; /* Register: configuration_dedicated_io_17 */
3d5f7c5a LFT	233	};
3d5f7c5a LFT	234
6b49cdd2 MV	235	/* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_fpga_interface_grp */
6b49cdd2 MV	236	fpga {
6b49cdd2 MV	237	reg = <0xffd07400 0x00000100>;
	238	pinctrl-single,register-width = <32>;
	239	pinctrl-single,function-mask = <0x00000001>;
	240	pinctrl-single,pins =
	241	<0x00000000 0x00000000>, /* Register: pinmux_emac0_usefpga */
	242	<0x00000004 0x00000000>, /* Register: pinmux_emac1_usefpga */
	243	<0x00000008 0x00000000>, /* Register: pinmux_emac2_usefpga */
	244	<0x0000000c 0x00000000>, /* Register: pinmux_i2c0_usefpga */
	245	<0x00000010 0x00000000>, /* Register: pinmux_i2c1_usefpga */
	246	<0x00000014 0x00000000>, /* Register: pinmux_i2c_emac0_usefpga */
	247	<0x00000018 0x00000000>, /* Register: pinmux_i2c_emac1_usefpga */
	248	<0x0000001c 0x00000000>, /* Register: pinmux_i2c_emac2_usefpga */
	249	<0x00000020 0x00000000>, /* Register: pinmux_nand_usefpga */
	250	<0x00000024 0x00000000>, /* Register: pinmux_qspi_usefpga */
	251	<0x00000028 0x00000000>, /* Register: pinmux_sdmmc_usefpga */
	252	<0x0000002c 0x00000000>, /* Register: pinmux_spim0_usefpga */
	253	<0x00000030 0x00000000>, /* Register: pinmux_spim1_usefpga */
	254	<0x00000034 0x00000000>, /* Register: pinmux_spis0_usefpga */
	255	<0x00000038 0x00000000>, /* Register: pinmux_spis1_usefpga */
	256	<0x0000003c 0x00000000>, /* Register: pinmux_uart0_usefpga */
	257	<0x00000040 0x00000000>; /* Register: pinmux_uart1_usefpga */
	258	};
	259	};
	260
	261	/*
	262	* Driver: altera_arria10_soc_noc_arria10_uboot_driver
	263	* Version: 1.0
	264	* Binding: device
	265	*/
	266	i_noc: noc@0xffd10000 {
6b49cdd2 MV	267	compatible = "altr,socfpga-a10-noc";
	268	reg = <0xffd10000 0x00008000>;
	269	reg-names = "mpu_m0";
3d5f7c5a	270
6b49cdd2	271	firewall {
3d5f7c5a	272	/*
6b49cdd2 MV	273	* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.mpuregion0addr.base
6b49cdd2 MV	274	* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.mpuregion0addr.limit
3d5f7c5a	275	*/
6b49cdd2	276	mpu0 = <0x00000000 0x0000ffff>;
3d5f7c5a	277	/*
6b49cdd2 MV	278	* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.hpsregion0addr.base
6b49cdd2 MV	279	* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.hpsregion0addr.limit
3d5f7c5a	280	*/
6b49cdd2	281	l3-0 = <0x00000000 0x0000ffff>;
3d5f7c5a	282	/*
6b49cdd2 MV	283	* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram0region0addr.base
6b49cdd2 MV	284	* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram0region0addr.limit
3d5f7c5a	285	*/
6b49cdd2	286	fpga2sdram0-0 = <0x00000000 0x0000ffff>;
3d5f7c5a	287	/*
6b49cdd2 MV	288	* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram1region0addr.base
6b49cdd2 MV	289	* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram1region0addr.limit
3d5f7c5a	290	*/
6b49cdd2 MV	291	fpga2sdram1-0 = <0x00000000 0x0000ffff>;
	292	/*
	293	* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram2region0addr.base
	294	* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram2region0addr.limit
	295	*/
	296	fpga2sdram2-0 = <0x00000000 0x0000ffff>;
3d5f7c5a	297	};
6b49cdd2	298	};
3d5f7c5a	299
6b49cdd2 MV	300	hps_fpgabridge0: fpgabridge@0 {
	301	compatible = "altr,socfpga-hps2fpga-bridge";
	302	init-val = <1>;
	303	};
3d5f7c5a	304
6b49cdd2 MV	305	hps_fpgabridge1: fpgabridge@1 {
	306	compatible = "altr,socfpga-lwhps2fpga-bridge";
	307	init-val = <1>;
	308	};
3d5f7c5a	309
6b49cdd2 MV	310	hps_fpgabridge2: fpgabridge@2 {
	311	compatible = "altr,socfpga-fpga2hps-bridge";
	312	init-val = <1>;
	313	};
3d5f7c5a	314
6b49cdd2 MV	315	hps_fpgabridge3: fpgabridge@3 {
	316	compatible = "altr,socfpga-fpga2sdram0-bridge";
	317	init-val = <1>;
	318	};
3d5f7c5a	319
6b49cdd2 MV	320	hps_fpgabridge4: fpgabridge@4 {
	321	compatible = "altr,socfpga-fpga2sdram1-bridge";
	322	init-val = <0>;
	323	};
3d5f7c5a	324
6b49cdd2 MV	325	hps_fpgabridge5: fpgabridge@5 {
	326	compatible = "altr,socfpga-fpga2sdram2-bridge";
	327	init-val = <1>;
3d5f7c5a LFT	328	};
3d5f7c5a LFT	329	};