[J-u-boot.git] / drivers / pci / pci_sh7751.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * SH7751 PCI Controller (PCIC) for U-Boot.
 * (C) Dustin McIntire ([email protected])
 * (C) 2007,2008 Nobuhiro Iwamatsu <[email protected]>
 */

#include <config.h>
#include <dm.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/pci.h>
#include <linux/bitops.h>
#include <linux/delay.h>

/* Register addresses and such */
#define SH7751_BCR1	(vu_long *)0xFF800000
#define SH7751_BCR2	(vu_short *)0xFF800004
#define SH7751_WCR1	(vu_long *)0xFF800008
#define SH7751_WCR2	(vu_long *)0xFF80000C
#define SH7751_WCR3	(vu_long *)0xFF800010
#define SH7751_MCR	(vu_long *)0xFF800014
#define SH7751_BCR3	(vu_short *)0xFF800050
#define SH7751_PCICONF0	(vu_long *)0xFE200000
#define SH7751_PCICONF1	(vu_long *)0xFE200004
#define SH7751_PCICONF2	(vu_long *)0xFE200008
#define SH7751_PCICONF3	(vu_long *)0xFE20000C
#define SH7751_PCICONF4	(vu_long *)0xFE200010
#define SH7751_PCICONF5	(vu_long *)0xFE200014
#define SH7751_PCICONF6	(vu_long *)0xFE200018
#define SH7751_PCICR	(vu_long *)0xFE200100
#define SH7751_PCILSR0	(vu_long *)0xFE200104
#define SH7751_PCILSR1	(vu_long *)0xFE200108
#define SH7751_PCILAR0	(vu_long *)0xFE20010C
#define SH7751_PCILAR1	(vu_long *)0xFE200110
#define SH7751_PCIMBR	(vu_long *)0xFE2001C4
#define SH7751_PCIIOBR	(vu_long *)0xFE2001C8
#define SH7751_PCIPINT	(vu_long *)0xFE2001CC
#define SH7751_PCIPINTM	(vu_long *)0xFE2001D0
#define SH7751_PCICLKR	(vu_long *)0xFE2001D4
#define SH7751_PCIBCR1	(vu_long *)0xFE2001E0
#define SH7751_PCIBCR2	(vu_long *)0xFE2001E4
#define SH7751_PCIWCR1	(vu_long *)0xFE2001E8
#define SH7751_PCIWCR2	(vu_long *)0xFE2001EC
#define SH7751_PCIWCR3	(vu_long *)0xFE2001F0
#define SH7751_PCIMCR	(vu_long *)0xFE2001F4
#define SH7751_PCIBCR3	(vu_long *)0xFE2001F8

#define BCR1_BREQEN		0x00080000
#define PCI_SH7751_ID		0x35051054
#define PCI_SH7751R_ID		0x350E1054
#define SH7751_PCICONF1_WCC	0x00000080
#define SH7751_PCICONF1_PER	0x00000040
#define SH7751_PCICONF1_BUM	0x00000004
#define SH7751_PCICONF1_MES	0x00000002
#define SH7751_PCICONF1_CMDS	0x000000C6
#define SH7751_PCI_HOST_BRIDGE	0x6
#define SH7751_PCICR_PREFIX	0xa5000000
#define SH7751_PCICR_PRST	0x00000002
#define SH7751_PCICR_CFIN	0x00000001
#define SH7751_PCIPINT_D3	0x00000002
#define SH7751_PCIPINT_D0	0x00000001
#define SH7751_PCICLKR_PREFIX	0xa5000000

#define SH7751_PCI_MEM_BASE	0xFD000000
#define SH7751_PCI_MEM_SIZE	0x01000000
#define SH7751_PCI_IO_BASE	0xFE240000
#define SH7751_PCI_IO_SIZE	0x00040000

#define SH7751_PCIPAR	(vu_long *)0xFE2001C0
#define SH7751_PCIPDR	(vu_long *)0xFE200220

#define p4_in(addr)	(*addr)
#define p4_out(data, addr) (*addr) = (data)

static int sh7751_pci_read_config(const struct udevice *dev, pci_dev_t bdf,
				  uint offset, ulong *value,
				  enum pci_size_t size)
{
	u32 addr, reg;

	addr = PCI_CONF1_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), offset);
	p4_out(addr, SH7751_PCIPAR);
	reg = p4_in(SH7751_PCIPDR);
	*value = pci_conv_32_to_size(reg, offset, size);

	return 0;
}

static int sh7751_pci_write_config(struct udevice *dev, pci_dev_t bdf,
				      uint offset, ulong value,
				      enum pci_size_t size)
{
	u32 addr, reg, old;

	addr = PCI_CONF1_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), offset);
	p4_out(addr, SH7751_PCIPAR);
	old = p4_in(SH7751_PCIPDR);
	reg = pci_conv_size_to_32(old, value, offset, size);
	p4_out(reg, SH7751_PCIPDR);

	return 0;
}

static int sh7751_pci_probe(struct udevice *dev)
{
	/* Double-check that we're a 7751 or 7751R chip */
	if (p4_in(SH7751_PCICONF0) != PCI_SH7751_ID
	    && p4_in(SH7751_PCICONF0) != PCI_SH7751R_ID) {
		printf("PCI: Unknown PCI host bridge.\n");
		return 1;
	}
	printf("PCI: SH7751 PCI host bridge found.\n");

	/* Double-check some BSC config settings */
	/* (Area 3 non-MPX 32-bit, PCI bus pins) */
	if ((p4_in(SH7751_BCR1) & 0x20008) == 0x20000) {
		printf("SH7751_BCR1 value is wrong(0x%08X)\n",
			(unsigned int)p4_in(SH7751_BCR1));
		return 2;
	}
	if ((p4_in(SH7751_BCR2) & 0xC0) != 0xC0) {
		printf("SH7751_BCR2 value is wrong(0x%08X)\n",
			(unsigned int)p4_in(SH7751_BCR2));
		return 3;
	}
	if (p4_in(SH7751_BCR2) & 0x01) {
		printf("SH7751_BCR2 value is wrong(0x%08X)\n",
			(unsigned int)p4_in(SH7751_BCR2));
		return 4;
	}

	/* Force BREQEN in BCR1 to allow PCIC access */
	p4_out((p4_in(SH7751_BCR1) | BCR1_BREQEN), SH7751_BCR1);

	/* Toggle PCI reset pin */
	p4_out((SH7751_PCICR_PREFIX | SH7751_PCICR_PRST), SH7751_PCICR);
	udelay(32);
	p4_out(SH7751_PCICR_PREFIX, SH7751_PCICR);

	/* Set cmd bits: WCC, PER, BUM, MES */
	/* (Addr/Data stepping, Parity enabled, Bus Master, Memory enabled) */
	p4_out(0xfb900047, SH7751_PCICONF1);	/* K.Kino */

	/* Define this host as the host bridge */
	p4_out((SH7751_PCI_HOST_BRIDGE << 24), SH7751_PCICONF2);

	/* Force PCI clock(s) on */
	p4_out(0, SH7751_PCICLKR);
	p4_out(0x03, SH7751_PCICLKR);

	/* Clear powerdown IRQs, also mask them (unused) */
	p4_out((SH7751_PCIPINT_D0 | SH7751_PCIPINT_D3), SH7751_PCIPINT);
	p4_out(0, SH7751_PCIPINTM);

	p4_out(0xab000001, SH7751_PCICONF4);

	/* Set up target memory mappings (for external DMA access) */
	/* Map both P0 and P2 range to Area 3 RAM for ease of use */
	p4_out(CFG_SYS_SDRAM_SIZE - 0x100000, SH7751_PCILSR0);
	p4_out(CFG_SYS_SDRAM_BASE & 0x1FF00000, SH7751_PCILAR0);
	p4_out(CFG_SYS_SDRAM_BASE & 0xFFF00000, SH7751_PCICONF5);

	p4_out(0, SH7751_PCILSR1);
	p4_out(0, SH7751_PCILAR1);
	p4_out(0xd0000000, SH7751_PCICONF6);

	/* Map memory window to same address on PCI bus */
	p4_out(SH7751_PCI_MEM_BASE, SH7751_PCIMBR);

	/* Map IO window to same address on PCI bus */
	p4_out(SH7751_PCI_IO_BASE, SH7751_PCIIOBR);

	/* set BREQEN */
	p4_out(inl(SH7751_BCR1) | 0x00080000, SH7751_BCR1);

	/* Copy BSC registers into PCI BSC */
	p4_out(inl(SH7751_BCR1), SH7751_PCIBCR1);
	p4_out(inw(SH7751_BCR2), SH7751_PCIBCR2);
	p4_out(inw(SH7751_BCR3), SH7751_PCIBCR3);
	p4_out(inl(SH7751_WCR1), SH7751_PCIWCR1);
	p4_out(inl(SH7751_WCR2), SH7751_PCIWCR2);
	p4_out(inl(SH7751_WCR3), SH7751_PCIWCR3);
	p4_out(inl(SH7751_MCR), SH7751_PCIMCR);

	/* Finally, set central function init complete */
	p4_out((SH7751_PCICR_PREFIX | SH7751_PCICR_CFIN), SH7751_PCICR);

	return 0;
}

static const struct dm_pci_ops sh7751_pci_ops = {
	.read_config	= sh7751_pci_read_config,
	.write_config	= sh7751_pci_write_config,
};

static const struct udevice_id sh7751_pci_ids[] = {
	{ .compatible = "renesas,pci-sh7751" },
	{ }
};

U_BOOT_DRIVER(sh7751_pci) = {
	.name		= "sh7751_pci",
	.id		= UCLASS_PCI,
	.of_match	= sh7751_pci_ids,
	.ops		= &sh7751_pci_ops,
	.probe		= sh7751_pci_probe,
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
28e5efde NI	2	/*
	3	* SH7751 PCI Controller (PCIC) for U-Boot.
	4	* (C) Dustin McIntire ([email protected])
	5	* (C) 2007,2008 Nobuhiro Iwamatsu <[email protected]>
28e5efde NI	6	*/
28e5efde NI	7
03de305e	8	#include <config.h>
72c2f4ac	9	#include <dm.h>
b5d10a13	10	#include <pci.h>
28e5efde NI	11	#include <asm/processor.h>
28e5efde NI	12	#include <asm/io.h>
b5d10a13	13	#include <asm/pci.h>
cd93d625	14	#include <linux/bitops.h>
c05ed00a	15	#include <linux/delay.h>
28e5efde NI	16
	17	/* Register addresses and such */
	18	#define SH7751_BCR1 (vu_long *)0xFF800000
b5d10a13	19	#define SH7751_BCR2 (vu_short *)0xFF800004
28e5efde NI	20	#define SH7751_WCR1 (vu_long *)0xFF800008
	21	#define SH7751_WCR2 (vu_long *)0xFF80000C
	22	#define SH7751_WCR3 (vu_long *)0xFF800010
	23	#define SH7751_MCR (vu_long *)0xFF800014
b5d10a13	24	#define SH7751_BCR3 (vu_short *)0xFF800050
72c2f4ac MV	25	#define SH7751_PCICONF0 (vu_long *)0xFE200000
	26	#define SH7751_PCICONF1 (vu_long *)0xFE200004
	27	#define SH7751_PCICONF2 (vu_long *)0xFE200008
	28	#define SH7751_PCICONF3 (vu_long *)0xFE20000C
	29	#define SH7751_PCICONF4 (vu_long *)0xFE200010
	30	#define SH7751_PCICONF5 (vu_long *)0xFE200014
	31	#define SH7751_PCICONF6 (vu_long *)0xFE200018
	32	#define SH7751_PCICR (vu_long *)0xFE200100
	33	#define SH7751_PCILSR0 (vu_long *)0xFE200104
	34	#define SH7751_PCILSR1 (vu_long *)0xFE200108
	35	#define SH7751_PCILAR0 (vu_long *)0xFE20010C
	36	#define SH7751_PCILAR1 (vu_long *)0xFE200110
	37	#define SH7751_PCIMBR (vu_long *)0xFE2001C4
	38	#define SH7751_PCIIOBR (vu_long *)0xFE2001C8
	39	#define SH7751_PCIPINT (vu_long *)0xFE2001CC
	40	#define SH7751_PCIPINTM (vu_long *)0xFE2001D0
	41	#define SH7751_PCICLKR (vu_long *)0xFE2001D4
	42	#define SH7751_PCIBCR1 (vu_long *)0xFE2001E0
	43	#define SH7751_PCIBCR2 (vu_long *)0xFE2001E4
	44	#define SH7751_PCIWCR1 (vu_long *)0xFE2001E8
	45	#define SH7751_PCIWCR2 (vu_long *)0xFE2001EC
	46	#define SH7751_PCIWCR3 (vu_long *)0xFE2001F0
	47	#define SH7751_PCIMCR (vu_long *)0xFE2001F4
	48	#define SH7751_PCIBCR3 (vu_long *)0xFE2001F8
	49
	50	#define BCR1_BREQEN 0x00080000
	51	#define PCI_SH7751_ID 0x35051054
	52	#define PCI_SH7751R_ID 0x350E1054
	53	#define SH7751_PCICONF1_WCC 0x00000080
	54	#define SH7751_PCICONF1_PER 0x00000040
	55	#define SH7751_PCICONF1_BUM 0x00000004
	56	#define SH7751_PCICONF1_MES 0x00000002
28e5efde NI	57	#define SH7751_PCICONF1_CMDS 0x000000C6
28e5efde NI	58	#define SH7751_PCI_HOST_BRIDGE 0x6
72c2f4ac MV	59	#define SH7751_PCICR_PREFIX 0xa5000000
	60	#define SH7751_PCICR_PRST 0x00000002
	61	#define SH7751_PCICR_CFIN 0x00000001
	62	#define SH7751_PCIPINT_D3 0x00000002
	63	#define SH7751_PCIPINT_D0 0x00000001
	64	#define SH7751_PCICLKR_PREFIX 0xa5000000
28e5efde	65
72c2f4ac MV	66	#define SH7751_PCI_MEM_BASE 0xFD000000
	67	#define SH7751_PCI_MEM_SIZE 0x01000000
	68	#define SH7751_PCI_IO_BASE 0xFE240000
	69	#define SH7751_PCI_IO_SIZE 0x00040000
28e5efde	70
72c2f4ac MV	71	#define SH7751_PCIPAR (vu_long *)0xFE2001C0
72c2f4ac MV	72	#define SH7751_PCIPDR (vu_long *)0xFE200220
28e5efde	73
b5d10a13 NI	74	#define p4_in(addr) (*addr)
b5d10a13 NI	75	#define p4_out(data, addr) (*addr) = (data)
28e5efde	76
c4e72c4a	77	static int sh7751_pci_read_config(const struct udevice *dev, pci_dev_t bdf,
72c2f4ac MV	78	uint offset, ulong *value,
	79	enum pci_size_t size)
	80	{
	81	u32 addr, reg;
72c2f4ac	82
2a67bf65	83	addr = PCI_CONF1_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), offset);
72c2f4ac MV	84	p4_out(addr, SH7751_PCIPAR);
	85	reg = p4_in(SH7751_PCIPDR);
	86	*value = pci_conv_32_to_size(reg, offset, size);
28e5efde NI	87
	88	return 0;
	89	}
	90
72c2f4ac MV	91	static int sh7751_pci_write_config(struct udevice *dev, pci_dev_t bdf,
	92	uint offset, ulong value,
	93	enum pci_size_t size)
28e5efde	94	{
72c2f4ac	95	u32 addr, reg, old;
72c2f4ac	96
2a67bf65	97	addr = PCI_CONF1_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), offset);
72c2f4ac MV	98	p4_out(addr, SH7751_PCIPAR);
	99	old = p4_in(SH7751_PCIPDR);
	100	reg = pci_conv_size_to_32(old, value, offset, size);
	101	p4_out(reg, SH7751_PCIPDR);
28e5efde NI	102
	103	return 0;
	104	}
	105
72c2f4ac	106	static int sh7751_pci_probe(struct udevice *dev)
28e5efde NI	107	{
	108	/* Double-check that we're a 7751 or 7751R chip */
	109	if (p4_in(SH7751_PCICONF0) != PCI_SH7751_ID
	110	&& p4_in(SH7751_PCICONF0) != PCI_SH7751R_ID) {
	111	printf("PCI: Unknown PCI host bridge.\n");
	112	return 1;
	113	}
	114	printf("PCI: SH7751 PCI host bridge found.\n");
	115
	116	/* Double-check some BSC config settings */
	117	/* (Area 3 non-MPX 32-bit, PCI bus pins) */
	118	if ((p4_in(SH7751_BCR1) & 0x20008) == 0x20000) {
b5d10a13 NI	119	printf("SH7751_BCR1 value is wrong(0x%08X)\n",
b5d10a13 NI	120	(unsigned int)p4_in(SH7751_BCR1));
28e5efde NI	121	return 2;
	122	}
	123	if ((p4_in(SH7751_BCR2) & 0xC0) != 0xC0) {
b5d10a13 NI	124	printf("SH7751_BCR2 value is wrong(0x%08X)\n",
b5d10a13 NI	125	(unsigned int)p4_in(SH7751_BCR2));
28e5efde NI	126	return 3;
	127	}
	128	if (p4_in(SH7751_BCR2) & 0x01) {
b5d10a13 NI	129	printf("SH7751_BCR2 value is wrong(0x%08X)\n",
b5d10a13 NI	130	(unsigned int)p4_in(SH7751_BCR2));
28e5efde NI	131	return 4;
	132	}
	133
	134	/* Force BREQEN in BCR1 to allow PCIC access */
	135	p4_out((p4_in(SH7751_BCR1) \| BCR1_BREQEN), SH7751_BCR1);
	136
	137	/* Toggle PCI reset pin */
	138	p4_out((SH7751_PCICR_PREFIX \| SH7751_PCICR_PRST), SH7751_PCICR);
	139	udelay(32);
	140	p4_out(SH7751_PCICR_PREFIX, SH7751_PCICR);
	141
	142	/* Set cmd bits: WCC, PER, BUM, MES */
	143	/* (Addr/Data stepping, Parity enabled, Bus Master, Memory enabled) */
	144	p4_out(0xfb900047, SH7751_PCICONF1); /* K.Kino */
	145
	146	/* Define this host as the host bridge */
	147	p4_out((SH7751_PCI_HOST_BRIDGE << 24), SH7751_PCICONF2);
	148
	149	/* Force PCI clock(s) on */
	150	p4_out(0, SH7751_PCICLKR);
	151	p4_out(0x03, SH7751_PCICLKR);
	152
	153	/* Clear powerdown IRQs, also mask them (unused) */
	154	p4_out((SH7751_PCIPINT_D0 \| SH7751_PCIPINT_D3), SH7751_PCIPINT);
	155	p4_out(0, SH7751_PCIPINTM);
	156
	157	p4_out(0xab000001, SH7751_PCICONF4);
	158
	159	/* Set up target memory mappings (for external DMA access) */
	160	/* Map both P0 and P2 range to Area 3 RAM for ease of use */
aa6e94de TR	161	p4_out(CFG_SYS_SDRAM_SIZE - 0x100000, SH7751_PCILSR0);
	162	p4_out(CFG_SYS_SDRAM_BASE & 0x1FF00000, SH7751_PCILAR0);
	163	p4_out(CFG_SYS_SDRAM_BASE & 0xFFF00000, SH7751_PCICONF5);
30391de7	164
28e5efde NI	165	p4_out(0, SH7751_PCILSR1);
28e5efde NI	166	p4_out(0, SH7751_PCILAR1);
28e5efde NI	167	p4_out(0xd0000000, SH7751_PCICONF6);
	168
	169	/* Map memory window to same address on PCI bus */
	170	p4_out(SH7751_PCI_MEM_BASE, SH7751_PCIMBR);
	171
	172	/* Map IO window to same address on PCI bus */
d44cf293	173	p4_out(SH7751_PCI_IO_BASE, SH7751_PCIIOBR);
28e5efde NI	174
	175	/* set BREQEN */
	176	p4_out(inl(SH7751_BCR1) \| 0x00080000, SH7751_BCR1);
	177
	178	/* Copy BSC registers into PCI BSC */
	179	p4_out(inl(SH7751_BCR1), SH7751_PCIBCR1);
a319f149 JCPV	180	p4_out(inw(SH7751_BCR2), SH7751_PCIBCR2);
a319f149 JCPV	181	p4_out(inw(SH7751_BCR3), SH7751_PCIBCR3);
28e5efde NI	182	p4_out(inl(SH7751_WCR1), SH7751_PCIWCR1);
	183	p4_out(inl(SH7751_WCR2), SH7751_PCIWCR2);
	184	p4_out(inl(SH7751_WCR3), SH7751_PCIWCR3);
	185	p4_out(inl(SH7751_MCR), SH7751_PCIMCR);
	186
	187	/* Finally, set central function init complete */
	188	p4_out((SH7751_PCICR_PREFIX \| SH7751_PCICR_CFIN), SH7751_PCICR);
	189
28e5efde NI	190	return 0;
28e5efde NI	191	}
72c2f4ac MV	192
	193	static const struct dm_pci_ops sh7751_pci_ops = {
	194	.read_config = sh7751_pci_read_config,
	195	.write_config = sh7751_pci_write_config,
	196	};
	197
	198	static const struct udevice_id sh7751_pci_ids[] = {
	199	{ .compatible = "renesas,pci-sh7751" },
	200	{ }
	201	};
	202
	203	U_BOOT_DRIVER(sh7751_pci) = {
	204	.name = "sh7751_pci",
	205	.id = UCLASS_PCI,
	206	.of_match = sh7751_pci_ids,
	207	.ops = &sh7751_pci_ops,
	208	.probe = sh7751_pci_probe,
	209	};