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83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
cba69eee IC |
2 | /* |
3 | * (C) Copyright 2012-2012 Henrik Nordstrom <[email protected]> | |
4 | * | |
5 | * (C) Copyright 2007-2011 | |
6 | * Allwinner Technology Co., Ltd. <www.allwinnertech.com> | |
7 | * Tom Cubie <[email protected]> | |
8 | * | |
9 | * Configuration settings for the Allwinner sunxi series of boards. | |
cba69eee IC |
10 | */ |
11 | ||
12 | #ifndef _SUNXI_COMMON_CONFIG_H | |
13 | #define _SUNXI_COMMON_CONFIG_H | |
14 | ||
daf6d399 | 15 | #include <asm/arch/cpu.h> |
e049fe28 HG |
16 | #include <linux/stringify.h> |
17 | ||
d29adf8e | 18 | #ifdef CONFIG_ARM64 |
e628f008 | 19 | #define CONFIG_SYS_BOOTM_LEN (32 << 20) |
d29adf8e AP |
20 | #endif |
21 | ||
cba69eee | 22 | /* Serial & console */ |
cba69eee IC |
23 | #define CONFIG_SYS_NS16550_SERIAL |
24 | /* ns16550 reg in the low bits of cpu reg */ | |
cba69eee | 25 | #define CONFIG_SYS_NS16550_CLK 24000000 |
4fb60552 | 26 | #ifndef CONFIG_DM_SERIAL |
1a81cf83 SG |
27 | # define CONFIG_SYS_NS16550_REG_SIZE -4 |
28 | # define CONFIG_SYS_NS16550_COM1 SUNXI_UART0_BASE | |
29 | # define CONFIG_SYS_NS16550_COM2 SUNXI_UART1_BASE | |
30 | # define CONFIG_SYS_NS16550_COM3 SUNXI_UART2_BASE | |
31 | # define CONFIG_SYS_NS16550_COM4 SUNXI_UART3_BASE | |
32 | # define CONFIG_SYS_NS16550_COM5 SUNXI_R_UART_BASE | |
33 | #endif | |
cba69eee | 34 | |
8a65f69c | 35 | /* CPU */ |
e4916e85 | 36 | #define COUNTER_FREQUENCY 24000000 |
8a65f69c | 37 | |
e049fe28 HG |
38 | /* |
39 | * The DRAM Base differs between some models. We cannot use macros for the | |
40 | * CONFIG_FOO defines which contain the DRAM base address since they end | |
41 | * up unexpanded in include/autoconf.mk . | |
42 | * | |
43 | * So we have to have this #ifdef #else #endif block for these. | |
44 | */ | |
45 | #ifdef CONFIG_MACH_SUN9I | |
46 | #define SDRAM_OFFSET(x) 0x2##x | |
47 | #define CONFIG_SYS_SDRAM_BASE 0x20000000 | |
17d6ecea | 48 | /* Note SPL_STACK_R_ADDR is set through Kconfig, we include it here |
ff42d107 HG |
49 | * since it needs to fit in with the other values. By also #defining it |
50 | * we get warnings if the Kconfig value mismatches. */ | |
e049fe28 HG |
51 | #define CONFIG_SPL_BSS_START_ADDR 0x2ff80000 |
52 | #else | |
53 | #define SDRAM_OFFSET(x) 0x4##x | |
cba69eee | 54 | #define CONFIG_SYS_SDRAM_BASE 0x40000000 |
c199489f | 55 | /* V3s do not have enough memory to place code at 0x4a000000 */ |
17d6ecea | 56 | /* Note SPL_STACK_R_ADDR is set through Kconfig, we include it here |
ff42d107 HG |
57 | * since it needs to fit in with the other values. By also #defining it |
58 | * we get warnings if the Kconfig value mismatches. */ | |
e049fe28 HG |
59 | #define CONFIG_SPL_BSS_START_ADDR 0x4ff80000 |
60 | #endif | |
61 | ||
62 | #define CONFIG_SPL_BSS_MAX_SIZE 0x00080000 /* 512 KiB */ | |
e049fe28 | 63 | |
77fe9887 HG |
64 | /* |
65 | * The A80's A1 sram starts at 0x00010000 rather then at 0x00000000 and is | |
66 | * slightly bigger. Note that it is possible to map the first 32 KiB of the | |
67 | * A1 at 0x00000000 like with older SoCs by writing 0x16aa0001 to the | |
68 | * undocumented 0x008000e0 SYS_CTRL register. Where the 16aa is a key and | |
69 | * the 1 actually activates the mapping of the first 32 KiB to 0x00000000. | |
cadc7c20 IZ |
70 | * A64 and H5 also has SRAM A1 at 0x00010000, but no magic remap register |
71 | * is known yet. | |
72 | * H6 has SRAM A1 at 0x00020000. | |
77fe9887 | 73 | */ |
cadc7c20 IZ |
74 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SUNXI_SRAM_ADDRESS |
75 | /* FIXME: this may be larger on some SoCs */ | |
76 | #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */ | |
cba69eee IC |
77 | |
78 | #define CONFIG_SYS_INIT_SP_OFFSET \ | |
79 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
80 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
81 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) | |
82 | ||
cba69eee IC |
83 | #define PHYS_SDRAM_0 CONFIG_SYS_SDRAM_BASE |
84 | #define PHYS_SDRAM_0_SIZE 0x80000000 /* 2 GiB */ | |
85 | ||
a6e50a88 | 86 | #ifdef CONFIG_AHCI |
0751b138 | 87 | #define CONFIG_SYS_64BIT_LBA |
a6e50a88 IC |
88 | #endif |
89 | ||
e5268616 | 90 | #ifdef CONFIG_NAND_SUNXI |
a0dfa88b | 91 | #define CONFIG_SYS_NAND_MAX_ECCPOS 1664 |
4ccae81c | 92 | #define CONFIG_SYS_MAX_NAND_DEVICE 8 |
960caeba PZ |
93 | #endif |
94 | ||
e24ea55c | 95 | /* mmc config */ |
44c79879 | 96 | #ifdef CONFIG_MMC |
e24ea55c | 97 | #define CONFIG_MMC_SUNXI_SLOT 0 |
fb1c43cc MR |
98 | #endif |
99 | ||
100 | #if defined(CONFIG_ENV_IS_IN_MMC) | |
99219664 MR |
101 | |
102 | #ifdef CONFIG_ARM64 | |
103 | /* | |
104 | * This is actually (CONFIG_ENV_OFFSET - | |
105 | * (CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)), but the value will be used | |
106 | * directly in a makefile, without the preprocessor expansion. | |
107 | */ | |
108 | #define CONFIG_BOARD_SIZE_LIMIT 0x7e000 | |
109 | #endif | |
110 | ||
ae042beb | 111 | #define CONFIG_SYS_MMC_MAX_DEVICE 4 |
ff2b47f6 | 112 | #endif |
e24ea55c | 113 | |
cba69eee IC |
114 | /* |
115 | * Miscellaneous configurable options | |
116 | */ | |
06beadb0 IC |
117 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
118 | #define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */ | |
cba69eee | 119 | |
cba69eee | 120 | /* standalone support */ |
e049fe28 | 121 | #define CONFIG_STANDALONE_LOAD_ADDR CONFIG_SYS_LOAD_ADDR |
cba69eee | 122 | |
cba69eee IC |
123 | /* FLASH and environment organization */ |
124 | ||
fa5e1020 | 125 | #define CONFIG_SYS_MONITOR_LEN (768 << 10) /* 768 KiB */ |
cba69eee | 126 | |
942cb0b6 SG |
127 | #define CONFIG_SPL_BOARD_LOAD_IMAGE |
128 | ||
cadc7c20 IZ |
129 | /* |
130 | * We cannot use expressions here, because expressions won't be evaluated in | |
131 | * autoconf.mk. | |
132 | */ | |
133 | #if CONFIG_SUNXI_SRAM_ADDRESS == 0x10000 | |
7f0ef5a9 | 134 | #define CONFIG_SPL_MAX_SIZE 0x7fa0 /* 32 KiB */ |
54522c92 AP |
135 | #ifdef CONFIG_ARM64 |
136 | /* end of SRAM A2 for now, as SRAM A1 is pretty tight for an ARM64 build */ | |
137 | #define LOW_LEVEL_SRAM_STACK 0x00054000 | |
138 | #else | |
bc613d85 | 139 | #define LOW_LEVEL_SRAM_STACK 0x00018000 |
54522c92 | 140 | #endif /* !CONFIG_ARM64 */ |
e5715e71 | 141 | #elif CONFIG_SUNXI_SRAM_ADDRESS == 0x20000 |
8ec293e0 JS |
142 | #ifdef CONFIG_MACH_SUN50I_H616 |
143 | #define CONFIG_SPL_MAX_SIZE 0xbfa0 /* 48 KiB */ | |
144 | #define LOW_LEVEL_SRAM_STACK 0x58000 | |
145 | #else | |
e5715e71 IZ |
146 | #define CONFIG_SPL_MAX_SIZE 0x7fa0 /* 32 KiB */ |
147 | /* end of SRAM A2 on H6 for now */ | |
148 | #define LOW_LEVEL_SRAM_STACK 0x00118000 | |
8ec293e0 | 149 | #endif |
d96ebc46 | 150 | #else |
7f0ef5a9 | 151 | #define CONFIG_SPL_MAX_SIZE 0x5fa0 /* 24KB on sun4i/sun7i */ |
bc613d85 | 152 | #define LOW_LEVEL_SRAM_STACK 0x00008000 /* End of sram */ |
d96ebc46 | 153 | #endif |
50827a59 | 154 | |
bc613d85 AP |
155 | #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK |
156 | ||
8ec293e0 | 157 | #ifndef CONFIG_MACH_SUN50I_H616 |
50827a59 | 158 | #define CONFIG_SPL_PAD_TO 32768 /* decimal for 'dd' */ |
8ec293e0 | 159 | #endif |
50827a59 | 160 | |
c26fb9db | 161 | /* Ethernet support */ |
c26fb9db | 162 | |
2582ca0d | 163 | #ifdef CONFIG_USB_EHCI_HCD |
6a72e804 | 164 | #define CONFIG_USB_OHCI_NEW |
6a72e804 | 165 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 |
1a800f7a HG |
166 | #endif |
167 | ||
cba69eee | 168 | #ifndef CONFIG_SPL_BUILD |
2ec3a612 | 169 | |
671f9ad8 AP |
170 | #ifdef CONFIG_ARM64 |
171 | /* | |
172 | * Boards seem to come with at least 512MB of DRAM. | |
173 | * The kernel should go at 512K, which is the default text offset (that will | |
174 | * be adjusted at runtime if needed). | |
175 | * There is no compression for arm64 kernels (yet), so leave some space | |
176 | * for really big kernels, say 256MB for now. | |
177 | * Scripts, PXE and DTBs should go afterwards, leaving the rest for the initrd. | |
671f9ad8 | 178 | */ |
17d6ecea JS |
179 | #define BOOTM_SIZE __stringify(0xa000000) |
180 | #define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(0080000)) | |
747c2421 AF |
181 | #define KERNEL_COMP_ADDR_R __stringify(SDRAM_OFFSET(4000000)) |
182 | #define KERNEL_COMP_SIZE __stringify(0xb000000) | |
17d6ecea JS |
183 | #define FDT_ADDR_R __stringify(SDRAM_OFFSET(FA00000)) |
184 | #define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(FC00000)) | |
185 | #define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(FD00000)) | |
186 | #define FDTOVERLAY_ADDR_R __stringify(SDRAM_OFFSET(FE00000)) | |
187 | #define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(FF00000)) | |
671f9ad8 AP |
188 | |
189 | #else | |
8c95c556 | 190 | /* |
5c965ed9 | 191 | * 160M RAM (256M minimum minus 64MB heap + 32MB for u-boot, stack, fb, etc. |
8c95c556 | 192 | * 32M uncompressed kernel, 16M compressed kernel, 1M fdt, |
17d6ecea | 193 | * 1M script, 1M pxe, 1M dt overlay and the ramdisk at the end. |
8c95c556 | 194 | */ |
c199489f | 195 | #ifndef CONFIG_MACH_SUN8I_V3S |
17d6ecea JS |
196 | #define BOOTM_SIZE __stringify(0xa000000) |
197 | #define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(2000000)) | |
198 | #define FDT_ADDR_R __stringify(SDRAM_OFFSET(3000000)) | |
199 | #define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(3100000)) | |
200 | #define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(3200000)) | |
201 | #define FDTOVERLAY_ADDR_R __stringify(SDRAM_OFFSET(3300000)) | |
202 | #define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(3400000)) | |
c199489f IZ |
203 | #else |
204 | /* | |
205 | * 64M RAM minus 2MB heap + 16MB for u-boot, stack, fb, etc. | |
206 | * 16M uncompressed kernel, 8M compressed kernel, 1M fdt, | |
17d6ecea | 207 | * 1M script, 1M pxe, 1M dt overlay and the ramdisk at the end. |
c199489f | 208 | */ |
17d6ecea JS |
209 | #define BOOTM_SIZE __stringify(0x2e00000) |
210 | #define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(1000000)) | |
211 | #define FDT_ADDR_R __stringify(SDRAM_OFFSET(1800000)) | |
212 | #define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(1900000)) | |
213 | #define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(1A00000)) | |
214 | #define FDTOVERLAY_ADDR_R __stringify(SDRAM_OFFSET(1B00000)) | |
215 | #define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(1C00000)) | |
c199489f | 216 | #endif |
671f9ad8 | 217 | #endif |
2a909c5f | 218 | |
846e3254 | 219 | #define MEM_LAYOUT_ENV_SETTINGS \ |
c199489f | 220 | "bootm_size=" BOOTM_SIZE "\0" \ |
2a909c5f SS |
221 | "kernel_addr_r=" KERNEL_ADDR_R "\0" \ |
222 | "fdt_addr_r=" FDT_ADDR_R "\0" \ | |
223 | "scriptaddr=" SCRIPT_ADDR_R "\0" \ | |
224 | "pxefile_addr_r=" PXEFILE_ADDR_R "\0" \ | |
17d6ecea | 225 | "fdtoverlay_addr_r=" FDTOVERLAY_ADDR_R "\0" \ |
2a909c5f SS |
226 | "ramdisk_addr_r=" RAMDISK_ADDR_R "\0" |
227 | ||
747c2421 AF |
228 | #ifdef CONFIG_ARM64 |
229 | ||
230 | #define MEM_LAYOUT_ENV_EXTRA_SETTINGS \ | |
231 | "kernel_comp_addr_r=" KERNEL_COMP_ADDR_R "\0" \ | |
232 | "kernel_comp_size=" KERNEL_COMP_SIZE "\0" | |
233 | ||
234 | #else | |
235 | ||
236 | #define MEM_LAYOUT_ENV_EXTRA_SETTINGS "" | |
237 | ||
238 | #endif | |
239 | ||
2a909c5f SS |
240 | #define DFU_ALT_INFO_RAM \ |
241 | "dfu_alt_info_ram=" \ | |
242 | "kernel ram " KERNEL_ADDR_R " 0x1000000;" \ | |
243 | "fdt ram " FDT_ADDR_R " 0x100000;" \ | |
244 | "ramdisk ram " RAMDISK_ADDR_R " 0x4000000\0" | |
846e3254 | 245 | |
41f8e9f5 | 246 | #ifdef CONFIG_MMC |
5a37a400 | 247 | #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1 |
de86fc38 MR |
248 | #define BOOTENV_DEV_MMC_AUTO(devtypeu, devtypel, instance) \ |
249 | BOOTENV_DEV_MMC(MMC, mmc, 0) \ | |
250 | BOOTENV_DEV_MMC(MMC, mmc, 1) \ | |
251 | "bootcmd_mmc_auto=" \ | |
252 | "if test ${mmc_bootdev} -eq 1; then " \ | |
253 | "run bootcmd_mmc1; " \ | |
254 | "run bootcmd_mmc0; " \ | |
255 | "elif test ${mmc_bootdev} -eq 0; then " \ | |
256 | "run bootcmd_mmc0; " \ | |
257 | "run bootcmd_mmc1; " \ | |
258 | "fi\0" | |
259 | ||
260 | #define BOOTENV_DEV_NAME_MMC_AUTO(devtypeu, devtypel, instance) \ | |
261 | "mmc_auto " | |
262 | ||
263 | #define BOOT_TARGET_DEVICES_MMC(func) func(MMC_AUTO, mmc_auto, na) | |
5a37a400 | 264 | #else |
de86fc38 | 265 | #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) |
5a37a400 | 266 | #endif |
41f8e9f5 CYT |
267 | #else |
268 | #define BOOT_TARGET_DEVICES_MMC(func) | |
269 | #endif | |
270 | ||
2ec3a612 HG |
271 | #ifdef CONFIG_AHCI |
272 | #define BOOT_TARGET_DEVICES_SCSI(func) func(SCSI, scsi, 0) | |
273 | #else | |
274 | #define BOOT_TARGET_DEVICES_SCSI(func) | |
275 | #endif | |
276 | ||
2582ca0d | 277 | #ifdef CONFIG_USB_STORAGE |
859b3f14 CYT |
278 | #define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0) |
279 | #else | |
280 | #define BOOT_TARGET_DEVICES_USB(func) | |
281 | #endif | |
282 | ||
0eabec14 OJ |
283 | #ifdef CONFIG_CMD_PXE |
284 | #define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na) | |
285 | #else | |
286 | #define BOOT_TARGET_DEVICES_PXE(func) | |
287 | #endif | |
288 | ||
289 | #ifdef CONFIG_CMD_DHCP | |
290 | #define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na) | |
291 | #else | |
292 | #define BOOT_TARGET_DEVICES_DHCP(func) | |
293 | #endif | |
294 | ||
f3b589c0 BN |
295 | /* FEL boot support, auto-execute boot.scr if a script address was provided */ |
296 | #define BOOTENV_DEV_FEL(devtypeu, devtypel, instance) \ | |
297 | "bootcmd_fel=" \ | |
298 | "if test -n ${fel_booted} && test -n ${fel_scriptaddr}; then " \ | |
299 | "echo '(FEL boot)'; " \ | |
300 | "source ${fel_scriptaddr}; " \ | |
301 | "fi\0" | |
302 | #define BOOTENV_DEV_NAME_FEL(devtypeu, devtypel, instance) \ | |
303 | "fel " | |
304 | ||
2ec3a612 | 305 | #define BOOT_TARGET_DEVICES(func) \ |
f3b589c0 | 306 | func(FEL, fel, na) \ |
41f8e9f5 | 307 | BOOT_TARGET_DEVICES_MMC(func) \ |
2ec3a612 | 308 | BOOT_TARGET_DEVICES_SCSI(func) \ |
859b3f14 | 309 | BOOT_TARGET_DEVICES_USB(func) \ |
0eabec14 OJ |
310 | BOOT_TARGET_DEVICES_PXE(func) \ |
311 | BOOT_TARGET_DEVICES_DHCP(func) | |
2ec3a612 | 312 | |
3b824025 HG |
313 | #ifdef CONFIG_OLD_SUNXI_KERNEL_COMPAT |
314 | #define BOOTCMD_SUNXI_COMPAT \ | |
315 | "bootcmd_sunxi_compat=" \ | |
316 | "setenv root /dev/mmcblk0p3 rootwait; " \ | |
317 | "if ext2load mmc 0 0x44000000 uEnv.txt; then " \ | |
318 | "echo Loaded environment from uEnv.txt; " \ | |
319 | "env import -t 0x44000000 ${filesize}; " \ | |
320 | "fi; " \ | |
321 | "setenv bootargs console=${console} root=${root} ${extraargs}; " \ | |
322 | "ext2load mmc 0 0x43000000 script.bin && " \ | |
323 | "ext2load mmc 0 0x48000000 uImage && " \ | |
324 | "bootm 0x48000000\0" | |
325 | #else | |
326 | #define BOOTCMD_SUNXI_COMPAT | |
327 | #endif | |
328 | ||
2ec3a612 HG |
329 | #include <config_distro_bootcmd.h> |
330 | ||
86b49093 HG |
331 | #ifdef CONFIG_USB_KEYBOARD |
332 | #define CONSOLE_STDIN_SETTINGS \ | |
86b49093 HG |
333 | "stdin=serial,usbkbd\0" |
334 | #else | |
7f2c521f LV |
335 | #define CONSOLE_STDIN_SETTINGS \ |
336 | "stdin=serial\0" | |
86b49093 | 337 | #endif |
7f2c521f | 338 | |
5d235324 | 339 | #ifdef CONFIG_DM_VIDEO |
56009451 JS |
340 | #define CONSOLE_STDOUT_SETTINGS \ |
341 | "stdout=serial,vidconsole\0" \ | |
342 | "stderr=serial,vidconsole\0" | |
7f2c521f LV |
343 | #else |
344 | #define CONSOLE_STDOUT_SETTINGS \ | |
345 | "stdout=serial\0" \ | |
346 | "stderr=serial\0" | |
347 | #endif | |
348 | ||
c8564b24 MR |
349 | #ifdef CONFIG_MTDIDS_DEFAULT |
350 | #define SUNXI_MTDIDS_DEFAULT \ | |
351 | "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" | |
352 | #else | |
353 | #define SUNXI_MTDIDS_DEFAULT | |
354 | #endif | |
355 | ||
356 | #ifdef CONFIG_MTDPARTS_DEFAULT | |
357 | #define SUNXI_MTDPARTS_DEFAULT \ | |
358 | "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" | |
359 | #else | |
360 | #define SUNXI_MTDPARTS_DEFAULT | |
361 | #endif | |
362 | ||
c53654fc MR |
363 | #define PARTS_DEFAULT \ |
364 | "name=loader1,start=8k,size=32k,uuid=${uuid_gpt_loader1};" \ | |
365 | "name=loader2,size=984k,uuid=${uuid_gpt_loader2};" \ | |
366 | "name=esp,size=128M,bootable,uuid=${uuid_gpt_esp};" \ | |
367 | "name=system,size=-,uuid=${uuid_gpt_system};" | |
368 | ||
369 | #define UUID_GPT_ESP "c12a7328-f81f-11d2-ba4b-00a0c93ec93b" | |
370 | ||
371 | #ifdef CONFIG_ARM64 | |
372 | #define UUID_GPT_SYSTEM "b921b045-1df0-41c3-af44-4c6f280d3fae" | |
373 | #else | |
374 | #define UUID_GPT_SYSTEM "69dad710-2ce4-4e3c-b16c-21a1d49abed3" | |
375 | #endif | |
376 | ||
7f2c521f LV |
377 | #define CONSOLE_ENV_SETTINGS \ |
378 | CONSOLE_STDIN_SETTINGS \ | |
379 | CONSOLE_STDOUT_SETTINGS | |
380 | ||
2eff3b71 AF |
381 | #ifdef CONFIG_ARM64 |
382 | #define FDTFILE "allwinner/" CONFIG_DEFAULT_DEVICE_TREE ".dtb" | |
383 | #else | |
384 | #define FDTFILE CONFIG_DEFAULT_DEVICE_TREE ".dtb" | |
385 | #endif | |
386 | ||
2ec3a612 | 387 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
7f2c521f | 388 | CONSOLE_ENV_SETTINGS \ |
846e3254 | 389 | MEM_LAYOUT_ENV_SETTINGS \ |
747c2421 | 390 | MEM_LAYOUT_ENV_EXTRA_SETTINGS \ |
2a909c5f | 391 | DFU_ALT_INFO_RAM \ |
2eff3b71 | 392 | "fdtfile=" FDTFILE "\0" \ |
846e3254 | 393 | "console=ttyS0,115200\0" \ |
c8564b24 MR |
394 | SUNXI_MTDIDS_DEFAULT \ |
395 | SUNXI_MTDPARTS_DEFAULT \ | |
c53654fc MR |
396 | "uuid_gpt_esp=" UUID_GPT_ESP "\0" \ |
397 | "uuid_gpt_system=" UUID_GPT_SYSTEM "\0" \ | |
398 | "partitions=" PARTS_DEFAULT "\0" \ | |
3b824025 | 399 | BOOTCMD_SUNXI_COMPAT \ |
2ec3a612 HG |
400 | BOOTENV |
401 | ||
402 | #else /* ifndef CONFIG_SPL_BUILD */ | |
403 | #define CONFIG_EXTRA_ENV_SETTINGS | |
cba69eee IC |
404 | #endif |
405 | ||
406 | #endif /* _SUNXI_COMMON_CONFIG_H */ |