[J-u-boot.git] / include / configs / pico-imx8mq.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright 2018 NXP
 */

#ifndef __IMX8M_PICOPI_H
#define __IMX8M_PICOPI_H

#include <linux/sizes.h>
#include <asm/arch/imx-regs.h>

#define CONFIG_SPL_MAX_SIZE		(124 * 1024)
#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300

#ifdef CONFIG_SPL_BUILD
/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
#define CONFIG_SPL_STACK		0x187FF0
#define CONFIG_SPL_BSS_START_ADDR	0x00180000
#define CONFIG_SPL_BSS_MAX_SIZE		0x2000	/* 8 KB */
#define CONFIG_SYS_SPL_MALLOC_START	0x42200000
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x80000	/* 512 KB */
#define CONFIG_SYS_SPL_PTE_RAM_BASE	0x41580000

/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
#define CONFIG_MALLOC_F_ADDR		0x182000
/* For RAW image gives a error info not panic */
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE

#undef CONFIG_DM_MMC
#endif

#define CONFIG_REMAKE_ELF

/* ENET Config */
/* ENET1 */
#if defined(CONFIG_CMD_NET)
#define CONFIG_ETHPRIME			"FEC"

#define CONFIG_FEC_XCV_TYPE		RGMII
#define CONFIG_FEC_MXC_PHYADDR		1
#define FEC_QUIRK_ENET_MAC

#define IMX_FEC_BASE			0x30BE0000
#endif

/* Initial environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS					\
	"script=boot.scr\0"						\
	"image=Image\0"							\
	"console=ttymxc0,115200\0"					\
	"fdt_addr=0x43000000\0"						\
	"fdt_high=0xffffffffffffffff\0"					\
	"fdt_file=imx8mq-pico-pi.dtb\0"					\
	"initrd_addr=0x43800000\0"					\
	"initrd_high=0xffffffffffffffff\0"				\
	"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0"		\
	"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0"	\
	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0"			\
	"mmcautodetect=yes\0"						\
	"mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 "	\
	"loadbootscript="						\
		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
	"bootscript=echo Running bootscript from mmc ...; source\0"	\
	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
	"mmcboot=echo Booting from mmc ...; "				\
		"run mmcargs; "						\
		"echo wait for boot; "					\
		"fi;\0"							\
	"netargs=setenv bootargs console=${console} "			\
		"root=/dev/nfs "					\
		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"	\
	"netboot=echo Booting from net ...; "				\
		"run netargs;  "					\
		"if test ${ip_dyn} = yes; then "			\
			"setenv get_cmd dhcp; "				\
		"else "							\
			"setenv get_cmd tftp; "				\
		"fi; "							\
		"${get_cmd} ${loadaddr} ${image}; "			\
		"booti; "

#define CONFIG_BOOTCOMMAND \
	"mmc dev ${mmcdev}; if mmc rescan; then "			\
		"if run loadbootscript; then "				\
			"run bootscript; "				\
		"else "							\
			"if run loadimage; then "			\
				"run mmcboot; "				\
			"else run netboot; "				\
			"fi; "						\
		"fi; "							\
	"else booti ${loadaddr} - ${fdt_addr}; fi"

/* Link Definitions */

#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE	0x80000
#define CONFIG_SYS_INIT_SP_OFFSET	\
	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR		\
	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)

#define CONFIG_MMCROOT			"/dev/mmcblk1p2"	/* USDHC2 */

#define CONFIG_SYS_SDRAM_BASE		0x40000000
#define PHYS_SDRAM			0x40000000
#define PHYS_SDRAM_SIZE			0x80000000	/* 2 GiB DDR */

#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM
#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + \
					(PHYS_SDRAM_SIZE >> 1))

#define CONFIG_MXC_UART_BASE		UART1_BASE_ADDR

/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE		1024
#define CONFIG_SYS_MAXARGS		64
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
					sizeof(CONFIG_SYS_PROMPT) + 16)

#define CONFIG_SYS_FSL_USDHC_NUM	2
#define CONFIG_SYS_FSL_ESDHC_ADDR	0

#define CONFIG_SYS_MMC_IMG_LOAD_PART	1

#define CONFIG_MXC_GPIO

#define CONFIG_OF_SYSTEM_SETUP

#define CONFIG_SYS_BOOTM_LEN		SZ_128M

#endif
Commit	Line	Data
b52fb0b0 MV	1	/* SPDX-License-Identifier: GPL-2.0+ */
	2	/*
	3	* Copyright 2018 NXP
	4	*/
	5
	6	#ifndef __IMX8M_PICOPI_H
	7	#define __IMX8M_PICOPI_H
	8
	9	#include <linux/sizes.h>
	10	#include <asm/arch/imx-regs.h>
	11
	12	#define CONFIG_SPL_MAX_SIZE (124 * 1024)
	13	#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
	14	#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
	15	#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
b52fb0b0 MV	16
	17	#ifdef CONFIG_SPL_BUILD
	18	/#define CONFIG_ENABLE_DDR_TRAINING_DEBUG/
b52fb0b0	19	#define CONFIG_SPL_STACK 0x187FF0
b52fb0b0 MV	20	#define CONFIG_SPL_BSS_START_ADDR 0x00180000
	21	#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */
	22	#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
	23	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */
	24	#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000
	25
	26	/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
	27	#define CONFIG_MALLOC_F_ADDR 0x182000
	28	/* For RAW image gives a error info not panic */
	29	#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
	30
	31	#undef CONFIG_DM_MMC
b52fb0b0 MV	32	#endif
	33
	34	#define CONFIG_REMAKE_ELF
	35
b52fb0b0 MV	36	/* ENET Config */
	37	/* ENET1 */
	38	#if defined(CONFIG_CMD_NET)
b52fb0b0 MV	39	#define CONFIG_ETHPRIME "FEC"
b52fb0b0 MV	40
b52fb0b0 MV	41	#define CONFIG_FEC_XCV_TYPE RGMII
	42	#define CONFIG_FEC_MXC_PHYADDR 1
	43	#define FEC_QUIRK_ENET_MAC
	44
b52fb0b0	45	#define IMX_FEC_BASE 0x30BE0000
b52fb0b0 MV	46	#endif
	47
	48	/* Initial environment variables */
	49	#define CONFIG_EXTRA_ENV_SETTINGS \
	50	"script=boot.scr\0" \
	51	"image=Image\0" \
	52	"console=ttymxc0,115200\0" \
	53	"fdt_addr=0x43000000\0" \
	54	"fdt_high=0xffffffffffffffff\0" \
	55	"fdt_file=imx8mq-pico-pi.dtb\0" \
	56	"initrd_addr=0x43800000\0" \
	57	"initrd_high=0xffffffffffffffff\0" \
	58	"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
	59	"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
	60	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
	61	"mmcautodetect=yes\0" \
	62	"mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
	63	"loadbootscript=" \
	64	"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
	65	"bootscript=echo Running bootscript from mmc ...; source\0" \
	66	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
	67	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
	68	"mmcboot=echo Booting from mmc ...; " \
	69	"run mmcargs; " \
	70	"echo wait for boot; " \
	71	"fi;\0" \
	72	"netargs=setenv bootargs console=${console} " \
	73	"root=/dev/nfs " \
	74	"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
	75	"netboot=echo Booting from net ...; " \
	76	"run netargs; " \
	77	"if test ${ip_dyn} = yes; then " \
	78	"setenv get_cmd dhcp; " \
	79	"else " \
	80	"setenv get_cmd tftp; " \
	81	"fi; " \
	82	"${get_cmd} ${loadaddr} ${image}; " \
	83	"booti; "
	84
	85	#define CONFIG_BOOTCOMMAND \
	86	"mmc dev ${mmcdev}; if mmc rescan; then " \
	87	"if run loadbootscript; then " \
	88	"run bootscript; " \
	89	"else " \
	90	"if run loadimage; then " \
	91	"run mmcboot; " \
	92	"else run netboot; " \
	93	"fi; " \
	94	"fi; " \
	95	"else booti ${loadaddr} - ${fdt_addr}; fi"
	96
	97	/* Link Definitions */
b52fb0b0 MV	98
	99	#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
	100	#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
	101	#define CONFIG_SYS_INIT_SP_OFFSET \
	102	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
	103	#define CONFIG_SYS_INIT_SP_ADDR \
	104	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
	105
b52fb0b0 MV	106	#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
b52fb0b0 MV	107
b52fb0b0 MV	108	#define CONFIG_SYS_SDRAM_BASE 0x40000000
	109	#define PHYS_SDRAM 0x40000000
	110	#define PHYS_SDRAM_SIZE 0x80000000 /* 2 GiB DDR */
	111
	112	#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
	113	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
	114	(PHYS_SDRAM_SIZE >> 1))
	115
b52fb0b0 MV	116	#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR
	117
	118	/* Monitor Command Prompt */
	119	#define CONFIG_SYS_CBSIZE 1024
	120	#define CONFIG_SYS_MAXARGS 64
	121	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	122	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	123	sizeof(CONFIG_SYS_PROMPT) + 16)
	124
b52fb0b0 MV	125	#define CONFIG_SYS_FSL_USDHC_NUM 2
	126	#define CONFIG_SYS_FSL_ESDHC_ADDR 0
	127
	128	#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
	129
	130	#define CONFIG_MXC_GPIO
	131
b52fb0b0 MV	132	#define CONFIG_OF_SYSTEM_SETUP
b52fb0b0 MV	133
b52fb0b0 MV	134	#define CONFIG_SYS_BOOTM_LEN SZ_128M
	135
	136	#endif