[J-u-boot.git] / include / configs / kmcent2.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * (C) Copyright 2016 Keymile AG
 * Rainer Boschung <[email protected]>
 *
 */

#ifndef __KMCENT2_H
#define __KMCENT2_H

#define CONFIG_HOSTNAME		"kmcent2"
#define KM_BOARD_NAME	CONFIG_HOSTNAME

/*
 * The Linux fsl_fman driver needs to be able to process frames with more
 * than just the VLAN tag (i.e. eDSA tag). It is passed as a kernel boot
 * parameters
 */
#define CONFIG_KM_DEF_BOOT_ARGS_CPU	"fsl_dpaa_fman.fsl_fm_max_frm=1558"

#include "km/keymile-common.h"

/* Application IFC chip selects */
#define SYS_LAWAPP_BASE		0xc0000000
#define SYS_LAWAPP_BASE_PHYS	(0xf00000000ull | SYS_LAWAPP_BASE)

/* Application IFC CS4 MRAM */
#define CONFIG_SYS_MRAM_BASE		SYS_LAWAPP_BASE
#define SYS_MRAM_BASE_PHYS	SYS_LAWAPP_BASE_PHYS
#define SYS_MRAM_CSPR_EXT	(0x0f)
#define SYS_MRAM_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_MRAM_BASE) | \
				CSPR_PORT_SIZE_8 | /* 8 bit */		\
				CSPR_MSEL_GPCM   | /* msel = gpcm */	\
				CSPR_V /* bank is valid */)
#define SYS_MRAM_AMASK		IFC_AMASK(2 * 1024 * 1024) /* 2 MiB */
#define SYS_MRAM_CSOR		CSOR_GPCM_TRHZ_40
/* MRAM Timing parameters for IFC CS4 */
#define SYS_MRAM_FTIM0	(FTIM0_GPCM_TACSE(0x6) | \
			FTIM0_GPCM_TEADC(0x8)  | \
			FTIM0_GPCM_TEAHC(0x2))
#define SYS_MRAM_FTIM1	(FTIM1_GPCM_TACO(0x2) | \
			FTIM1_GPCM_TRAD(0xe))
#define SYS_MRAM_FTIM2	(FTIM2_GPCM_TCS(0x2) | \
			FTIM2_GPCM_TCH(0x2)  | \
			FTIM2_GPCM_TWP(0x8))
#define SYS_MRAM_FTIM3	0x04000000
#define CONFIG_SYS_CSPR4_EXT	SYS_MRAM_CSPR_EXT
#define CONFIG_SYS_CSPR4	SYS_MRAM_CSPR
#define CONFIG_SYS_AMASK4	SYS_MRAM_AMASK
#define CONFIG_SYS_CSOR4	SYS_MRAM_CSOR
#define CONFIG_SYS_CS4_FTIM0	SYS_MRAM_FTIM0
#define CONFIG_SYS_CS4_FTIM1	SYS_MRAM_FTIM1
#define CONFIG_SYS_CS4_FTIM2	SYS_MRAM_FTIM2
#define CONFIG_SYS_CS4_FTIM3	SYS_MRAM_FTIM3

/* Application IFC CS6: BFTIC */
#define SYS_BFTIC_BASE		0xd0000000
#define SYS_BFTIC_BASE_PHYS	(0xf00000000ull | SYS_BFTIC_BASE)
#define SYS_BFTIC_CSPR_EXT	(0x0f)
#define SYS_BFTIC_CSPR	(CSPR_PHYS_ADDR(SYS_BFTIC_BASE) | \
				CSPR_PORT_SIZE_8 | /* Port size = 8 bit */\
				CSPR_MSEL_GPCM |   /* MSEL = GPCM */\
				CSPR_V)            /* valid */
#define SYS_BFTIC_AMASK IFC_AMASK(64 * 1024)  /* 64kB */
#define SYS_BFTIC_CSOR  CSOR_GPCM_TRHZ_40
/* BFTIC Timing parameters for IFC CS6 */
#define SYS_BFTIC_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \
				FTIM0_GPCM_TEADC(0x8) | \
				FTIM0_GPCM_TEAHC(0x2))
#define SYS_BFTIC_FTIM1 (FTIM1_GPCM_TACO(0x2) | \
				FTIM1_GPCM_TRAD(0x12))
#define SYS_BFTIC_FTIM2 (FTIM2_GPCM_TCS(0x3) | \
				FTIM2_GPCM_TCH(0x1) | \
				FTIM2_GPCM_TWP(0x12))
#define SYS_BFTIC_FTIM3	0x04000000
#define CONFIG_SYS_CSPR6_EXT	SYS_BFTIC_CSPR_EXT
#define CONFIG_SYS_CSPR6	SYS_BFTIC_CSPR
#define CONFIG_SYS_AMASK6	SYS_BFTIC_AMASK
#define CONFIG_SYS_CSOR6	SYS_BFTIC_CSOR
#define CONFIG_SYS_CS6_FTIM0	SYS_BFTIC_FTIM0
#define CONFIG_SYS_CS6_FTIM1	SYS_BFTIC_FTIM1
#define CONFIG_SYS_CS6_FTIM2	SYS_BFTIC_FTIM2
#define CONFIG_SYS_CS6_FTIM3	SYS_BFTIC_FTIM3

/* Application IFC CS7 PAXE */
#define CONFIG_SYS_PAXE_BASE		0xd8000000
#define SYS_PAXE_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_PAXE_BASE)
#define SYS_PAXE_CSPR_EXT	(0x0f)
#define SYS_PAXE_CSPR  (CSPR_PHYS_ADDR(CONFIG_SYS_PAXE_BASE) | \
				CSPR_PORT_SIZE_8 | /* Port size = 8 bit */\
				CSPR_MSEL_GPCM |   /* MSEL = GPCM */\
				CSPR_V)            /* valid */
#define SYS_PAXE_AMASK IFC_AMASK(64 * 1024)  /* 64kB */
#define SYS_PAXE_CSOR  CSOR_GPCM_TRHZ_40
/* PAXE Timing parameters for IFC CS7 */
#define SYS_PAXE_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \
			FTIM0_GPCM_TEADC(0x8) | \
			FTIM0_GPCM_TEAHC(0x2))
#define SYS_PAXE_FTIM1 (FTIM1_GPCM_TACO(0x2) | \
			FTIM1_GPCM_TRAD(0x12))
#define SYS_PAXE_FTIM2 (FTIM2_GPCM_TCS(0x3) | \
			FTIM2_GPCM_TCH(0x1) | \
			FTIM2_GPCM_TWP(0x12))
#define SYS_PAXE_FTIM3	0x04000000
#define CONFIG_SYS_CSPR7_EXT	SYS_PAXE_CSPR_EXT
#define CONFIG_SYS_CSPR7	SYS_PAXE_CSPR
#define CONFIG_SYS_AMASK7	SYS_PAXE_AMASK
#define CONFIG_SYS_CSOR7	SYS_PAXE_CSOR
#define CONFIG_SYS_CS7_FTIM0	SYS_PAXE_FTIM0
#define CONFIG_SYS_CS7_FTIM1	SYS_PAXE_FTIM1
#define CONFIG_SYS_CS7_FTIM2	SYS_PAXE_FTIM2
#define CONFIG_SYS_CS7_FTIM3	SYS_PAXE_FTIM3

/* PRST */
#define KM_BFTIC4_RST		0
#define KM_DPAXE_RST		1
#define KM_FEMT_RST		3
#define KM_FOAM_RST		4
#define KM_EFE_RST		5
#define KM_ES_PHY_RST		6
#define KM_XES_PHY_RST		7
#define KM_ZL30158_RST		8
#define KM_ZL30364_RST		9
#define KM_BOBCAT_RST		10
#define KM_ETHSW_DDR_RST		12
#define KM_CFE_RST		13
#define KM_PEXSW_RST		14
#define KM_PEXSW_NT_RST		15

/* QRIO GPIOs used for deblocking */
#define KM_I2C_DEBLOCK_PORT	QRIO_GPIO_A
#define KM_I2C_DEBLOCK_SCL	20
#define KM_I2C_DEBLOCK_SDA	21

/* High Level Configuration Options */
#define CONFIG_SYS_BOOK3E_HV		/* Category E.HV supported */
#define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */

#define CONFIG_RESET_VECTOR_ADDRESS	0xebfffffc

#define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_PCIE1			/* PCIE controller 1 */

/* Environment in parallel NOR-Flash */
#define CONFIG_ENV_TOTAL_SIZE		0x040000
#define ENV_DEL_ADDR		0xebf00000	/*direct for newenv*/

/*
 * These can be toggled for performance analysis, otherwise use default.
 */
#define CONFIG_SYS_CACHE_STASHING
#define CONFIG_SYS_INIT_L2CSR0		L2CSR0_L2E

#define CONFIG_ENABLE_36BIT_PHYS

/* POST memory regions test */
#define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS

/*
 *  Config the L3 Cache as L3 SRAM
 */
#define CONFIG_SYS_INIT_L3_ADDR		0xFFFC0000
#define CONFIG_SYS_L3_SIZE		256 << 10

#define CONFIG_SYS_DCSRBAR		0xf0000000
#define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull

/*
 * DDR Setup
 */
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE

#define CONFIG_DIMM_SLOTS_PER_CTLR	1

#define CONFIG_SYS_SPD_BUS_NUM	0
#define SPD_EEPROM_ADDRESS	0x54
#define CONFIG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */

/******************************************************************************
 * (PRAM usage)
 * ... -------------------------------------------------------
 * ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM
 * ... |<------------------- pram -------------------------->|
 * ... -------------------------------------------------------
 * @END_OF_RAM:
 * @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose
 * @CONFIG_KM_PHRAM: address for /var
 * @CONFIG_KM_PNVRAM: address for PNVRAM (for the application)
 * @CONFIG_KM_ROOTFSSIZE: address for rootfilesystem in RAM
 */

/* size of rootfs in RAM */
#define CONFIG_KM_ROOTFSSIZE	0x0
/* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable
 * is not valid yet, which is the case for when u-boot copies itself to RAM
 */
#define CONFIG_PRAM		((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM) >> 10)

/*
 * IFC Definitions
 */
/* NOR flash on IFC CS0 */
#define CONFIG_SYS_FLASH_BASE		0xe8000000
#define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | \
					CONFIG_SYS_FLASH_BASE)

#define CONFIG_SYS_NOR_CSPR_EXT	(0x0f)
#define CONFIG_SYS_NOR_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
				CSPR_PORT_SIZE_16 | /* Port size = 16 bit */\
				0x00000010 |	    /* drive TE high */\
				CSPR_MSEL_NOR |	    /* MSEL = NOR */\
				CSPR_V)		    /* valid */
#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(64 * 1024 * 1024) /* 64MB */
#define CONFIG_SYS_NOR_CSOR	(CSOR_NOR_AVD_TGL_PGM_EN | /* AVD toggle */\
				CSOR_NOR_TRHZ_20 | \
				CSOR_NOR_BCTLD)

/* NOR Flash Timing Params */
#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x1) | \
				FTIM0_NOR_TEADC(0x7) | \
				FTIM0_NOR_TEAHC(0x1))
#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x1) | \
				FTIM1_NOR_TRAD_NOR(0x21) | \
				FTIM1_NOR_TSEQRAD_NOR(0x21))
#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCH(0x1) | \
				FTIM2_NOR_TCS(0x1) | \
				FTIM2_NOR_TWP(0xb) | \
				FTIM2_NOR_TWPH(0x6))
#define CONFIG_SYS_NOR_FTIM3	0x0

#define CONFIG_SYS_CSPR0_EXT	CONFIG_SYS_NOR_CSPR_EXT
#define CONFIG_SYS_CSPR0	CONFIG_SYS_NOR_CSPR
#define CONFIG_SYS_AMASK0	CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR0	CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS0_FTIM0	CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS0_FTIM1	CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2	CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3	CONFIG_SYS_NOR_FTIM3

/* More NOR Flash params */
#define CONFIG_SYS_FLASH_QUIET_TEST

#define CONFIG_SYS_MAX_FLASH_SECT	512	/* sectors per device */

#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS}

/* NAND Flash on IFC CS1*/
#define CONFIG_SYS_NAND_BASE		0xfa000000
#define CONFIG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_NAND_BASE)

#define CONFIG_SYS_NAND_CSPR_EXT	(0x0f)
#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE) | \
				CSPR_PORT_SIZE_8 | /* Port Size = 8 bit */\
				0x00000010 |	   /* drive TE high */\
				CSPR_MSEL_NAND |   /* MSEL = NAND */\
				CSPR_V)		   /* valid */
#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024) /* 64kB */

#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN | /* ECC encoder on */ \
				CSOR_NAND_ECC_DEC_EN | /* ECC decoder on */   \
				CSOR_NAND_ECC_MODE_4 | /* 4-bit ECC */        \
				CSOR_NAND_RAL_3      | /* RAL = 3Bytes */     \
				CSOR_NAND_PGS_2K     | /* Page size = 2K */   \
				CSOR_NAND_SPRZ_128   | /* Spare size = 128 */ \
				CSOR_NAND_PB(64)     | /* 64 Pages/Block */   \
				CSOR_NAND_TRHZ_40    | /**/                   \
				CSOR_NAND_BCTLD)       /**/

/* ONFI NAND Flash mode0 Timing Params */
#define CONFIG_SYS_NAND_FTIM0	(FTIM0_NAND_TCCST(0x3) | \
				FTIM0_NAND_TWP(0x8) | \
				FTIM0_NAND_TWCHT(0x3) | \
				FTIM0_NAND_TWH(0x5))
#define CONFIG_SYS_NAND_FTIM1	(FTIM1_NAND_TADLE(0x1e) | \
				FTIM1_NAND_TWBE(0x1e) | \
				FTIM1_NAND_TRR(0x6) | \
				FTIM1_NAND_TRP(0x8))
#define CONFIG_SYS_NAND_FTIM2	(FTIM2_NAND_TRAD(0x9) | \
				FTIM2_NAND_TREH(0x5) | \
				FTIM2_NAND_TWHRE(0x3c))
#define CONFIG_SYS_NAND_FTIM3	(FTIM3_NAND_TWW(0x1e))

#define CONFIG_SYS_CSPR1_EXT	CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR1	CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK1	CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR1	CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS1_FTIM0	CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS1_FTIM1	CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS1_FTIM2	CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS1_FTIM3	CONFIG_SYS_NAND_FTIM3

/* More NAND Flash Params */
#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE	1

/* QRIO on IFC CS2 */
#define CONFIG_SYS_QRIO_BASE		0xfb000000
#define CONFIG_SYS_QRIO_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_QRIO_BASE)
#define SYS_QRIO_CSPR_EXT	(0x0f)
#define SYS_QRIO_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE) | \
				CSPR_PORT_SIZE_8 | /* Port size = 8 bit */\
				0x00000010 |	   /* drive TE high */\
				CSPR_MSEL_GPCM |   /* MSEL = GPCM */\
				CSPR_V)           /* valid */
#define SYS_QRIO_AMASK	IFC_AMASK(64 * 1024)  /* 64kB */
#define SYS_QRIO_CSOR	(CSOR_GPCM_TRHZ_20 |\
			CSOR_GPCM_BCTLD)
/* QRIO Timing parameters for IFC CS2 */
#define SYS_QRIO_FTIM0	(FTIM0_GPCM_TACSE(0x2) | \
			FTIM0_GPCM_TEADC(0x8) | \
			FTIM0_GPCM_TEAHC(0x2))
#define SYS_QRIO_FTIM1	(FTIM1_GPCM_TACO(0x2) | \
			FTIM1_GPCM_TRAD(0x6))
#define SYS_QRIO_FTIM2	(FTIM2_GPCM_TCS(0x1) | \
			FTIM2_GPCM_TCH(0x1) | \
			FTIM2_GPCM_TWP(0x7))
#define SYS_QRIO_FTIM3	0x04000000
#define CONFIG_SYS_CSPR2_EXT	SYS_QRIO_CSPR_EXT
#define CONFIG_SYS_CSPR2	SYS_QRIO_CSPR
#define CONFIG_SYS_AMASK2	SYS_QRIO_AMASK
#define CONFIG_SYS_CSOR2	SYS_QRIO_CSOR
#define CONFIG_SYS_CS2_FTIM0	SYS_QRIO_FTIM0
#define CONFIG_SYS_CS2_FTIM1	SYS_QRIO_FTIM1
#define CONFIG_SYS_CS2_FTIM2	SYS_QRIO_FTIM2
#define CONFIG_SYS_CS2_FTIM3	SYS_QRIO_FTIM3

#define CONFIG_HWCONFIG

/* define to use L1 as initial stack */
#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address */
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe03c000
/* The assembler doesn't like typecast */
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
#define CONFIG_SYS_INIT_RAM_SIZE		0x00004000

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
					GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
#define CONFIG_SYS_MONITOR_LEN		0xc0000         /* 768k */

/*
 * Serial Port - controlled on board with jumper J8
 * open - index 2
 * shorted - index 1
 * Retain non-DM serial port for debug purposes.
 */
#if !defined(CONFIG_DM_SERIAL)
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0) / 2)
#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR + 0x11C500)
#endif

#ifndef __ASSEMBLY__
void set_sda(int state);
void set_scl(int state);
int get_sda(void);
int get_scl(void);
#endif

/*
 * General PCI
 * Memory space is mapped 1-1, but I/O space must start from 0.
 */
/* controller 1 */
#define	CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
#define	CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
#define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
#define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull

#define CONFIG_SYS_BMAN_NUM_PORTALS	10
#define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
#define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
#define CONFIG_SYS_BMAN_MEM_SIZE	0x02000000
#define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
#define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
					CONFIG_SYS_BMAN_CENA_SIZE)
#define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_BMAN_SWP_ISDR_REG	0xE08
#define CONFIG_SYS_QMAN_NUM_PORTALS	10
#define CONFIG_SYS_QMAN_MEM_BASE	0xf6000000
#define CONFIG_SYS_QMAN_MEM_PHYS	0xff6000000ull
#define CONFIG_SYS_QMAN_MEM_SIZE	0x02000000
#define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
#define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
					CONFIG_SYS_QMAN_CENA_SIZE)
#define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_QMAN_SWP_ISDR_REG	0xE08

#define CONFIG_SYS_DPAA_FMAN
#define CONFIG_SYS_DPAA_PME

#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)

/* Qman / Bman */
/* RGMII (FM1@DTESC5) is local managemant interface */
#define CONFIG_SYS_RGMII2_PHY_ADDR             0x11

/*
 * Hardware Watchdog
 */
#define CONFIG_WATCHDOG_PRESC 34	/* wdog prescaler 2^(64-34) ~10min */
#define CONFIG_WATCHDOG_RC WRC_CHIP	/* reset chip on watchdog event */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 64 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */

/*
 * Environment Configuration
 */
#ifndef CONFIG_KM_DEF_ENV		/* if not set by keymile-common.h */
#define CONFIG_KM_DEF_ENV
#endif

#define __USB_PHY_TYPE	utmi

#define CONFIG_KM_DEF_ENV_CPU						\
	"boot=bootm ${load_addr_r} - ${fdt_addr_r}\0"			\
	"cramfsloadfdt="						\
		"cramfsload ${fdt_addr_r} "				\
		"fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0"		\
	"u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0"		\
	"update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)	\
		" +${filesize} && "					\
		"erase " __stringify(CONFIG_SYS_MONITOR_BASE)		\
		" +${filesize} && "					\
		"cp.b ${load_addr_r} "					\
		__stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize} && "	\
		"protect on " __stringify(CONFIG_SYS_MONITOR_BASE)	\
		" +${filesize}\0"					\
	"update-nor=protect off " __stringify(CONFIG_SYS_FLASH_BASE)	\
		" +${filesize} && "					\
		"erase " __stringify(CONFIG_SYS_FLASH_BASE)		\
		" +${filesize} && "					\
		"cp.b ${load_addr_r} "					\
		__stringify(CONFIG_SYS_FLASH_BASE) " ${filesize} && "	\
		"protect on " __stringify(CONFIG_SYS_MONITOR_BASE)	\
		" +" __stringify(CONFIG_SYS_MONITOR_LEN) "\0"		\
	"set_fdthigh=true\0"						\
	"checkfdt=true\0"						\
	"fpgacfg=true\0"						\
	""

#define CONFIG_HW_ENV_SETTINGS						\
	"hwconfig=fsl_ddr:ctlr_intlv=cacheline\0"			\
	"usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0"		\
	"usb_dr_mode=host\0"

#define CONFIG_KM_NEW_ENV						\
	"newenv=protect off " __stringify(ENV_DEL_ADDR)			\
		" +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && "		\
		"erase " __stringify(ENV_DEL_ADDR)			\
		" +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && "		\
		"protect on " __stringify(ENV_DEL_ADDR)			\
		" +" __stringify(CONFIG_ENV_TOTAL_SIZE) "\0"

/* ppc_82xx is the equivalent to ppc_6xx, the generic ppc toolchain */
#ifndef CONFIG_KM_DEF_ARCH
#define CONFIG_KM_DEF_ARCH	"arch=ppc_82xx\0"
#endif

#define CONFIG_EXTRA_ENV_SETTINGS					\
	CONFIG_KM_DEF_ENV						\
	CONFIG_KM_DEF_ARCH						\
	CONFIG_KM_NEW_ENV						\
	CONFIG_HW_ENV_SETTINGS						\
	"EEprom_ivm=pca9547:70:9\0"					\
	""

#endif	/* __KMCENT2_H */
Commit	Line	Data
37bfd9cb NF	1	/* SPDX-License-Identifier: GPL-2.0+ */
	2	/*
	3	* (C) Copyright 2016 Keymile AG
	4	* Rainer Boschung <[email protected]>
	5	*
	6	*/
	7
	8	#ifndef __KMCENT2_H
	9	#define __KMCENT2_H
	10
	11	#define CONFIG_HOSTNAME "kmcent2"
	12	#define KM_BOARD_NAME CONFIG_HOSTNAME
	13
	14	/*
	15	* The Linux fsl_fman driver needs to be able to process frames with more
	16	* than just the VLAN tag (i.e. eDSA tag). It is passed as a kernel boot
	17	* parameters
	18	*/
	19	#define CONFIG_KM_DEF_BOOT_ARGS_CPU "fsl_dpaa_fman.fsl_fm_max_frm=1558"
	20
	21	#include "km/keymile-common.h"
	22
	23	/* Application IFC chip selects */
	24	#define SYS_LAWAPP_BASE 0xc0000000
	25	#define SYS_LAWAPP_BASE_PHYS (0xf00000000ull \| SYS_LAWAPP_BASE)
	26
	27	/* Application IFC CS4 MRAM */
	28	#define CONFIG_SYS_MRAM_BASE SYS_LAWAPP_BASE
	29	#define SYS_MRAM_BASE_PHYS SYS_LAWAPP_BASE_PHYS
	30	#define SYS_MRAM_CSPR_EXT (0x0f)
	31	#define SYS_MRAM_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_MRAM_BASE) \| \
	32	CSPR_PORT_SIZE_8 \| /* 8 bit */ \
	33	CSPR_MSEL_GPCM \| /* msel = gpcm */ \
	34	CSPR_V /* bank is valid */)
	35	#define SYS_MRAM_AMASK IFC_AMASK(2 * 1024 * 1024) /* 2 MiB */
	36	#define SYS_MRAM_CSOR CSOR_GPCM_TRHZ_40
	37	/* MRAM Timing parameters for IFC CS4 */
	38	#define SYS_MRAM_FTIM0 (FTIM0_GPCM_TACSE(0x6) \| \
	39	FTIM0_GPCM_TEADC(0x8) \| \
	40	FTIM0_GPCM_TEAHC(0x2))
	41	#define SYS_MRAM_FTIM1 (FTIM1_GPCM_TACO(0x2) \| \
	42	FTIM1_GPCM_TRAD(0xe))
	43	#define SYS_MRAM_FTIM2 (FTIM2_GPCM_TCS(0x2) \| \
	44	FTIM2_GPCM_TCH(0x2) \| \
	45	FTIM2_GPCM_TWP(0x8))
	46	#define SYS_MRAM_FTIM3 0x04000000
	47	#define CONFIG_SYS_CSPR4_EXT SYS_MRAM_CSPR_EXT
	48	#define CONFIG_SYS_CSPR4 SYS_MRAM_CSPR
	49	#define CONFIG_SYS_AMASK4 SYS_MRAM_AMASK
	50	#define CONFIG_SYS_CSOR4 SYS_MRAM_CSOR
	51	#define CONFIG_SYS_CS4_FTIM0 SYS_MRAM_FTIM0
	52	#define CONFIG_SYS_CS4_FTIM1 SYS_MRAM_FTIM1
	53	#define CONFIG_SYS_CS4_FTIM2 SYS_MRAM_FTIM2
	54	#define CONFIG_SYS_CS4_FTIM3 SYS_MRAM_FTIM3
	55
	56	/* Application IFC CS6: BFTIC */
	57	#define SYS_BFTIC_BASE 0xd0000000
	58	#define SYS_BFTIC_BASE_PHYS (0xf00000000ull \| SYS_BFTIC_BASE)
	59	#define SYS_BFTIC_CSPR_EXT (0x0f)
	60	#define SYS_BFTIC_CSPR (CSPR_PHYS_ADDR(SYS_BFTIC_BASE) \| \
	61	CSPR_PORT_SIZE_8 \| /* Port size = 8 bit */\
	62	CSPR_MSEL_GPCM \| /* MSEL = GPCM */\
	63	CSPR_V) /* valid */
	64	#define SYS_BFTIC_AMASK IFC_AMASK(64 * 1024) /* 64kB */
65	#define SYS_BFTIC_CSOR CSOR_GPCM_TRHZ_40
66	/* BFTIC Timing parameters for IFC CS6 */
67	#define SYS_BFTIC_FTIM0 (FTIM0_GPCM_TACSE(0x6) \| \
68	FTIM0_GPCM_TEADC(0x8) \| \
69	FTIM0_GPCM_TEAHC(0x2))
70	#define SYS_BFTIC_FTIM1 (FTIM1_GPCM_TACO(0x2) \| \
71	FTIM1_GPCM_TRAD(0x12))
72	#define SYS_BFTIC_FTIM2 (FTIM2_GPCM_TCS(0x3) \| \
73	FTIM2_GPCM_TCH(0x1) \| \
74	FTIM2_GPCM_TWP(0x12))
75	#define SYS_BFTIC_FTIM3 0x04000000
76	#define CONFIG_SYS_CSPR6_EXT SYS_BFTIC_CSPR_EXT
77	#define CONFIG_SYS_CSPR6 SYS_BFTIC_CSPR
78	#define CONFIG_SYS_AMASK6 SYS_BFTIC_AMASK
79	#define CONFIG_SYS_CSOR6 SYS_BFTIC_CSOR
80	#define CONFIG_SYS_CS6_FTIM0 SYS_BFTIC_FTIM0
81	#define CONFIG_SYS_CS6_FTIM1 SYS_BFTIC_FTIM1
82	#define CONFIG_SYS_CS6_FTIM2 SYS_BFTIC_FTIM2
83	#define CONFIG_SYS_CS6_FTIM3 SYS_BFTIC_FTIM3
84
85	/* Application IFC CS7 PAXE */
86	#define CONFIG_SYS_PAXE_BASE 0xd8000000
87	#define SYS_PAXE_BASE_PHYS (0xf00000000ull \| CONFIG_SYS_PAXE_BASE)
88	#define SYS_PAXE_CSPR_EXT (0x0f)
89	#define SYS_PAXE_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_PAXE_BASE) \| \
90	CSPR_PORT_SIZE_8 \| /* Port size = 8 bit */\
91	CSPR_MSEL_GPCM \| /* MSEL = GPCM */\
92	CSPR_V) /* valid */
93	#define SYS_PAXE_AMASK IFC_AMASK(64 * 1024) /* 64kB */
94	#define SYS_PAXE_CSOR CSOR_GPCM_TRHZ_40
95	/* PAXE Timing parameters for IFC CS7 */
96	#define SYS_PAXE_FTIM0 (FTIM0_GPCM_TACSE(0x6) \| \
97	FTIM0_GPCM_TEADC(0x8) \| \
98	FTIM0_GPCM_TEAHC(0x2))
99	#define SYS_PAXE_FTIM1 (FTIM1_GPCM_TACO(0x2) \| \
100	FTIM1_GPCM_TRAD(0x12))
101	#define SYS_PAXE_FTIM2 (FTIM2_GPCM_TCS(0x3) \| \
102	FTIM2_GPCM_TCH(0x1) \| \
103	FTIM2_GPCM_TWP(0x12))
104	#define SYS_PAXE_FTIM3 0x04000000
105	#define CONFIG_SYS_CSPR7_EXT SYS_PAXE_CSPR_EXT
106	#define CONFIG_SYS_CSPR7 SYS_PAXE_CSPR
107	#define CONFIG_SYS_AMASK7 SYS_PAXE_AMASK
108	#define CONFIG_SYS_CSOR7 SYS_PAXE_CSOR
109	#define CONFIG_SYS_CS7_FTIM0 SYS_PAXE_FTIM0
110	#define CONFIG_SYS_CS7_FTIM1 SYS_PAXE_FTIM1
111	#define CONFIG_SYS_CS7_FTIM2 SYS_PAXE_FTIM2
112	#define CONFIG_SYS_CS7_FTIM3 SYS_PAXE_FTIM3
113
114	/* PRST */
115	#define KM_BFTIC4_RST 0
116	#define KM_DPAXE_RST 1
117	#define KM_FEMT_RST 3
118	#define KM_FOAM_RST 4
119	#define KM_EFE_RST 5
120	#define KM_ES_PHY_RST 6
121	#define KM_XES_PHY_RST 7
122	#define KM_ZL30158_RST 8
123	#define KM_ZL30364_RST 9
124	#define KM_BOBCAT_RST 10
125	#define KM_ETHSW_DDR_RST 12
126	#define KM_CFE_RST 13
127	#define KM_PEXSW_RST 14
128	#define KM_PEXSW_NT_RST 15
129
130	/* QRIO GPIOs used for deblocking */
131	#define KM_I2C_DEBLOCK_PORT QRIO_GPIO_A
132	#define KM_I2C_DEBLOCK_SCL 20
133	#define KM_I2C_DEBLOCK_SDA 21
134
135	/* High Level Configuration Options */
136	#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
137	#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
138
139	#define CONFIG_RESET_VECTOR_ADDRESS 0xebfffffc
140
141	#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
142	#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
143	#define CONFIG_PCIE1 /* PCIE controller 1 */
37bfd9cb NF	144
	145	/* Environment in parallel NOR-Flash */
	146	#define CONFIG_ENV_TOTAL_SIZE 0x040000
	147	#define ENV_DEL_ADDR 0xebf00000 /direct for newenv/
	148
37bfd9cb NF	149	/*
	150	* These can be toggled for performance analysis, otherwise use default.
	151	*/
	152	#define CONFIG_SYS_CACHE_STASHING
37bfd9cb	153	#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
37bfd9cb NF	154
	155	#define CONFIG_ENABLE_36BIT_PHYS
	156
	157	/* POST memory regions test */
	158	#define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS
	159
	160	/*
	161	* Config the L3 Cache as L3 SRAM
	162	*/
	163	#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
	164	#define CONFIG_SYS_L3_SIZE 256 << 10
	165
	166	#define CONFIG_SYS_DCSRBAR 0xf0000000
	167	#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
	168
	169	/*
	170	* DDR Setup
	171	*/
	172	#define CONFIG_VERY_BIG_RAM
	173	#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
	174	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
37bfd9cb NF	175
37bfd9cb NF	176	#define CONFIG_DIMM_SLOTS_PER_CTLR 1
37bfd9cb	177
37bfd9cb NF	178	#define CONFIG_SYS_SPD_BUS_NUM 0
	179	#define SPD_EEPROM_ADDRESS 0x54
	180	#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
	181
37bfd9cb NF	182	/******************************************************************************
	183	* (PRAM usage)
	184	* ... -------------------------------------------------------
	185	* ... \|ROOTFSSIZE \| PNVRAM \|PHRAM \|RESERVED_PRAM \| END_OF_RAM
	186	* ... \|<------------------- pram -------------------------->\|
	187	* ... -------------------------------------------------------
	188	* @END_OF_RAM:
	189	* @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose
	190	* @CONFIG_KM_PHRAM: address for /var
	191	* @CONFIG_KM_PNVRAM: address for PNVRAM (for the application)
	192	* @CONFIG_KM_ROOTFSSIZE: address for rootfilesystem in RAM
	193	*/
	194
	195	/* size of rootfs in RAM */
	196	#define CONFIG_KM_ROOTFSSIZE 0x0
	197	/* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable
	198	* is not valid yet, which is the case for when u-boot copies itself to RAM
	199	*/
	200	#define CONFIG_PRAM ((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM) >> 10)
	201
	202	/*
	203	* IFC Definitions
	204	*/
	205	/* NOR flash on IFC CS0 */
	206	#define CONFIG_SYS_FLASH_BASE 0xe8000000
	207	#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull \| \
	208	CONFIG_SYS_FLASH_BASE)
	209
	210	#define CONFIG_SYS_NOR_CSPR_EXT (0x0f)
	211	#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) \| \
	212	CSPR_PORT_SIZE_16 \| /* Port size = 16 bit */\
	213	0x00000010 \| /* drive TE high */\
	214	CSPR_MSEL_NOR \| /* MSEL = NOR */\
	215	CSPR_V) /* valid */
	216	#define CONFIG_SYS_NOR_AMASK IFC_AMASK(64 * 1024 * 1024) /* 64MB */
	217	#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_AVD_TGL_PGM_EN \| /* AVD toggle */\
	218	CSOR_NOR_TRHZ_20 \| \
	219	CSOR_NOR_BCTLD)
	220
	221	/* NOR Flash Timing Params */
	222	#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) \| \
	223	FTIM0_NOR_TEADC(0x7) \| \
	224	FTIM0_NOR_TEAHC(0x1))
	225	#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) \| \
	226	FTIM1_NOR_TRAD_NOR(0x21) \| \
	227	FTIM1_NOR_TSEQRAD_NOR(0x21))
	228	#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCH(0x1) \| \
	229	FTIM2_NOR_TCS(0x1) \| \
	230	FTIM2_NOR_TWP(0xb) \| \
	231	FTIM2_NOR_TWPH(0x6))
	232	#define CONFIG_SYS_NOR_FTIM3 0x0
	233
	234	#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
	235	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
	236	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
	237	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
	238	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
	239	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
	240	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
	241	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
	242
	243	/* More NOR Flash params */
	244	#define CONFIG_SYS_FLASH_QUIET_TEST
	245
37bfd9cb NF	246	#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
	247
	248	#define CONFIG_SYS_FLASH_EMPTY_INFO
	249	#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
	250
	251	/* NAND Flash on IFC CS1*/
37bfd9cb NF	252	#define CONFIG_SYS_NAND_BASE 0xfa000000
	253	#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull \| CONFIG_SYS_NAND_BASE)
	254
	255	#define CONFIG_SYS_NAND_CSPR_EXT (0x0f)
	256	#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE) \| \
	257	CSPR_PORT_SIZE_8 \| /* Port Size = 8 bit */\
	258	0x00000010 \| /* drive TE high */\
	259	CSPR_MSEL_NAND \| /* MSEL = NAND */\
	260	CSPR_V) /* valid */
	261	#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) /* 64kB */
	262
	263	#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN \| /* ECC encoder on */ \
	264	CSOR_NAND_ECC_DEC_EN \| /* ECC decoder on */ \
	265	CSOR_NAND_ECC_MODE_4 \| /* 4-bit ECC */ \
	266	CSOR_NAND_RAL_3 \| /* RAL = 3Bytes */ \
	267	CSOR_NAND_PGS_2K \| /* Page size = 2K */ \
	268	CSOR_NAND_SPRZ_128 \| /* Spare size = 128 */ \
	269	CSOR_NAND_PB(64) \| /* 64 Pages/Block */ \
	270	CSOR_NAND_TRHZ_40 \| /**/ \
	271	CSOR_NAND_BCTLD) /**/
	272
37bfd9cb NF	273	/* ONFI NAND Flash mode0 Timing Params */
	274	#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x3) \| \
	275	FTIM0_NAND_TWP(0x8) \| \
	276	FTIM0_NAND_TWCHT(0x3) \| \
	277	FTIM0_NAND_TWH(0x5))
	278	#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1e) \| \
	279	FTIM1_NAND_TWBE(0x1e) \| \
	280	FTIM1_NAND_TRR(0x6) \| \
	281	FTIM1_NAND_TRP(0x8))
	282	#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x9) \| \
	283	FTIM2_NAND_TREH(0x5) \| \
	284	FTIM2_NAND_TWHRE(0x3c))
	285	#define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x1e))
	286
	287	#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
	288	#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
	289	#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
	290	#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
	291	#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
	292	#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
	293	#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
	294	#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
	295
	296	/* More NAND Flash Params */
	297	#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
	298	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	299
	300	/* QRIO on IFC CS2 */
	301	#define CONFIG_SYS_QRIO_BASE 0xfb000000
	302	#define CONFIG_SYS_QRIO_BASE_PHYS (0xf00000000ull \| CONFIG_SYS_QRIO_BASE)
	303	#define SYS_QRIO_CSPR_EXT (0x0f)
	304	#define SYS_QRIO_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE) \| \
	305	CSPR_PORT_SIZE_8 \| /* Port size = 8 bit */\
	306	0x00000010 \| /* drive TE high */\
	307	CSPR_MSEL_GPCM \| /* MSEL = GPCM */\
	308	CSPR_V) /* valid */
	309	#define SYS_QRIO_AMASK IFC_AMASK(64 * 1024) /* 64kB */
	310	#define SYS_QRIO_CSOR (CSOR_GPCM_TRHZ_20 \|\
	311	CSOR_GPCM_BCTLD)
	312	/* QRIO Timing parameters for IFC CS2 */
	313	#define SYS_QRIO_FTIM0 (FTIM0_GPCM_TACSE(0x2) \| \
	314	FTIM0_GPCM_TEADC(0x8) \| \
	315	FTIM0_GPCM_TEAHC(0x2))
	316	#define SYS_QRIO_FTIM1 (FTIM1_GPCM_TACO(0x2) \| \
	317	FTIM1_GPCM_TRAD(0x6))
	318	#define SYS_QRIO_FTIM2 (FTIM2_GPCM_TCS(0x1) \| \
	319	FTIM2_GPCM_TCH(0x1) \| \
	320	FTIM2_GPCM_TWP(0x7))
	321	#define SYS_QRIO_FTIM3 0x04000000
	322	#define CONFIG_SYS_CSPR2_EXT SYS_QRIO_CSPR_EXT
	323	#define CONFIG_SYS_CSPR2 SYS_QRIO_CSPR
	324	#define CONFIG_SYS_AMASK2 SYS_QRIO_AMASK
	325	#define CONFIG_SYS_CSOR2 SYS_QRIO_CSOR
	326	#define CONFIG_SYS_CS2_FTIM0 SYS_QRIO_FTIM0
	327	#define CONFIG_SYS_CS2_FTIM1 SYS_QRIO_FTIM1
	328	#define CONFIG_SYS_CS2_FTIM2 SYS_QRIO_FTIM2
	329	#define CONFIG_SYS_CS2_FTIM3 SYS_QRIO_FTIM3
	330
37bfd9cb NF	331	#define CONFIG_HWCONFIG
	332
	333	/* define to use L1 as initial stack */
	334	#define CONFIG_SYS_INIT_RAM_LOCK
	335	#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
	336	#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
	337	#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
	338	/* The assembler doesn't like typecast */
	339	#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
	340	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) \| \
	341	CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
	342	#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
	343
	344	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
	345	GENERATED_GBL_DATA_SIZE)
	346	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
	347
	348	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
	349	#define CONFIG_SYS_MONITOR_LEN 0xc0000 /* 768k */
	350
37bfd9cb NF	351	/*
	352	* Serial Port - controlled on board with jumper J8
	353	* open - index 2
	354	* shorted - index 1
	355	* Retain non-DM serial port for debug purposes.
	356	*/
	357	#if !defined(CONFIG_DM_SERIAL)
37bfd9cb NF	358	#define CONFIG_SYS_NS16550_SERIAL
	359	#define CONFIG_SYS_NS16550_REG_SIZE 1
	360	#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
	361	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x11C500)
	362	#endif
	363
	364	#ifndef __ASSEMBLY__
	365	void set_sda(int state);
	366	void set_scl(int state);
	367	int get_sda(void);
	368	int get_scl(void);
	369	#endif
	370
	371	/*
	372	* General PCI
	373	* Memory space is mapped 1-1, but I/O space must start from 0.
	374	*/
	375	/* controller 1 */
	376	#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
	377	#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
	378	#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
	379	#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
	380
	381	#define CONFIG_SYS_BMAN_NUM_PORTALS 10
	382	#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
	383	#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
	384	#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
	385	#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
	386	#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
	387	#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
	388	CONFIG_SYS_BMAN_CENA_SIZE)
	389	#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
	390	#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
	391	#define CONFIG_SYS_QMAN_NUM_PORTALS 10
	392	#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
	393	#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
	394	#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
	395	#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
	396	#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
	397	#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
	398	CONFIG_SYS_QMAN_CENA_SIZE)
	399	#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
	400	#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
	401
	402	#define CONFIG_SYS_DPAA_FMAN
	403	#define CONFIG_SYS_DPAA_PME
	404
37bfd9cb NF	405	#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
	406
	407	/* Qman / Bman */
	408	/* RGMII (FM1@DTESC5) is local managemant interface */
	409	#define CONFIG_SYS_RGMII2_PHY_ADDR 0x11
37bfd9cb NF	410
	411	/*
	412	* Hardware Watchdog
	413	*/
	414	#define CONFIG_WATCHDOG_PRESC 34 /* wdog prescaler 2^(64-34) ~10min */
	415	#define CONFIG_WATCHDOG_RC WRC_CHIP /* reset chip on watchdog event */
	416
	417	/*
	418	* For booting Linux, the board info and command line data
	419	* have to be in the first 64 MB of memory, since this is
	420	* the maximum mapped by the Linux kernel during initialization.
	421	*/
	422	#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
	423	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
	424
	425	/*
	426	* Environment Configuration
	427	*/
	428	#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */
	429	#define CONFIG_KM_DEF_ENV
	430	#endif
	431
	432	#define __USB_PHY_TYPE utmi
	433
	434	#define CONFIG_KM_DEF_ENV_CPU \
	435	"boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \
	436	"cramfsloadfdt=" \
	437	"cramfsload ${fdt_addr_r} " \
	438	"fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \
	439	"u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0" \
	440	"update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
	441	" +${filesize} && " \
	442	"erase " __stringify(CONFIG_SYS_MONITOR_BASE) \
	443	" +${filesize} && " \
	444	"cp.b ${load_addr_r} " \
	445	__stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize} && " \
	446	"protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \
	447	" +${filesize}\0" \
	448	"update-nor=protect off " __stringify(CONFIG_SYS_FLASH_BASE) \
	449	" +${filesize} && " \
	450	"erase " __stringify(CONFIG_SYS_FLASH_BASE) \
	451	" +${filesize} && " \
	452	"cp.b ${load_addr_r} " \
	453	__stringify(CONFIG_SYS_FLASH_BASE) " ${filesize} && " \
	454	"protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \
	455	" +" __stringify(CONFIG_SYS_MONITOR_LEN) "\0" \
	456	"set_fdthigh=true\0" \
	457	"checkfdt=true\0" \
	458	"fpgacfg=true\0" \
	459	""
	460
	461	#define CONFIG_HW_ENV_SETTINGS \
	462	"hwconfig=fsl_ddr:ctlr_intlv=cacheline\0" \
	463	"usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
	464	"usb_dr_mode=host\0"
	465
	466	#define CONFIG_KM_NEW_ENV \
	467	"newenv=protect off " __stringify(ENV_DEL_ADDR) \
	468	" +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && " \
	469	"erase " __stringify(ENV_DEL_ADDR) \
	470	" +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && " \
	471	"protect on " __stringify(ENV_DEL_ADDR) \
	472	" +" __stringify(CONFIG_ENV_TOTAL_SIZE) "\0"
	473
474	/* ppc_82xx is the equivalent to ppc_6xx, the generic ppc toolchain */
475	#ifndef CONFIG_KM_DEF_ARCH
476	#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
477	#endif
478
479	#define CONFIG_EXTRA_ENV_SETTINGS \
480	CONFIG_KM_DEF_ENV \
481	CONFIG_KM_DEF_ARCH \
482	CONFIG_KM_NEW_ENV \
483	CONFIG_HW_ENV_SETTINGS \
484	"EEprom_ivm=pca9547:70:9\0" \
485	""
486
487	#endif /* __KMCENT2_H */