[J-u-boot.git] / arch / x86 / cpu / broadwell / cpu.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2016 Google, Inc
 *
 * Based on code from coreboot src/soc/intel/broadwell/cpu.c
 */

#include <common.h>
#include <dm.h>
#include <cpu.h>
#include <event.h>
#include <init.h>
#include <log.h>
#include <asm/cpu.h>
#include <asm/cpu_x86.h>
#include <asm/cpu_common.h>
#include <asm/global_data.h>
#include <asm/intel_regs.h>
#include <asm/lpc_common.h>
#include <asm/msr.h>
#include <asm/pci.h>
#include <asm/post.h>
#include <asm/turbo.h>
#include <asm/arch/cpu.h>
#include <asm/arch/pch.h>
#include <asm/arch/rcb.h>

static int broadwell_init_cpu(void *ctx, struct event *event)
{
	struct udevice *dev;
	int ret;

	/* Start up the LPC so we have serial */
	ret = uclass_first_device(UCLASS_LPC, &dev);
	if (ret)
		return ret;
	if (!dev)
		return -ENODEV;
	ret = cpu_set_flex_ratio_to_tdp_nominal();
	if (ret)
		return ret;

	return 0;
}
EVENT_SPY(EVT_DM_POST_INIT, broadwell_init_cpu);

void set_max_freq(void)
{
	msr_t msr, perf_ctl;

	if (cpu_config_tdp_levels()) {
		/* Set to nominal TDP ratio */
		msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
		perf_ctl.lo = (msr.lo & 0xff) << 8;
	} else {
		/* Platform Info bits 15:8 give max ratio */
		msr = msr_read(MSR_PLATFORM_INFO);
		perf_ctl.lo = msr.lo & 0xff00;
	}

	perf_ctl.hi = 0;
	msr_write(MSR_IA32_PERF_CTL, perf_ctl);

	debug("CPU: frequency set to %d MHz\n",
	      ((perf_ctl.lo >> 8) & 0xff) * INTEL_BCLK_MHZ);
}

int arch_cpu_init(void)
{
	post_code(POST_CPU_INIT);

#ifdef CONFIG_TPL
	/* Do a mini-init if TPL has already done the full init */
	return x86_cpu_reinit_f();
#else
	return x86_cpu_init_f();
#endif
}

int checkcpu(void)
{
	int ret;

	set_max_freq();

	ret = cpu_common_init();
	if (ret)
		return ret;
	gd->arch.pei_boot_mode = PEI_BOOT_NONE;

	return 0;
}

int print_cpuinfo(void)
{
	char processor_name[CPU_MAX_NAME_LEN];
	const char *name;

	/* Print processor name */
	name = cpu_get_name(processor_name);
	printf("CPU:   %s\n", name);

	return 0;
}

void board_debug_uart_init(void)
{
	/* com1 / com2 decode range */
	pci_x86_write_config(PCH_DEV_LPC, LPC_IO_DEC, 1 << 4, PCI_SIZE_16);

	pci_x86_write_config(PCH_DEV_LPC, LPC_EN, COMA_LPC_EN, PCI_SIZE_16);
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0
2f3f477b SG	2	/*
	3	* Copyright (c) 2016 Google, Inc
	4	*
2f3f477b SG	5	* Based on code from coreboot src/soc/intel/broadwell/cpu.c
	6	*/
	7
	8	#include <common.h>
	9	#include <dm.h>
	10	#include <cpu.h>
7fe32b34	11	#include <event.h>
691d719d	12	#include <init.h>
f7ae49fc	13	#include <log.h>
2f3f477b SG	14	#include <asm/cpu.h>
	15	#include <asm/cpu_x86.h>
	16	#include <asm/cpu_common.h>
401d1c4f	17	#include <asm/global_data.h>
2f3f477b	18	#include <asm/intel_regs.h>
6b83b295	19	#include <asm/lpc_common.h>
2f3f477b	20	#include <asm/msr.h>
6b83b295	21	#include <asm/pci.h>
2f3f477b SG	22	#include <asm/post.h>
	23	#include <asm/turbo.h>
	24	#include <asm/arch/cpu.h>
	25	#include <asm/arch/pch.h>
	26	#include <asm/arch/rcb.h>
	27
7fe32b34	28	static int broadwell_init_cpu(void ctx, struct event event)
2f3f477b SG	29	{
	30	struct udevice *dev;
	31	int ret;
	32
	33	/* Start up the LPC so we have serial */
	34	ret = uclass_first_device(UCLASS_LPC, &dev);
	35	if (ret)
	36	return ret;
	37	if (!dev)
	38	return -ENODEV;
	39	ret = cpu_set_flex_ratio_to_tdp_nominal();
	40	if (ret)
	41	return ret;
	42
	43	return 0;
	44	}
7fe32b34	45	EVENT_SPY(EVT_DM_POST_INIT, broadwell_init_cpu);
2f3f477b SG	46
	47	void set_max_freq(void)
	48	{
2f0c2f03	49	msr_t msr, perf_ctl;
2f3f477b	50
2f0c2f03	51	if (cpu_config_tdp_levels()) {
2f3f477b SG	52	/* Set to nominal TDP ratio */
	53	msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
	54	perf_ctl.lo = (msr.lo & 0xff) << 8;
	55	} else {
	56	/* Platform Info bits 15:8 give max ratio */
	57	msr = msr_read(MSR_PLATFORM_INFO);
	58	perf_ctl.lo = msr.lo & 0xff00;
	59	}
	60
	61	perf_ctl.hi = 0;
e2493a7f	62	msr_write(MSR_IA32_PERF_CTL, perf_ctl);
2f3f477b SG	63
2f3f477b SG	64	debug("CPU: frequency set to %d MHz\n",
55a6b13a	65	((perf_ctl.lo >> 8) & 0xff) * INTEL_BCLK_MHZ);
2f3f477b SG	66	}
	67
	68	int arch_cpu_init(void)
	69	{
	70	post_code(POST_CPU_INIT);
	71
12c81b2f SG	72	#ifdef CONFIG_TPL
	73	/* Do a mini-init if TPL has already done the full init */
	74	return x86_cpu_reinit_f();
	75	#else
2f3f477b	76	return x86_cpu_init_f();
12c81b2f	77	#endif
2f3f477b SG	78	}
2f3f477b SG	79
76d1d02f	80	int checkcpu(void)
2f3f477b	81	{
2f3f477b SG	82	int ret;
	83
	84	set_max_freq();
	85
	86	ret = cpu_common_init();
	87	if (ret)
	88	return ret;
	89	gd->arch.pei_boot_mode = PEI_BOOT_NONE;
	90
76d1d02f SG	91	return 0;
	92	}
	93
	94	int print_cpuinfo(void)
	95	{
	96	char processor_name[CPU_MAX_NAME_LEN];
	97	const char *name;
	98
2f3f477b SG	99	/* Print processor name */
	100	name = cpu_get_name(processor_name);
	101	printf("CPU: %s\n", name);
	102
	103	return 0;
	104	}
	105
6b83b295 SG	106	void board_debug_uart_init(void)
6b83b295 SG	107	{
6b83b295	108	/* com1 / com2 decode range */
a827ba91	109	pci_x86_write_config(PCH_DEV_LPC, LPC_IO_DEC, 1 << 4, PCI_SIZE_16);
6b83b295	110
a827ba91	111	pci_x86_write_config(PCH_DEV_LPC, LPC_EN, COMA_LPC_EN, PCI_SIZE_16);
6b83b295	112	}