[J-u-boot.git] / arch / arm / cpu / lh7a40x / start.S

/*
 *  armboot - Startup Code for ARM920 CPU-core
 *
 *  Copyright (c) 2001	Marius Gröger <[email protected]>
 *  Copyright (c) 2002	Alex Züpke <[email protected]>
 *  Copyright (c) 2002	Gary Jennejohn <[email protected]>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <asm-offsets.h>
#include <config.h>
#include <version.h>

/*
 *************************************************************************
 *
 * Jump vector table as in table 3.1 in [1]
 *
 *************************************************************************
 */


.globl _start
_start:	b       reset
	ldr	pc, _undefined_instruction
	ldr	pc, _software_interrupt
	ldr	pc, _prefetch_abort
	ldr	pc, _data_abort
	ldr	pc, _not_used
	ldr	pc, _irq
	ldr	pc, _fiq

_undefined_instruction:	.word undefined_instruction
_software_interrupt:	.word software_interrupt
_prefetch_abort:	.word prefetch_abort
_data_abort:		.word data_abort
_not_used:		.word not_used
_irq:			.word irq
_fiq:			.word fiq

	.balignl 16,0xdeadbeef


/*
 *************************************************************************
 *
 * Startup Code (reset vector)
 *
 * do important init only if we don't start from memory!
 * relocate armboot to ram
 * setup stack
 * jump to second stage
 *
 *************************************************************************
 */

.globl _TEXT_BASE
_TEXT_BASE:
	.word	CONFIG_SYS_TEXT_BASE

/*
 * These are defined in the board-specific linker script.
 * Subtracting _start from them lets the linker put their
 * relative position in the executable instead of leaving
 * them null.
 */
.globl _bss_start_ofs
_bss_start_ofs:
	.word __bss_start - _start

.globl _bss_end_ofs
_bss_end_ofs:
	.word __bss_end__ - _start

.globl _end_ofs
_end_ofs:
	.word _end - _start

#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.globl IRQ_STACK_START
IRQ_STACK_START:
	.word	0x0badc0de

/* IRQ stack memory (calculated at run-time) */
.globl FIQ_STACK_START
FIQ_STACK_START:
	.word 0x0badc0de
#endif

/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
	.word	0x0badc0de

/*
 * the actual reset code
 */

reset:
	/*
	 * set the cpu to SVC32 mode
	 */
	mrs	r0,cpsr
	bic	r0,r0,#0x1f
	orr	r0,r0,#0xd3
	msr	cpsr,r0

#define pWDTCTL		0x80001400  /* Watchdog Timer control register */
#define pINTENC		0x8000050C  /* Interrupt-Controller enable clear register */
#define pCLKSET		0x80000420  /* clock divisor register */

	/* disable watchdog, set watchdog control register to
	 * all zeros (default reset)
	 */
	ldr     r0, =pWDTCTL
	mov     r1, #0x0
	str     r1, [r0]

	/*
	 * mask all IRQs by setting all bits in the INTENC register (default)
	 */
	mov	r1, #0xffffffff
	ldr	r0, =pINTENC
	str	r1, [r0]

	/* FCLK:HCLK:PCLK = 1:2:2 */
	/* default FCLK is 200 MHz, using 14.7456 MHz fin */
	ldr	r0, =pCLKSET
	ldr r1, =0x0004ee39
@	ldr r1, =0x0005ee39	@ 1: 2: 4
	str	r1, [r0]

	/*
	 * we do sys-critical inits only at reboot,
	 * not when booting from ram!
	 */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
	bl	cpu_init_crit
#endif

/* Set stackpointer in internal RAM to call board_init_f */
call_board_init_f:
	ldr	sp, =(CONFIG_SYS_INIT_SP_ADDR)
	bic	sp, sp, #7 /* 8-byte alignment for ABI compliance */
	ldr	r0,=0x00000000
	bl	board_init_f

/*------------------------------------------------------------------------------*/

/*
 * void relocate_code (addr_sp, gd, addr_moni)
 *
 * This "function" does not return, instead it continues in RAM
 * after relocating the monitor code.
 *
 */
	.globl	relocate_code
relocate_code:
	mov	r4, r0	/* save addr_sp */
	mov	r5, r1	/* save addr of gd */
	mov	r6, r2	/* save addr of destination */

	/* Set up the stack						    */
stack_setup:
	mov	sp, r4

	adr	r0, _start
	cmp	r0, r6
	moveq	r9, #0		/* no relocation. relocation offset(r9) = 0 */
	beq	clear_bss		/* skip relocation */
	mov	r1, r6			/* r1 <- scratch for copy_loop */
	ldr	r3, _bss_start_ofs
	add	r2, r0, r3		/* r2 <- source end address	    */

copy_loop:
	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
	stmia	r1!, {r9-r10}		/* copy to   target address [r1]    */
	cmp	r0, r2			/* until source end address [r2]    */
	blo	copy_loop

#ifndef CONFIG_SPL_BUILD
	/*
	 * fix .rel.dyn relocations
	 */
	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
	sub	r9, r6, r0		/* r9 <- relocation offset */
	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
	add	r10, r10, r0		/* r10 <- sym table in FLASH */
	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
fixloop:
	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
	ldr	r1, [r2, #4]
	and	r7, r1, #0xff
	cmp	r7, #23			/* relative fixup? */
	beq	fixrel
	cmp	r7, #2			/* absolute fixup? */
	beq	fixabs
	/* ignore unknown type of fixup */
	b	fixnext
fixabs:
	/* absolute fix: set location to (offset) symbol value */
	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
	add	r1, r10, r1		/* r1 <- address of symbol in table */
	ldr	r1, [r1, #4]		/* r1 <- symbol value */
	add	r1, r1, r9		/* r1 <- relocated sym addr */
	b	fixnext
fixrel:
	/* relative fix: increase location by offset */
	ldr	r1, [r0]
	add	r1, r1, r9
fixnext:
	str	r1, [r0]
	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
	cmp	r2, r3
	blo	fixloop
#endif

clear_bss:
#ifndef CONFIG_SPL_BUILD
	ldr	r0, _bss_start_ofs
	ldr	r1, _bss_end_ofs
	mov	r4, r6			/* reloc addr */
	add	r0, r0, r4
	add	r1, r1, r4
	mov	r2, #0x00000000		/* clear			    */

clbss_l:cmp	r0, r1			/* clear loop... */
	bhs	clbss_e			/* if reached end of bss, exit */
	str	r2, [r0]
	add	r0, r0, #4
	b	clbss_l
clbss_e:
#endif

/*
 * We are done. Do not return, instead branch to second part of board
 * initialization, now running from RAM.
 */
	ldr	r0, _board_init_r_ofs
	adr	r1, _start
	add	lr, r0, r1
	add	lr, lr, r9
	/* setup parameters for board_init_r */
	mov	r0, r5		/* gd_t */
	mov	r1, r6		/* dest_addr */
	/* jump to it ... */
	mov	pc, lr

_board_init_r_ofs:
	.word board_init_r - _start

_rel_dyn_start_ofs:
	.word __rel_dyn_start - _start
_rel_dyn_end_ofs:
	.word __rel_dyn_end - _start
_dynsym_start_ofs:
	.word __dynsym_start - _start

/*
 *************************************************************************
 *
 * CPU_init_critical registers
 *
 * setup important registers
 * setup memory timing
 *
 *************************************************************************
 */


cpu_init_crit:
	/*
	 * flush v4 I/D caches
	 */
	mov	r0, #0
	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */

	/*
	 * disable MMU stuff and caches
	 */
	mrc	p15, 0, r0, c1, c0, 0
	bic	r0, r0, #0x00002300	@ clear bits 13, 9:8 (--V- --RS)
	bic	r0, r0, #0x00000087	@ clear bits 7, 2:0 (B--- -CAM)
	orr	r0, r0, #0x00000002	@ set bit 2 (A) Align
	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
	orr	r0, r0, #0x40000000	@ set bit 30 (nF) notFastBus
	mcr	p15, 0, r0, c1, c0, 0


	/*
	 * before relocating, we have to setup RAM timing
	 * because memory timing is board-dependend, you will
	 * find a lowlevel_init.S in your board directory.
	 */
	mov	ip, lr
	bl	lowlevel_init
	mov	lr, ip

	mov	pc, lr


/*
 *************************************************************************
 *
 * Interrupt handling
 *
 *************************************************************************
 */

@
@ IRQ stack frame.
@
#define S_FRAME_SIZE	72

#define S_OLD_R0	68
#define S_PSR		64
#define S_PC		60
#define S_LR		56
#define S_SP		52

#define S_IP		48
#define S_FP		44
#define S_R10		40
#define S_R9		36
#define S_R8		32
#define S_R7		28
#define S_R6		24
#define S_R5		20
#define S_R4		16
#define S_R3		12
#define S_R2		8
#define S_R1		4
#define S_R0		0

#define MODE_SVC 0x13
#define I_BIT	 0x80

/*
 * use bad_save_user_regs for abort/prefetch/undef/swi ...
 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
 */

	.macro	bad_save_user_regs
	sub	sp, sp, #S_FRAME_SIZE
	stmia	sp, {r0 - r12}			@ Calling r0-r12
	ldr	r2, IRQ_STACK_START_IN
	ldmia	r2, {r2 - r3}			@ get pc, cpsr
	add	r0, sp, #S_FRAME_SIZE		@ restore sp_SVC

	add	r5, sp, #S_SP
	mov	r1, lr
	stmia	r5, {r0 - r3}			@ save sp_SVC, lr_SVC, pc, cpsr
	mov	r0, sp
	.endm

	.macro	irq_save_user_regs
	sub	sp, sp, #S_FRAME_SIZE
	stmia	sp, {r0 - r12}			@ Calling r0-r12
	add     r8, sp, #S_PC
	stmdb   r8, {sp, lr}^                   @ Calling SP, LR
	str     lr, [r8, #0]                    @ Save calling PC
	mrs     r6, spsr
	str     r6, [r8, #4]                    @ Save CPSR
	str     r0, [r8, #8]                    @ Save OLD_R0
	mov	r0, sp
	.endm

	.macro	irq_restore_user_regs
	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
	mov	r0, r0
	ldr	lr, [sp, #S_PC]			@ Get PC
	add	sp, sp, #S_FRAME_SIZE
	subs	pc, lr, #4			@ return & move spsr_svc into cpsr
	.endm

	.macro get_bad_stack
	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack

	str	lr, [r13]			@ save caller lr / spsr
	mrs	lr, spsr
	str     lr, [r13, #4]

	mov	r13, #MODE_SVC			@ prepare SVC-Mode
	@ msr	spsr_c, r13
	msr	spsr, r13
	mov	lr, pc
	movs	pc, lr
	.endm

	.macro get_irq_stack			@ setup IRQ stack
	ldr	sp, IRQ_STACK_START
	.endm

	.macro get_fiq_stack			@ setup FIQ stack
	ldr	sp, FIQ_STACK_START
	.endm

/*
 * exception handlers
 */
	.align  5
undefined_instruction:
	get_bad_stack
	bad_save_user_regs
	bl	do_undefined_instruction

	.align	5
software_interrupt:
	get_bad_stack
	bad_save_user_regs
	bl	do_software_interrupt

	.align	5
prefetch_abort:
	get_bad_stack
	bad_save_user_regs
	bl	do_prefetch_abort

	.align	5
data_abort:
	get_bad_stack
	bad_save_user_regs
	bl	do_data_abort

	.align	5
not_used:
	get_bad_stack
	bad_save_user_regs
	bl	do_not_used

#ifdef CONFIG_USE_IRQ

	.align	5
irq:
	get_irq_stack
	irq_save_user_regs
	bl	do_irq
	irq_restore_user_regs

	.align	5
fiq:
	get_fiq_stack
	/* someone ought to write a more effiction fiq_save_user_regs */
	irq_save_user_regs
	bl	do_fiq
	irq_restore_user_regs

#else

	.align	5
irq:
	get_bad_stack
	bad_save_user_regs
	bl	do_irq

	.align	5
fiq:
	get_bad_stack
	bad_save_user_regs
	bl	do_fiq

#endif

	.align	5
.globl reset_cpu
reset_cpu:
	bl	disable_interrupts

	/* Disable watchdog */
	ldr	r1, =pWDTCTL
	mov	r3, #0
	str	r3, [r1]

	/* reset counter */
	ldr	r3, =0x00001984
	str	r3, [r1, #4]

	/* Enable the watchdog */
	mov	r3, #1
	str	r3, [r1]

_loop_forever:
	b	_loop_forever
Commit	Line	Data
f39748ae WD	1	/*
	2	* armboot - Startup Code for ARM920 CPU-core
	3	*
fa82f871 AA	4	* Copyright (c) 2001 Marius Gröger <[email protected]>
fa82f871 AA	5	* Copyright (c) 2002 Alex Züpke <[email protected]>
792a09eb	6	* Copyright (c) 2002 Gary Jennejohn <[email protected]>
f39748ae WD	7	*
	8	* See file CREDITS for list of people who contributed to this
	9	* project.
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	* MA 02111-1307 USA
	25	*/
	26
25ddd1fb	27	#include <asm-offsets.h>
f39748ae WD	28	#include <config.h>
	29	#include <version.h>
	30
f39748ae WD	31	/*
	32	*************************************************************************
	33	*
	34	* Jump vector table as in table 3.1 in [1]
	35	*
	36	*************************************************************************
	37	*/
	38
	39
	40	.globl _start
	41	_start: b reset
	42	ldr pc, _undefined_instruction
	43	ldr pc, _software_interrupt
	44	ldr pc, _prefetch_abort
	45	ldr pc, _data_abort
	46	ldr pc, _not_used
	47	ldr pc, _irq
	48	ldr pc, _fiq
	49
	50	_undefined_instruction: .word undefined_instruction
	51	_software_interrupt: .word software_interrupt
	52	_prefetch_abort: .word prefetch_abort
	53	_data_abort: .word data_abort
	54	_not_used: .word not_used
	55	_irq: .word irq
	56	_fiq: .word fiq
	57
	58	.balignl 16,0xdeadbeef
	59
	60
	61	/*
	62	*************************************************************************
	63	*
	64	* Startup Code (reset vector)
	65	*
	66	* do important init only if we don't start from memory!
	67	* relocate armboot to ram
	68	* setup stack
	69	* jump to second stage
	70	*
	71	*************************************************************************
	72	*/
	73
ec985e94	74	.globl _TEXT_BASE
f39748ae	75	_TEXT_BASE:
14d0a02a	76	.word CONFIG_SYS_TEXT_BASE
f39748ae	77
f39748ae WD	78	/*
f39748ae WD	79	* These are defined in the board-specific linker script.
3336ca60 AA	80	* Subtracting _start from them lets the linker put their
	81	* relative position in the executable instead of leaving
	82	* them null.
f39748ae	83	*/
3336ca60 AA	84	.globl _bss_start_ofs
	85	_bss_start_ofs:
	86	.word __bss_start - _start
f39748ae	87
3336ca60 AA	88	.globl _bss_end_ofs
3336ca60 AA	89	_bss_end_ofs:
44c6e659	90	.word __bss_end__ - _start
f39748ae	91
f326cbba PYC	92	.globl _end_ofs
	93	_end_ofs:
	94	.word _end - _start
	95
f39748ae WD	96	#ifdef CONFIG_USE_IRQ
	97	/* IRQ stack memory (calculated at run-time) */
	98	.globl IRQ_STACK_START
	99	IRQ_STACK_START:
	100	.word 0x0badc0de
	101
	102	/* IRQ stack memory (calculated at run-time) */
	103	.globl FIQ_STACK_START
	104	FIQ_STACK_START:
	105	.word 0x0badc0de
	106	#endif
	107
ec985e94 HS	108	/* IRQ stack memory (calculated at run-time) + 8 bytes */
	109	.globl IRQ_STACK_START_IN
	110	IRQ_STACK_START_IN:
	111	.word 0x0badc0de
	112
ec985e94 HS	113	/*
	114	* the actual reset code
	115	*/
	116
	117	reset:
	118	/*
	119	* set the cpu to SVC32 mode
	120	*/
	121	mrs r0,cpsr
	122	bic r0,r0,#0x1f
	123	orr r0,r0,#0xd3
	124	msr cpsr,r0
	125
	126	#define pWDTCTL 0x80001400 /* Watchdog Timer control register */
16263087	127	#define pINTENC 0x8000050C /* Interrupt-Controller enable clear register */
ec985e94 HS	128	#define pCLKSET 0x80000420 /* clock divisor register */
	129
	130	/* disable watchdog, set watchdog control register to
	131	* all zeros (default reset)
	132	*/
	133	ldr r0, =pWDTCTL
	134	mov r1, #0x0
	135	str r1, [r0]
	136
	137	/*
	138	* mask all IRQs by setting all bits in the INTENC register (default)
	139	*/
	140	mov r1, #0xffffffff
	141	ldr r0, =pINTENC
	142	str r1, [r0]
	143
	144	/* FCLK:HCLK:PCLK = 1:2:2 */
	145	/* default FCLK is 200 MHz, using 14.7456 MHz fin */
	146	ldr r0, =pCLKSET
	147	ldr r1, =0x0004ee39
	148	@ ldr r1, =0x0005ee39 @ 1: 2: 4
	149	str r1, [r0]
	150
	151	/*
	152	* we do sys-critical inits only at reboot,
	153	* not when booting from ram!
	154	*/
	155	#ifndef CONFIG_SKIP_LOWLEVEL_INIT
	156	bl cpu_init_crit
	157	#endif
	158
	159	/* Set stackpointer in internal RAM to call board_init_f */
	160	call_board_init_f:
	161	ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
296cae73	162	bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
ec985e94 HS	163	ldr r0,=0x00000000
	164	bl board_init_f
	165
	166	/------------------------------------------------------------------------------/
	167
	168	/*
	169	* void relocate_code (addr_sp, gd, addr_moni)
	170	*
	171	* This "function" does not return, instead it continues in RAM
	172	* after relocating the monitor code.
	173	*
	174	*/
	175	.globl relocate_code
	176	relocate_code:
	177	mov r4, r0 /* save addr_sp */
	178	mov r5, r1 /* save addr of gd */
	179	mov r6, r2 /* save addr of destination */
ec985e94 HS	180
	181	/* Set up the stack */
	182	stack_setup:
	183	mov sp, r4
	184
	185	adr r0, _start
a1a47d3c	186	cmp r0, r6
76abfa57	187	moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
a1a47d3c	188	beq clear_bss /* skip relocation */
a78fb68f	189	mov r1, r6 /* r1 <- scratch for copy_loop */
3336ca60 AA	190	ldr r3, _bss_start_ofs
3336ca60 AA	191	add r2, r0, r3 /* r2 <- source end address */
ec985e94	192
ec985e94 HS	193	copy_loop:
ec985e94 HS	194	ldmia r0!, {r9-r10} /* copy from source address [r0] */
a78fb68f	195	stmia r1!, {r9-r10} /* copy to target address [r1] */
da90d4ce AA	196	cmp r0, r2 /* until source end address [r2] */
da90d4ce AA	197	blo copy_loop
ec985e94	198
401bb30b	199	#ifndef CONFIG_SPL_BUILD
3336ca60 AA	200	/*
	201	* fix .rel.dyn relocations
	202	*/
	203	ldr r0, _TEXT_BASE /* r0 <- Text base */
a78fb68f	204	sub r9, r6, r0 /* r9 <- relocation offset */
3336ca60 AA	205	ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
	206	add r10, r10, r0 /* r10 <- sym table in FLASH */
	207	ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
	208	add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
	209	ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
	210	add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
ec985e94	211	fixloop:
3336ca60 AA	212	ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
	213	add r0, r0, r9 /* r0 <- location to fix up in RAM */
	214	ldr r1, [r2, #4]
1f52d89f AB	215	and r7, r1, #0xff
1f52d89f AB	216	cmp r7, #23 /* relative fixup? */
3336ca60	217	beq fixrel
1f52d89f	218	cmp r7, #2 /* absolute fixup? */
3336ca60 AA	219	beq fixabs
	220	/* ignore unknown type of fixup */
	221	b fixnext
	222	fixabs:
	223	/* absolute fix: set location to (offset) symbol value */
	224	mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
	225	add r1, r10, r1 /* r1 <- address of symbol in table */
	226	ldr r1, [r1, #4] /* r1 <- symbol value */
3600945b	227	add r1, r1, r9 /* r1 <- relocated sym addr */
3336ca60 AA	228	b fixnext
	229	fixrel:
	230	/* relative fix: increase location by offset */
	231	ldr r1, [r0]
	232	add r1, r1, r9
	233	fixnext:
	234	str r1, [r0]
	235	add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
ec985e94	236	cmp r2, r3
79e63139	237	blo fixloop
ec985e94	238	#endif
ec985e94 HS	239
ec985e94 HS	240	clear_bss:
401bb30b	241	#ifndef CONFIG_SPL_BUILD
3336ca60 AA	242	ldr r0, _bss_start_ofs
3336ca60 AA	243	ldr r1, _bss_end_ofs
a78fb68f	244	mov r4, r6 /* reloc addr */
ec985e94	245	add r0, r0, r4
ec985e94 HS	246	add r1, r1, r4
	247	mov r2, #0x00000000 /* clear */
	248
448217d4 ZH	249	clbss_l:cmp r0, r1 /* clear loop... */
	250	bhs clbss_e /* if reached end of bss, exit */
	251	str r2, [r0]
ec985e94	252	add r0, r0, #4
448217d4 ZH	253	b clbss_l
448217d4 ZH	254	clbss_e:
ec985e94 HS	255	#endif
	256
	257	/*
	258	* We are done. Do not return, instead branch to second part of board
	259	* initialization, now running from RAM.
	260	*/
3336ca60 AA	261	ldr r0, _board_init_r_ofs
	262	adr r1, _start
	263	add lr, r0, r1
	264	add lr, lr, r9
ec985e94 HS	265	/* setup parameters for board_init_r */
ec985e94 HS	266	mov r0, r5 /* gd_t */
a78fb68f	267	mov r1, r6 /* dest_addr */
ec985e94	268	/* jump to it ... */
ec985e94 HS	269	mov pc, lr
ec985e94 HS	270
3336ca60 AA	271	_board_init_r_ofs:
	272	.word board_init_r - _start
	273
	274	_rel_dyn_start_ofs:
	275	.word __rel_dyn_start - _start
	276	_rel_dyn_end_ofs:
	277	.word __rel_dyn_end - _start
	278	_dynsym_start_ofs:
	279	.word __dynsym_start - _start
f39748ae	280
f39748ae WD	281	/*
	282	*************************************************************************
	283	*
	284	* CPU_init_critical registers
	285	*
	286	* setup important registers
	287	* setup memory timing
	288	*
	289	*************************************************************************
	290	*/
	291
	292
	293	cpu_init_crit:
	294	/*
	295	* flush v4 I/D caches
	296	*/
	297	mov r0, #0
	298	mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
	299	mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
	300
	301	/*
	302	* disable MMU stuff and caches
	303	*/
	304	mrc p15, 0, r0, c1, c0, 0
	305	bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
	306	bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
	307	orr r0, r0, #0x00000002 @ set bit 2 (A) Align
	308	orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
	309	orr r0, r0, #0x40000000 @ set bit 30 (nF) notFastBus
	310	mcr p15, 0, r0, c1, c0, 0
	311
	312
	313	/*
	314	* before relocating, we have to setup RAM timing
	315	* because memory timing is board-dependend, you will
400558b5	316	* find a lowlevel_init.S in your board directory.
f39748ae WD	317	*/
f39748ae WD	318	mov ip, lr
400558b5	319	bl lowlevel_init
f39748ae WD	320	mov lr, ip
	321
	322	mov pc, lr
	323
	324
	325	/*
	326	*************************************************************************
	327	*
	328	* Interrupt handling
	329	*
	330	*************************************************************************
	331	*/
	332
	333	@
	334	@ IRQ stack frame.
	335	@
	336	#define S_FRAME_SIZE 72
	337
	338	#define S_OLD_R0 68
	339	#define S_PSR 64
	340	#define S_PC 60
	341	#define S_LR 56
	342	#define S_SP 52
	343
	344	#define S_IP 48
	345	#define S_FP 44
	346	#define S_R10 40
	347	#define S_R9 36
	348	#define S_R8 32
	349	#define S_R7 28
	350	#define S_R6 24
	351	#define S_R5 20
	352	#define S_R4 16
	353	#define S_R3 12
	354	#define S_R2 8
	355	#define S_R1 4
	356	#define S_R0 0
	357
	358	#define MODE_SVC 0x13
	359	#define I_BIT 0x80
	360
	361	/*
	362	* use bad_save_user_regs for abort/prefetch/undef/swi ...
	363	* use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
	364	*/
	365
	366	.macro bad_save_user_regs
	367	sub sp, sp, #S_FRAME_SIZE
	368	stmia sp, {r0 - r12} @ Calling r0-r12
ec985e94	369	ldr r2, IRQ_STACK_START_IN
f39748ae WD	370	ldmia r2, {r2 - r3} @ get pc, cpsr
	371	add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
	372
	373	add r5, sp, #S_SP
	374	mov r1, lr
	375	stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
	376	mov r0, sp
	377	.endm
	378
	379	.macro irq_save_user_regs
	380	sub sp, sp, #S_FRAME_SIZE
	381	stmia sp, {r0 - r12} @ Calling r0-r12
	382	add r8, sp, #S_PC
	383	stmdb r8, {sp, lr}^ @ Calling SP, LR
	384	str lr, [r8, #0] @ Save calling PC
	385	mrs r6, spsr
	386	str r6, [r8, #4] @ Save CPSR
	387	str r0, [r8, #8] @ Save OLD_R0
	388	mov r0, sp
	389	.endm
	390
	391	.macro irq_restore_user_regs
	392	ldmia sp, {r0 - lr}^ @ Calling r0 - lr
	393	mov r0, r0
	394	ldr lr, [sp, #S_PC] @ Get PC
	395	add sp, sp, #S_FRAME_SIZE
	396	subs pc, lr, #4 @ return & move spsr_svc into cpsr
	397	.endm
	398
	399	.macro get_bad_stack
ec985e94	400	ldr r13, IRQ_STACK_START_IN @ setup our mode stack
f39748ae WD	401
	402	str lr, [r13] @ save caller lr / spsr
	403	mrs lr, spsr
	404	str lr, [r13, #4]
	405
	406	mov r13, #MODE_SVC @ prepare SVC-Mode
	407	@ msr spsr_c, r13
	408	msr spsr, r13
	409	mov lr, pc
	410	movs pc, lr
	411	.endm
	412
	413	.macro get_irq_stack @ setup IRQ stack
	414	ldr sp, IRQ_STACK_START
	415	.endm
	416
	417	.macro get_fiq_stack @ setup FIQ stack
	418	ldr sp, FIQ_STACK_START
	419	.endm
	420
	421	/*
	422	* exception handlers
	423	*/
	424	.align 5
	425	undefined_instruction:
	426	get_bad_stack
	427	bad_save_user_regs
53677ef1	428	bl do_undefined_instruction
f39748ae WD	429
	430	.align 5
	431	software_interrupt:
	432	get_bad_stack
	433	bad_save_user_regs
53677ef1	434	bl do_software_interrupt
f39748ae WD	435
	436	.align 5
	437	prefetch_abort:
	438	get_bad_stack
	439	bad_save_user_regs
53677ef1	440	bl do_prefetch_abort
f39748ae WD	441
	442	.align 5
	443	data_abort:
	444	get_bad_stack
	445	bad_save_user_regs
53677ef1	446	bl do_data_abort
f39748ae WD	447
	448	.align 5
	449	not_used:
	450	get_bad_stack
	451	bad_save_user_regs
53677ef1	452	bl do_not_used
f39748ae WD	453
	454	#ifdef CONFIG_USE_IRQ
	455
	456	.align 5
	457	irq:
	458	get_irq_stack
	459	irq_save_user_regs
53677ef1	460	bl do_irq
f39748ae WD	461	irq_restore_user_regs
	462
	463	.align 5
	464	fiq:
	465	get_fiq_stack
	466	/* someone ought to write a more effiction fiq_save_user_regs */
	467	irq_save_user_regs
53677ef1	468	bl do_fiq
f39748ae WD	469	irq_restore_user_regs
	470
	471	#else
	472
	473	.align 5
	474	irq:
	475	get_bad_stack
	476	bad_save_user_regs
53677ef1	477	bl do_irq
f39748ae WD	478
	479	.align 5
	480	fiq:
	481	get_bad_stack
	482	bad_save_user_regs
53677ef1	483	bl do_fiq
f39748ae WD	484
	485	#endif
	486
	487	.align 5
	488	.globl reset_cpu
	489	reset_cpu:
	490	bl disable_interrupts
	491
	492	/* Disable watchdog */
	493	ldr r1, =pWDTCTL
	494	mov r3, #0
	495	str r3, [r1]
	496
	497	/* reset counter */
	498	ldr r3, =0x00001984
	499	str r3, [r1, #4]
	500
	501	/* Enable the watchdog */
	502	mov r3, #1
	503	str r3, [r1]
	504
	505	_loop_forever:
	506	b _loop_forever