[J-u-boot.git] / drivers / pci / pcie_dw_mvebu.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2015 Marvell International Ltd.
 *
 * Copyright (C) 2016 Stefan Roese <[email protected]>
 *
 * Based on:
 *   - drivers/pci/pcie_imx.c
 *   - drivers/pci/pci_mvebu.c
 *   - drivers/pci/pcie_xilinx.c
 */

#include <config.h>
#include <dm.h>
#include <log.h>
#include <pci.h>
#include <time.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm-generic/gpio.h>
#include <linux/delay.h>

DECLARE_GLOBAL_DATA_PTR;

/* PCI Config space registers */
#define PCIE_CONFIG_BAR0		0x10
#define PCIE_LINK_STATUS_REG		0x80
#define PCIE_LINK_STATUS_SPEED_OFF	16
#define PCIE_LINK_STATUS_SPEED_MASK	(0xf << PCIE_LINK_STATUS_SPEED_OFF)
#define PCIE_LINK_STATUS_WIDTH_OFF	20
#define PCIE_LINK_STATUS_WIDTH_MASK	(0xf << PCIE_LINK_STATUS_WIDTH_OFF)

/* Resizable bar capability registers */
#define RESIZABLE_BAR_CAP		0x250
#define RESIZABLE_BAR_CTL0		0x254
#define RESIZABLE_BAR_CTL1		0x258

/* iATU registers */
#define PCIE_ATU_VIEWPORT		0x900
#define PCIE_ATU_REGION_INBOUND		(0x1 << 31)
#define PCIE_ATU_REGION_OUTBOUND	(0x0 << 31)
#define PCIE_ATU_REGION_INDEX1		(0x1 << 0)
#define PCIE_ATU_REGION_INDEX0		(0x0 << 0)
#define PCIE_ATU_CR1			0x904
#define PCIE_ATU_TYPE_MEM		(0x0 << 0)
#define PCIE_ATU_TYPE_IO		(0x2 << 0)
#define PCIE_ATU_TYPE_CFG0		(0x4 << 0)
#define PCIE_ATU_TYPE_CFG1		(0x5 << 0)
#define PCIE_ATU_CR2			0x908
#define PCIE_ATU_ENABLE			(0x1 << 31)
#define PCIE_ATU_BAR_MODE_ENABLE	(0x1 << 30)
#define PCIE_ATU_LOWER_BASE		0x90C
#define PCIE_ATU_UPPER_BASE		0x910
#define PCIE_ATU_LIMIT			0x914
#define PCIE_ATU_LOWER_TARGET		0x918
#define PCIE_ATU_BUS(x)			(((x) & 0xff) << 24)
#define PCIE_ATU_DEV(x)			(((x) & 0x1f) << 19)
#define PCIE_ATU_FUNC(x)		(((x) & 0x7) << 16)
#define PCIE_ATU_UPPER_TARGET		0x91C

#define PCIE_LINK_CAPABILITY		0x7C
#define PCIE_LINK_CTL_2			0xA0
#define TARGET_LINK_SPEED_MASK		0xF
#define LINK_SPEED_GEN_1		0x1
#define LINK_SPEED_GEN_2		0x2
#define LINK_SPEED_GEN_3		0x3

#define PCIE_GEN3_RELATED		0x890
#define GEN3_EQU_DISABLE		(1 << 16)
#define GEN3_ZRXDC_NON_COMP		(1 << 0)

#define PCIE_GEN3_EQU_CTRL		0x8A8
#define GEN3_EQU_EVAL_2MS_DISABLE	(1 << 5)

#define PCIE_ROOT_COMPLEX_MODE_MASK	(0xF << 4)

#define PCIE_LINK_UP_TIMEOUT_MS		100

#define PCIE_GLOBAL_CONTROL		0x8000
#define PCIE_APP_LTSSM_EN		(1 << 2)
#define PCIE_DEVICE_TYPE_OFFSET		(4)
#define PCIE_DEVICE_TYPE_MASK		(0xF)
#define PCIE_DEVICE_TYPE_EP		(0x0) /* Endpoint */
#define PCIE_DEVICE_TYPE_LEP		(0x1) /* Legacy endpoint */
#define PCIE_DEVICE_TYPE_RC		(0x4) /* Root complex */

#define PCIE_GLOBAL_STATUS		0x8008
#define PCIE_GLB_STS_RDLH_LINK_UP	(1 << 1)
#define PCIE_GLB_STS_PHY_LINK_UP	(1 << 9)

#define PCIE_ARCACHE_TRC		0x8050
#define PCIE_AWCACHE_TRC		0x8054
#define ARCACHE_SHAREABLE_CACHEABLE	0x3511
#define AWCACHE_SHAREABLE_CACHEABLE	0x5311

#define LINK_SPEED_GEN_1                0x1
#define LINK_SPEED_GEN_2                0x2
#define LINK_SPEED_GEN_3                0x3

/**
 * struct pcie_dw_mvebu - MVEBU DW PCIe controller state
 *
 * @ctrl_base: The base address of the register space
 * @cfg_base: The base address of the configuration space
 * @cfg_size: The size of the configuration space which is needed
 *            as it gets written into the PCIE_ATU_LIMIT register
 * @first_busno: This driver supports multiple PCIe controllers.
 *               first_busno stores the bus number of the PCIe root-port
 *               number which may vary depending on the PCIe setup
 *               (PEX switches etc).
 */
struct pcie_dw_mvebu {
	void *ctrl_base;
	void *cfg_base;
	fdt_size_t cfg_size;
	int first_busno;

	/* IO and MEM PCI regions */
	int region_count;
	struct pci_region io;
	struct pci_region mem;
};

static int pcie_dw_get_link_speed(const void *regs_base)
{
	return (readl(regs_base + PCIE_LINK_STATUS_REG) &
		PCIE_LINK_STATUS_SPEED_MASK) >> PCIE_LINK_STATUS_SPEED_OFF;
}

static int pcie_dw_get_link_width(const void *regs_base)
{
	return (readl(regs_base + PCIE_LINK_STATUS_REG) &
		PCIE_LINK_STATUS_WIDTH_MASK) >> PCIE_LINK_STATUS_WIDTH_OFF;
}

/**
 * pcie_dw_prog_outbound_atu() - Configure ATU for outbound accesses
 *
 * @pcie: Pointer to the PCI controller state
 * @index: ATU region index
 * @type: ATU accsess type
 * @cpu_addr: the physical address for the translation entry
 * @pci_addr: the pcie bus address for the translation entry
 * @size: the size of the translation entry
 */
static void pcie_dw_prog_outbound_atu(struct pcie_dw_mvebu *pcie, int index,
				      int type, u64 cpu_addr, u64 pci_addr,
				      u32 size)
{
	writel(PCIE_ATU_REGION_OUTBOUND | index,
	       pcie->ctrl_base + PCIE_ATU_VIEWPORT);
	writel(lower_32_bits(cpu_addr), pcie->ctrl_base + PCIE_ATU_LOWER_BASE);
	writel(upper_32_bits(cpu_addr), pcie->ctrl_base + PCIE_ATU_UPPER_BASE);
	writel(lower_32_bits(cpu_addr + size - 1),
	       pcie->ctrl_base + PCIE_ATU_LIMIT);
	writel(lower_32_bits(pci_addr),
	       pcie->ctrl_base + PCIE_ATU_LOWER_TARGET);
	writel(upper_32_bits(pci_addr),
	       pcie->ctrl_base + PCIE_ATU_UPPER_TARGET);
	writel(type, pcie->ctrl_base + PCIE_ATU_CR1);
	writel(PCIE_ATU_ENABLE, pcie->ctrl_base + PCIE_ATU_CR2);
}

/**
 * set_cfg_address() - Configure the PCIe controller config space access
 *
 * @pcie: Pointer to the PCI controller state
 * @d: PCI device to access
 * @where: Offset in the configuration space
 *
 * Configures the PCIe controller to access the configuration space of
 * a specific PCIe device and returns the address to use for this
 * access.
 *
 * Return: Address that can be used to access the configation space
 *         of the requested device / offset
 */
static uintptr_t set_cfg_address(struct pcie_dw_mvebu *pcie,
				 pci_dev_t d, uint where)
{
	uintptr_t va_address;
	u32 atu_type;

	/*
	 * Region #0 is used for Outbound CFG space access.
	 * Direction = Outbound
	 * Region Index = 0
	 */

	if (PCI_BUS(d) == (pcie->first_busno + 1))
		/* For local bus, change TLP Type field to 4. */
		atu_type = PCIE_ATU_TYPE_CFG0;
	else
		/* Otherwise, change TLP Type field to 5. */
		atu_type = PCIE_ATU_TYPE_CFG1;

	if (PCI_BUS(d) == pcie->first_busno) {
		/* Accessing root port configuration space. */
		va_address = (uintptr_t)pcie->ctrl_base;
	} else {
		d = PCI_MASK_BUS(d) | (PCI_BUS(d) - pcie->first_busno);
		pcie_dw_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX0,
					  atu_type, (u64)pcie->cfg_base,
					  d << 8, pcie->cfg_size);
		va_address = (uintptr_t)pcie->cfg_base;
	}

	va_address += where & ~0x3;

	return va_address;
}

/**
 * pcie_dw_addr_valid() - Check for valid bus address
 *
 * @d: The PCI device to access
 * @first_busno: Bus number of the PCIe controller root complex
 *
 * Return 1 (true) if the PCI device can be accessed by this controller.
 *
 * Return: 1 on valid, 0 on invalid
 */
static int pcie_dw_addr_valid(pci_dev_t d, int first_busno)
{
	if ((PCI_BUS(d) == first_busno) && (PCI_DEV(d) > 0))
		return 0;
	if ((PCI_BUS(d) == first_busno + 1) && (PCI_DEV(d) > 0))
		return 0;

	return 1;
}

/**
 * pcie_dw_mvebu_read_config() - Read from configuration space
 *
 * @bus: Pointer to the PCI bus
 * @bdf: Identifies the PCIe device to access
 * @offset: The offset into the device's configuration space
 * @valuep: A pointer at which to store the read value
 * @size: Indicates the size of access to perform
 *
 * Read a value of size @size from offset @offset within the configuration
 * space of the device identified by the bus, device & function numbers in @bdf
 * on the PCI bus @bus.
 *
 * Return: 0 on success
 */
static int pcie_dw_mvebu_read_config(const struct udevice *bus, pci_dev_t bdf,
				     uint offset, ulong *valuep,
				     enum pci_size_t size)
{
	struct pcie_dw_mvebu *pcie = dev_get_priv(bus);
	uintptr_t va_address;
	ulong value;

	debug("PCIE CFG read:  (b,d,f)=(%2d,%2d,%2d) ",
	      PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));

	if (!pcie_dw_addr_valid(bdf, pcie->first_busno)) {
		debug("- out of range\n");
		*valuep = pci_get_ff(size);
		return 0;
	}

	va_address = set_cfg_address(pcie, bdf, offset);

	value = readl(va_address);

	debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value);
	*valuep = pci_conv_32_to_size(value, offset, size);

	if (pcie->region_count > 1)
		pcie_dw_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX0,
					  PCIE_ATU_TYPE_IO, pcie->io.phys_start,
					  pcie->io.bus_start, pcie->io.size);

	return 0;
}

/**
 * pcie_dw_mvebu_write_config() - Write to configuration space
 *
 * @bus: Pointer to the PCI bus
 * @bdf: Identifies the PCIe device to access
 * @offset: The offset into the device's configuration space
 * @value: The value to write
 * @size: Indicates the size of access to perform
 *
 * Write the value @value of size @size from offset @offset within the
 * configuration space of the device identified by the bus, device & function
 * numbers in @bdf on the PCI bus @bus.
 *
 * Return: 0 on success
 */
static int pcie_dw_mvebu_write_config(struct udevice *bus, pci_dev_t bdf,
				      uint offset, ulong value,
				      enum pci_size_t size)
{
	struct pcie_dw_mvebu *pcie = dev_get_priv(bus);
	uintptr_t va_address;
	ulong old;

	debug("PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ",
	      PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
	debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value);

	if (!pcie_dw_addr_valid(bdf, pcie->first_busno)) {
		debug("- out of range\n");
		return 0;
	}

	va_address = set_cfg_address(pcie, bdf, offset);

	old = readl(va_address);
	value = pci_conv_size_to_32(old, value, offset, size);
	writel(value, va_address);

	if (pcie->region_count > 1)
		pcie_dw_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX0,
					  PCIE_ATU_TYPE_IO, pcie->io.phys_start,
					  pcie->io.bus_start, pcie->io.size);

	return 0;
}

/**
 * pcie_dw_configure() - Configure link capabilities and speed
 *
 * @regs_base: A pointer to the PCIe controller registers
 * @cap_speed: The capabilities and speed to configure
 *
 * Configure the link capabilities and speed in the PCIe root complex.
 */
static void pcie_dw_configure(const void *regs_base, u32 cap_speed)
{
	/*
	 * TODO ([email protected], [email protected]):
	 * Need to read the serdes speed from the dts and according to it
	 * configure the PCIe gen
	 */

	/* Set link to GEN 3 */
	clrsetbits_le32(regs_base + PCIE_LINK_CTL_2,
			TARGET_LINK_SPEED_MASK, cap_speed);
	clrsetbits_le32(regs_base + PCIE_LINK_CAPABILITY,
			TARGET_LINK_SPEED_MASK, cap_speed);
	setbits_le32(regs_base + PCIE_GEN3_EQU_CTRL, GEN3_EQU_EVAL_2MS_DISABLE);
}

/**
 * is_link_up() - Return the link state
 *
 * @regs_base: A pointer to the PCIe controller registers
 *
 * Return: 1 (true) for active line and 0 (false) for no link
 */
static int is_link_up(const void *regs_base)
{
	u32 mask = PCIE_GLB_STS_RDLH_LINK_UP | PCIE_GLB_STS_PHY_LINK_UP;
	u32 reg;

	reg = readl(regs_base + PCIE_GLOBAL_STATUS);
	if ((reg & mask) == mask)
		return 1;

	return 0;
}

/**
 * wait_link_up() - Wait for the link to come up
 *
 * @regs_base: A pointer to the PCIe controller registers
 *
 * Return: 1 (true) for active line and 0 (false) for no link (timeout)
 */
static int wait_link_up(const void *regs_base)
{
	unsigned long timeout;

	timeout = get_timer(0) + PCIE_LINK_UP_TIMEOUT_MS;
	while (!is_link_up(regs_base)) {
		if (get_timer(0) > timeout)
			return 0;
	};

	return 1;
}

/**
 * pcie_dw_mvebu_pcie_link_up() - Configure the PCIe root port
 *
 * @regs_base: A pointer to the PCIe controller registers
 * @cap_speed: The capabilities and speed to configure
 *
 * Configure the PCIe controller root complex depending on the
 * requested link capabilities and speed.
 *
 * Return: 1 (true) for active line and 0 (false) for no link
 */
static int pcie_dw_mvebu_pcie_link_up(const void *regs_base, u32 cap_speed)
{
	if (!is_link_up(regs_base)) {
		/* Disable LTSSM state machine to enable configuration */
		clrbits_le32(regs_base + PCIE_GLOBAL_CONTROL,
			     PCIE_APP_LTSSM_EN);
	}

	clrsetbits_le32(regs_base + PCIE_GLOBAL_CONTROL,
			PCIE_DEVICE_TYPE_MASK << PCIE_DEVICE_TYPE_OFFSET,
			PCIE_DEVICE_TYPE_RC << PCIE_DEVICE_TYPE_OFFSET);

	/* Set the PCIe master AXI attributes */
	writel(ARCACHE_SHAREABLE_CACHEABLE, regs_base + PCIE_ARCACHE_TRC);
	writel(AWCACHE_SHAREABLE_CACHEABLE, regs_base + PCIE_AWCACHE_TRC);

	/* DW pre link configurations */
	pcie_dw_configure(regs_base, cap_speed);

	if (!is_link_up(regs_base)) {
		/* Configuration done. Start LTSSM */
		setbits_le32(regs_base + PCIE_GLOBAL_CONTROL,
			     PCIE_APP_LTSSM_EN);
	}

	/* Check that link was established */
	if (!wait_link_up(regs_base))
		return 0;

	/*
	 * Link can be established in Gen 1. still need to wait
	 * till MAC nagaotiation is completed
	 */
	udelay(100);

	return 1;
}

/**
 * pcie_dw_set_host_bars() - Configure the host BARs
 *
 * @regs_base: A pointer to the PCIe controller registers
 *
 * Configure the host BARs of the PCIe controller root port so that
 * PCI(e) devices may access the system memory.
 */
static void pcie_dw_set_host_bars(const void *regs_base)
{
	u32 size = gd->ram_size;
	u64 max_size;
	u32 reg;
	u32 bar0;

	/* Verify the maximal BAR size */
	reg = readl(regs_base + RESIZABLE_BAR_CAP);
	max_size = 1ULL << (5 + (reg + (1 << 4)));

	if (size > max_size) {
		size = max_size;
		printf("Warning: PCIe BARs can't map all DRAM space\n");
	}

	/* Set the BAR base and size towards DDR */
	bar0 = CFG_SYS_SDRAM_BASE & ~0xf;
	bar0 |= PCI_BASE_ADDRESS_MEM_TYPE_32;
	writel(CFG_SYS_SDRAM_BASE, regs_base + PCIE_CONFIG_BAR0);

	reg = ((size >> 20) - 1) << 12;
	writel(size, regs_base + RESIZABLE_BAR_CTL0);
}

/**
 * pcie_dw_mvebu_probe() - Probe the PCIe bus for active link
 *
 * @dev: A pointer to the device being operated on
 *
 * Probe for an active link on the PCIe bus and configure the controller
 * to enable this port.
 *
 * Return: 0 on success, else -ENODEV
 */
static int pcie_dw_mvebu_probe(struct udevice *dev)
{
	struct pcie_dw_mvebu *pcie = dev_get_priv(dev);
	struct udevice *ctlr = pci_get_controller(dev);
	struct pci_controller *hose = dev_get_uclass_priv(ctlr);
#if CONFIG_IS_ENABLED(DM_GPIO)
	struct gpio_desc reset_gpio;

	gpio_request_by_name(dev, "marvell,reset-gpio", 0, &reset_gpio,
			     GPIOD_IS_OUT);
	/*
	 * Issue reset to add-in card trough the dedicated GPIO.
	 * Some boards are connecting the card reset pin to common system
	 * reset wire and others are using separate GPIO port.
	 * In the last case we have to release a reset of the addon card
	 * using this GPIO.
	 */
	if (dm_gpio_is_valid(&reset_gpio)) {
		dm_gpio_set_value(&reset_gpio, 1); /* assert */
		mdelay(200);
		dm_gpio_set_value(&reset_gpio, 0); /* de-assert */
		mdelay(200);
	}
#else
	debug("PCIE Reset on GPIO support is missing\n");
#endif /* DM_GPIO */

	pcie->first_busno = dev_seq(dev);

	/* Don't register host if link is down */
	if (!pcie_dw_mvebu_pcie_link_up(pcie->ctrl_base, LINK_SPEED_GEN_3)) {
		printf("PCIE-%d: Link down\n", dev_seq(dev));
	} else {
		printf("PCIE-%d: Link up (Gen%d-x%d, Bus%d)\n", dev_seq(dev),
		       pcie_dw_get_link_speed(pcie->ctrl_base),
		       pcie_dw_get_link_width(pcie->ctrl_base),
		       hose->first_busno);
	}

	pcie->region_count = hose->region_count - CONFIG_NR_DRAM_BANKS;

	/* Store the IO and MEM windows settings for future use by the ATU */
	if (pcie->region_count > 1) {
		/* IO base */
		pcie->io.phys_start = hose->regions[0].phys_start;
		/* IO_bus_addr */
		pcie->io.bus_start  = hose->regions[0].bus_start;
		/* IO size */
		pcie->io.size       = hose->regions[0].size;
	}

	/* MEM base */
	pcie->mem.phys_start = hose->regions[pcie->region_count - 1].phys_start;
	/* MEM_bus_addr */
	pcie->mem.bus_start  = hose->regions[pcie->region_count - 1].bus_start;
	/* MEM size */
	pcie->mem.size       = hose->regions[pcie->region_count - 1].size;

	pcie_dw_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX1,
				  PCIE_ATU_TYPE_MEM, pcie->mem.phys_start,
				  pcie->mem.bus_start, pcie->mem.size);

	/* Set the CLASS_REV of RC CFG header to PCI_CLASS_BRIDGE_PCI_NORMAL */
	clrsetbits_le32(pcie->ctrl_base + PCI_CLASS_REVISION,
			0xffffff << 8, PCI_CLASS_BRIDGE_PCI_NORMAL << 8);

	pcie_dw_set_host_bars(pcie->ctrl_base);

	return 0;
}

/**
 * pcie_dw_mvebu_of_to_plat() - Translate from DT to device state
 *
 * @dev: A pointer to the device being operated on
 *
 * Translate relevant data from the device tree pertaining to device @dev into
 * state that the driver will later make use of. This state is stored in the
 * device's private data structure.
 *
 * Return: 0 on success, else -EINVAL
 */
static int pcie_dw_mvebu_of_to_plat(struct udevice *dev)
{
	struct pcie_dw_mvebu *pcie = dev_get_priv(dev);

	/* Get the controller base address */
	pcie->ctrl_base = devfdt_get_addr_index_ptr(dev, 0);
	if (!pcie->ctrl_base)
		return -EINVAL;

	/* Get the config space base address and size */
	pcie->cfg_base = devfdt_get_addr_size_index_ptr(dev, 1,
							&pcie->cfg_size);
	if (!pcie->cfg_base)
		return -EINVAL;

	return 0;
}

static const struct dm_pci_ops pcie_dw_mvebu_ops = {
	.read_config	= pcie_dw_mvebu_read_config,
	.write_config	= pcie_dw_mvebu_write_config,
};

static const struct udevice_id pcie_dw_mvebu_ids[] = {
	{ .compatible = "marvell,armada8k-pcie" },
	{ }
};

U_BOOT_DRIVER(pcie_dw_mvebu) = {
	.name			= "pcie_dw_mvebu",
	.id			= UCLASS_PCI,
	.of_match		= pcie_dw_mvebu_ids,
	.ops			= &pcie_dw_mvebu_ops,
	.of_to_plat	= pcie_dw_mvebu_of_to_plat,
	.probe			= pcie_dw_mvebu_probe,
	.priv_auto	= sizeof(struct pcie_dw_mvebu),
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
182ba1a7 SA	2	/*
	3	* Copyright (C) 2015 Marvell International Ltd.
	4	*
	5	* Copyright (C) 2016 Stefan Roese <[email protected]>
	6	*
	7	* Based on:
	8	* - drivers/pci/pcie_imx.c
	9	* - drivers/pci/pci_mvebu.c
	10	* - drivers/pci/pcie_xilinx.c
182ba1a7 SA	11	*/
182ba1a7 SA	12
03de305e	13	#include <config.h>
182ba1a7	14	#include <dm.h>
f7ae49fc	15	#include <log.h>
182ba1a7	16	#include <pci.h>
03de305e	17	#include <time.h>
401d1c4f	18	#include <asm/global_data.h>
182ba1a7	19	#include <asm/io.h>
130b53ec	20	#include <asm-generic/gpio.h>
c05ed00a	21	#include <linux/delay.h>
182ba1a7 SA	22
	23	DECLARE_GLOBAL_DATA_PTR;
	24
	25	/* PCI Config space registers */
	26	#define PCIE_CONFIG_BAR0 0x10
	27	#define PCIE_LINK_STATUS_REG 0x80
	28	#define PCIE_LINK_STATUS_SPEED_OFF 16
	29	#define PCIE_LINK_STATUS_SPEED_MASK (0xf << PCIE_LINK_STATUS_SPEED_OFF)
	30	#define PCIE_LINK_STATUS_WIDTH_OFF 20
	31	#define PCIE_LINK_STATUS_WIDTH_MASK (0xf << PCIE_LINK_STATUS_WIDTH_OFF)
	32
	33	/* Resizable bar capability registers */
	34	#define RESIZABLE_BAR_CAP 0x250
	35	#define RESIZABLE_BAR_CTL0 0x254
	36	#define RESIZABLE_BAR_CTL1 0x258
	37
	38	/* iATU registers */
	39	#define PCIE_ATU_VIEWPORT 0x900
	40	#define PCIE_ATU_REGION_INBOUND (0x1 << 31)
	41	#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
	42	#define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
	43	#define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
	44	#define PCIE_ATU_CR1 0x904
	45	#define PCIE_ATU_TYPE_MEM (0x0 << 0)
	46	#define PCIE_ATU_TYPE_IO (0x2 << 0)
	47	#define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
	48	#define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
	49	#define PCIE_ATU_CR2 0x908
	50	#define PCIE_ATU_ENABLE (0x1 << 31)
	51	#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
	52	#define PCIE_ATU_LOWER_BASE 0x90C
	53	#define PCIE_ATU_UPPER_BASE 0x910
	54	#define PCIE_ATU_LIMIT 0x914
	55	#define PCIE_ATU_LOWER_TARGET 0x918
	56	#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
	57	#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
	58	#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
	59	#define PCIE_ATU_UPPER_TARGET 0x91C
	60
	61	#define PCIE_LINK_CAPABILITY 0x7C
	62	#define PCIE_LINK_CTL_2 0xA0
	63	#define TARGET_LINK_SPEED_MASK 0xF
	64	#define LINK_SPEED_GEN_1 0x1
	65	#define LINK_SPEED_GEN_2 0x2
	66	#define LINK_SPEED_GEN_3 0x3
	67
	68	#define PCIE_GEN3_RELATED 0x890
	69	#define GEN3_EQU_DISABLE (1 << 16)
	70	#define GEN3_ZRXDC_NON_COMP (1 << 0)
	71
	72	#define PCIE_GEN3_EQU_CTRL 0x8A8
	73	#define GEN3_EQU_EVAL_2MS_DISABLE (1 << 5)
	74
	75	#define PCIE_ROOT_COMPLEX_MODE_MASK (0xF << 4)
	76
	77	#define PCIE_LINK_UP_TIMEOUT_MS 100
	78
	79	#define PCIE_GLOBAL_CONTROL 0x8000
	80	#define PCIE_APP_LTSSM_EN (1 << 2)
	81	#define PCIE_DEVICE_TYPE_OFFSET (4)
	82	#define PCIE_DEVICE_TYPE_MASK (0xF)
	83	#define PCIE_DEVICE_TYPE_EP (0x0) /* Endpoint */
	84	#define PCIE_DEVICE_TYPE_LEP (0x1) /* Legacy endpoint */
	85	#define PCIE_DEVICE_TYPE_RC (0x4) /* Root complex */
86
87	#define PCIE_GLOBAL_STATUS 0x8008
88	#define PCIE_GLB_STS_RDLH_LINK_UP (1 << 1)
89	#define PCIE_GLB_STS_PHY_LINK_UP (1 << 9)
90
91	#define PCIE_ARCACHE_TRC 0x8050
92	#define PCIE_AWCACHE_TRC 0x8054
93	#define ARCACHE_SHAREABLE_CACHEABLE 0x3511
94	#define AWCACHE_SHAREABLE_CACHEABLE 0x5311
95
96	#define LINK_SPEED_GEN_1 0x1
97	#define LINK_SPEED_GEN_2 0x2
98	#define LINK_SPEED_GEN_3 0x3
99
100	/**
101	* struct pcie_dw_mvebu - MVEBU DW PCIe controller state
102	*
103	* @ctrl_base: The base address of the register space
104	* @cfg_base: The base address of the configuration space
105	* @cfg_size: The size of the configuration space which is needed
106	* as it gets written into the PCIE_ATU_LIMIT register
107	* @first_busno: This driver supports multiple PCIe controllers.
108	* first_busno stores the bus number of the PCIe root-port
109	* number which may vary depending on the PCIe setup
110	* (PEX switches etc).
111	*/
112	struct pcie_dw_mvebu {
113	void *ctrl_base;
114	void *cfg_base;
115	fdt_size_t cfg_size;
116	int first_busno;
b8478fcd IL	117
b8478fcd IL	118	/* IO and MEM PCI regions */
1fde894e	119	int region_count;
b8478fcd IL	120	struct pci_region io;
b8478fcd IL	121	struct pci_region mem;
182ba1a7 SA	122	};
	123
	124	static int pcie_dw_get_link_speed(const void *regs_base)
	125	{
	126	return (readl(regs_base + PCIE_LINK_STATUS_REG) &
	127	PCIE_LINK_STATUS_SPEED_MASK) >> PCIE_LINK_STATUS_SPEED_OFF;
	128	}
	129
	130	static int pcie_dw_get_link_width(const void *regs_base)
	131	{
	132	return (readl(regs_base + PCIE_LINK_STATUS_REG) &
	133	PCIE_LINK_STATUS_WIDTH_MASK) >> PCIE_LINK_STATUS_WIDTH_OFF;
	134	}
	135
b8478fcd IL	136	/**
	137	* pcie_dw_prog_outbound_atu() - Configure ATU for outbound accesses
	138	*
	139	* @pcie: Pointer to the PCI controller state
	140	* @index: ATU region index
	141	* @type: ATU accsess type
	142	* @cpu_addr: the physical address for the translation entry
	143	* @pci_addr: the pcie bus address for the translation entry
	144	* @size: the size of the translation entry
	145	*/
	146	static void pcie_dw_prog_outbound_atu(struct pcie_dw_mvebu *pcie, int index,
	147	int type, u64 cpu_addr, u64 pci_addr,
	148	u32 size)
	149	{
	150	writel(PCIE_ATU_REGION_OUTBOUND \| index,
	151	pcie->ctrl_base + PCIE_ATU_VIEWPORT);
	152	writel(lower_32_bits(cpu_addr), pcie->ctrl_base + PCIE_ATU_LOWER_BASE);
	153	writel(upper_32_bits(cpu_addr), pcie->ctrl_base + PCIE_ATU_UPPER_BASE);
	154	writel(lower_32_bits(cpu_addr + size - 1),
	155	pcie->ctrl_base + PCIE_ATU_LIMIT);
	156	writel(lower_32_bits(pci_addr),
	157	pcie->ctrl_base + PCIE_ATU_LOWER_TARGET);
	158	writel(upper_32_bits(pci_addr),
	159	pcie->ctrl_base + PCIE_ATU_UPPER_TARGET);
	160	writel(type, pcie->ctrl_base + PCIE_ATU_CR1);
	161	writel(PCIE_ATU_ENABLE, pcie->ctrl_base + PCIE_ATU_CR2);
	162	}
	163
182ba1a7 SA	164	/**
	165	* set_cfg_address() - Configure the PCIe controller config space access
	166	*
	167	* @pcie: Pointer to the PCI controller state
	168	* @d: PCI device to access
	169	* @where: Offset in the configuration space
	170	*
	171	* Configures the PCIe controller to access the configuration space of
	172	* a specific PCIe device and returns the address to use for this
	173	* access.
	174	*
	175	* Return: Address that can be used to access the configation space
	176	* of the requested device / offset
	177	*/
	178	static uintptr_t set_cfg_address(struct pcie_dw_mvebu *pcie,
	179	pci_dev_t d, uint where)
	180	{
	181	uintptr_t va_address;
b8478fcd	182	u32 atu_type;
182ba1a7 SA	183
	184	/*
	185	* Region #0 is used for Outbound CFG space access.
	186	* Direction = Outbound
	187	* Region Index = 0
	188	*/
182ba1a7 SA	189
	190	if (PCI_BUS(d) == (pcie->first_busno + 1))
	191	/* For local bus, change TLP Type field to 4. */
b8478fcd	192	atu_type = PCIE_ATU_TYPE_CFG0;
182ba1a7 SA	193	else
182ba1a7 SA	194	/* Otherwise, change TLP Type field to 5. */
b8478fcd	195	atu_type = PCIE_ATU_TYPE_CFG1;
182ba1a7 SA	196
	197	if (PCI_BUS(d) == pcie->first_busno) {
	198	/* Accessing root port configuration space. */
	199	va_address = (uintptr_t)pcie->ctrl_base;
	200	} else {
3977dcd5	201	d = PCI_MASK_BUS(d) \| (PCI_BUS(d) - pcie->first_busno);
b8478fcd IL	202	pcie_dw_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX0,
	203	atu_type, (u64)pcie->cfg_base,
	204	d << 8, pcie->cfg_size);
182ba1a7 SA	205	va_address = (uintptr_t)pcie->cfg_base;
	206	}
	207
	208	va_address += where & ~0x3;
	209
	210	return va_address;
	211	}
	212
	213	/**
	214	* pcie_dw_addr_valid() - Check for valid bus address
	215	*
	216	* @d: The PCI device to access
	217	* @first_busno: Bus number of the PCIe controller root complex
	218	*
	219	* Return 1 (true) if the PCI device can be accessed by this controller.
	220	*
	221	* Return: 1 on valid, 0 on invalid
	222	*/
	223	static int pcie_dw_addr_valid(pci_dev_t d, int first_busno)
	224	{
	225	if ((PCI_BUS(d) == first_busno) && (PCI_DEV(d) > 0))
	226	return 0;
	227	if ((PCI_BUS(d) == first_busno + 1) && (PCI_DEV(d) > 0))
	228	return 0;
	229
	230	return 1;
	231	}
	232
	233	/**
	234	* pcie_dw_mvebu_read_config() - Read from configuration space
	235	*
	236	* @bus: Pointer to the PCI bus
	237	* @bdf: Identifies the PCIe device to access
	238	* @offset: The offset into the device's configuration space
	239	* @valuep: A pointer at which to store the read value
	240	* @size: Indicates the size of access to perform
	241	*
	242	* Read a value of size @size from offset @offset within the configuration
	243	* space of the device identified by the bus, device & function numbers in @bdf
	244	* on the PCI bus @bus.
	245	*
	246	* Return: 0 on success
	247	*/
c4e72c4a	248	static int pcie_dw_mvebu_read_config(const struct udevice *bus, pci_dev_t bdf,
182ba1a7 SA	249	uint offset, ulong *valuep,
	250	enum pci_size_t size)
	251	{
	252	struct pcie_dw_mvebu *pcie = dev_get_priv(bus);
	253	uintptr_t va_address;
	254	ulong value;
	255
	256	debug("PCIE CFG read: (b,d,f)=(%2d,%2d,%2d) ",
	257	PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
	258
	259	if (!pcie_dw_addr_valid(bdf, pcie->first_busno)) {
	260	debug("- out of range\n");
	261	*valuep = pci_get_ff(size);
	262	return 0;
	263	}
	264
	265	va_address = set_cfg_address(pcie, bdf, offset);
	266
	267	value = readl(va_address);
	268
	269	debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value);
	270	*valuep = pci_conv_32_to_size(value, offset, size);
	271
1fde894e MW	272	if (pcie->region_count > 1)
	273	pcie_dw_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX0,
	274	PCIE_ATU_TYPE_IO, pcie->io.phys_start,
	275	pcie->io.bus_start, pcie->io.size);
b8478fcd	276
182ba1a7 SA	277	return 0;
	278	}
	279
	280	/**
	281	* pcie_dw_mvebu_write_config() - Write to configuration space
	282	*
	283	* @bus: Pointer to the PCI bus
	284	* @bdf: Identifies the PCIe device to access
	285	* @offset: The offset into the device's configuration space
	286	* @value: The value to write
	287	* @size: Indicates the size of access to perform
	288	*
	289	* Write the value @value of size @size from offset @offset within the
	290	* configuration space of the device identified by the bus, device & function
	291	* numbers in @bdf on the PCI bus @bus.
	292	*
	293	* Return: 0 on success
	294	*/
	295	static int pcie_dw_mvebu_write_config(struct udevice *bus, pci_dev_t bdf,
	296	uint offset, ulong value,
	297	enum pci_size_t size)
	298	{
	299	struct pcie_dw_mvebu *pcie = dev_get_priv(bus);
	300	uintptr_t va_address;
	301	ulong old;
	302
	303	debug("PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ",
	304	PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
	305	debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value);
	306
	307	if (!pcie_dw_addr_valid(bdf, pcie->first_busno)) {
	308	debug("- out of range\n");
	309	return 0;
	310	}
	311
	312	va_address = set_cfg_address(pcie, bdf, offset);
	313
	314	old = readl(va_address);
	315	value = pci_conv_size_to_32(old, value, offset, size);
	316	writel(value, va_address);
	317
1fde894e MW	318	if (pcie->region_count > 1)
	319	pcie_dw_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX0,
	320	PCIE_ATU_TYPE_IO, pcie->io.phys_start,
	321	pcie->io.bus_start, pcie->io.size);
b8478fcd	322
182ba1a7 SA	323	return 0;
	324	}
	325
	326	/**
	327	* pcie_dw_configure() - Configure link capabilities and speed
	328	*
	329	* @regs_base: A pointer to the PCIe controller registers
	330	* @cap_speed: The capabilities and speed to configure
	331	*
	332	* Configure the link capabilities and speed in the PCIe root complex.
	333	*/
	334	static void pcie_dw_configure(const void *regs_base, u32 cap_speed)
	335	{
	336	/*
	337	* TODO ([email protected], [email protected]):
	338	* Need to read the serdes speed from the dts and according to it
	339	* configure the PCIe gen
	340	*/
	341
	342	/* Set link to GEN 3 */
	343	clrsetbits_le32(regs_base + PCIE_LINK_CTL_2,
	344	TARGET_LINK_SPEED_MASK, cap_speed);
	345	clrsetbits_le32(regs_base + PCIE_LINK_CAPABILITY,
	346	TARGET_LINK_SPEED_MASK, cap_speed);
	347	setbits_le32(regs_base + PCIE_GEN3_EQU_CTRL, GEN3_EQU_EVAL_2MS_DISABLE);
	348	}
	349
	350	/**
	351	* is_link_up() - Return the link state
	352	*
	353	* @regs_base: A pointer to the PCIe controller registers
	354	*
	355	* Return: 1 (true) for active line and 0 (false) for no link
	356	*/
	357	static int is_link_up(const void *regs_base)
	358	{
	359	u32 mask = PCIE_GLB_STS_RDLH_LINK_UP \| PCIE_GLB_STS_PHY_LINK_UP;
	360	u32 reg;
	361
	362	reg = readl(regs_base + PCIE_GLOBAL_STATUS);
	363	if ((reg & mask) == mask)
	364	return 1;
	365
	366	return 0;
	367	}
	368
	369	/**
	370	* wait_link_up() - Wait for the link to come up
	371	*
	372	* @regs_base: A pointer to the PCIe controller registers
	373	*
	374	* Return: 1 (true) for active line and 0 (false) for no link (timeout)
	375	*/
	376	static int wait_link_up(const void *regs_base)
	377	{
	378	unsigned long timeout;
	379
	380	timeout = get_timer(0) + PCIE_LINK_UP_TIMEOUT_MS;
	381	while (!is_link_up(regs_base)) {
	382	if (get_timer(0) > timeout)
	383	return 0;
	384	};
	385
	386	return 1;
387	}
388
389	/**
390	* pcie_dw_mvebu_pcie_link_up() - Configure the PCIe root port
391	*
392	* @regs_base: A pointer to the PCIe controller registers
393	* @cap_speed: The capabilities and speed to configure
394	*
395	* Configure the PCIe controller root complex depending on the
396	* requested link capabilities and speed.
397	*
398	* Return: 1 (true) for active line and 0 (false) for no link
399	*/
400	static int pcie_dw_mvebu_pcie_link_up(const void *regs_base, u32 cap_speed)
401	{
402	if (!is_link_up(regs_base)) {
403	/* Disable LTSSM state machine to enable configuration */
404	clrbits_le32(regs_base + PCIE_GLOBAL_CONTROL,
405	PCIE_APP_LTSSM_EN);
406	}
407
408	clrsetbits_le32(regs_base + PCIE_GLOBAL_CONTROL,
409	PCIE_DEVICE_TYPE_MASK << PCIE_DEVICE_TYPE_OFFSET,
410	PCIE_DEVICE_TYPE_RC << PCIE_DEVICE_TYPE_OFFSET);
411
412	/* Set the PCIe master AXI attributes */
413	writel(ARCACHE_SHAREABLE_CACHEABLE, regs_base + PCIE_ARCACHE_TRC);
414	writel(AWCACHE_SHAREABLE_CACHEABLE, regs_base + PCIE_AWCACHE_TRC);
415
416	/* DW pre link configurations */
417	pcie_dw_configure(regs_base, cap_speed);
418
419	if (!is_link_up(regs_base)) {
420	/* Configuration done. Start LTSSM */
421	setbits_le32(regs_base + PCIE_GLOBAL_CONTROL,
422	PCIE_APP_LTSSM_EN);
423	}
424
425	/* Check that link was established */
426	if (!wait_link_up(regs_base))
427	return 0;
428
429	/*
430	* Link can be established in Gen 1. still need to wait
431	* till MAC nagaotiation is completed
432	*/
433	udelay(100);
434
435	return 1;
436	}
437
182ba1a7 SA	438	/**
	439	* pcie_dw_set_host_bars() - Configure the host BARs
	440	*
	441	* @regs_base: A pointer to the PCIe controller registers
	442	*
	443	* Configure the host BARs of the PCIe controller root port so that
	444	* PCI(e) devices may access the system memory.
	445	*/
	446	static void pcie_dw_set_host_bars(const void *regs_base)
	447	{
	448	u32 size = gd->ram_size;
	449	u64 max_size;
	450	u32 reg;
	451	u32 bar0;
	452
	453	/* Verify the maximal BAR size */
	454	reg = readl(regs_base + RESIZABLE_BAR_CAP);
	455	max_size = 1ULL << (5 + (reg + (1 << 4)));
	456
	457	if (size > max_size) {
	458	size = max_size;
	459	printf("Warning: PCIe BARs can't map all DRAM space\n");
	460	}
	461
	462	/* Set the BAR base and size towards DDR */
aa6e94de	463	bar0 = CFG_SYS_SDRAM_BASE & ~0xf;
182ba1a7	464	bar0 \|= PCI_BASE_ADDRESS_MEM_TYPE_32;
aa6e94de	465	writel(CFG_SYS_SDRAM_BASE, regs_base + PCIE_CONFIG_BAR0);
182ba1a7 SA	466
	467	reg = ((size >> 20) - 1) << 12;
	468	writel(size, regs_base + RESIZABLE_BAR_CTL0);
	469	}
	470
	471	/**
	472	* pcie_dw_mvebu_probe() - Probe the PCIe bus for active link
	473	*
	474	* @dev: A pointer to the device being operated on
	475	*
	476	* Probe for an active link on the PCIe bus and configure the controller
	477	* to enable this port.
	478	*
	479	* Return: 0 on success, else -ENODEV
	480	*/
	481	static int pcie_dw_mvebu_probe(struct udevice *dev)
	482	{
	483	struct pcie_dw_mvebu *pcie = dev_get_priv(dev);
	484	struct udevice *ctlr = pci_get_controller(dev);
	485	struct pci_controller *hose = dev_get_uclass_priv(ctlr);
bcee8d67	486	#if CONFIG_IS_ENABLED(DM_GPIO)
130b53ec KP	487	struct gpio_desc reset_gpio;
	488
	489	gpio_request_by_name(dev, "marvell,reset-gpio", 0, &reset_gpio,
	490	GPIOD_IS_OUT);
	491	/*
	492	* Issue reset to add-in card trough the dedicated GPIO.
	493	* Some boards are connecting the card reset pin to common system
	494	* reset wire and others are using separate GPIO port.
	495	* In the last case we have to release a reset of the addon card
	496	* using this GPIO.
	497	*/
	498	if (dm_gpio_is_valid(&reset_gpio)) {
6664a0e5 BS	499	dm_gpio_set_value(&reset_gpio, 1); /* assert */
	500	mdelay(200);
	501	dm_gpio_set_value(&reset_gpio, 0); /* de-assert */
130b53ec KP	502	mdelay(200);
	503	}
	504	#else
	505	debug("PCIE Reset on GPIO support is missing\n");
bcee8d67	506	#endif /* DM_GPIO */
182ba1a7	507
8b85dfc6	508	pcie->first_busno = dev_seq(dev);
182ba1a7 SA	509
	510	/* Don't register host if link is down */
	511	if (!pcie_dw_mvebu_pcie_link_up(pcie->ctrl_base, LINK_SPEED_GEN_3)) {
8b85dfc6	512	printf("PCIE-%d: Link down\n", dev_seq(dev));
3f75e0ce	513	} else {
8b85dfc6	514	printf("PCIE-%d: Link up (Gen%d-x%d, Bus%d)\n", dev_seq(dev),
3f75e0ce KP	515	pcie_dw_get_link_speed(pcie->ctrl_base),
	516	pcie_dw_get_link_width(pcie->ctrl_base),
	517	hose->first_busno);
182ba1a7 SA	518	}
182ba1a7 SA	519
1fde894e MW	520	pcie->region_count = hose->region_count - CONFIG_NR_DRAM_BANKS;
1fde894e MW	521
b8478fcd	522	/* Store the IO and MEM windows settings for future use by the ATU */
1fde894e MW	523	if (pcie->region_count > 1) {
	524	/* IO base */
	525	pcie->io.phys_start = hose->regions[0].phys_start;
	526	/* IO_bus_addr */
	527	pcie->io.bus_start = hose->regions[0].bus_start;
	528	/* IO size */
	529	pcie->io.size = hose->regions[0].size;
	530	}
b8478fcd	531
1fde894e MW	532	/* MEM base */
	533	pcie->mem.phys_start = hose->regions[pcie->region_count - 1].phys_start;
	534	/* MEM_bus_addr */
	535	pcie->mem.bus_start = hose->regions[pcie->region_count - 1].bus_start;
	536	/* MEM size */
	537	pcie->mem.size = hose->regions[pcie->region_count - 1].size;
b8478fcd IL	538
	539	pcie_dw_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX1,
	540	PCIE_ATU_TYPE_MEM, pcie->mem.phys_start,
	541	pcie->mem.bus_start, pcie->mem.size);
182ba1a7	542
d7b90409	543	/* Set the CLASS_REV of RC CFG header to PCI_CLASS_BRIDGE_PCI_NORMAL */
182ba1a7	544	clrsetbits_le32(pcie->ctrl_base + PCI_CLASS_REVISION,
d7b90409	545	0xffffff << 8, PCI_CLASS_BRIDGE_PCI_NORMAL << 8);
182ba1a7 SA	546
	547	pcie_dw_set_host_bars(pcie->ctrl_base);
	548
	549	return 0;
	550	}
	551
	552	/**
d1998a9f	553	* pcie_dw_mvebu_of_to_plat() - Translate from DT to device state
182ba1a7 SA	554	*
	555	* @dev: A pointer to the device being operated on
	556	*
	557	* Translate relevant data from the device tree pertaining to device @dev into
	558	* state that the driver will later make use of. This state is stored in the
	559	* device's private data structure.
	560	*
	561	* Return: 0 on success, else -EINVAL
	562	*/
d1998a9f	563	static int pcie_dw_mvebu_of_to_plat(struct udevice *dev)
182ba1a7 SA	564	{
	565	struct pcie_dw_mvebu *pcie = dev_get_priv(dev);
	566
	567	/* Get the controller base address */
320a1938 JJ	568	pcie->ctrl_base = devfdt_get_addr_index_ptr(dev, 0);
320a1938 JJ	569	if (!pcie->ctrl_base)
182ba1a7 SA	570	return -EINVAL;
	571
	572	/* Get the config space base address and size */
842fb5de JJ	573	pcie->cfg_base = devfdt_get_addr_size_index_ptr(dev, 1,
	574	&pcie->cfg_size);
	575	if (!pcie->cfg_base)
182ba1a7 SA	576	return -EINVAL;
	577
	578	return 0;
	579	}
	580
	581	static const struct dm_pci_ops pcie_dw_mvebu_ops = {
	582	.read_config = pcie_dw_mvebu_read_config,
	583	.write_config = pcie_dw_mvebu_write_config,
	584	};
	585
	586	static const struct udevice_id pcie_dw_mvebu_ids[] = {
	587	{ .compatible = "marvell,armada8k-pcie" },
	588	{ }
	589	};
	590
	591	U_BOOT_DRIVER(pcie_dw_mvebu) = {
	592	.name = "pcie_dw_mvebu",
	593	.id = UCLASS_PCI,
	594	.of_match = pcie_dw_mvebu_ids,
	595	.ops = &pcie_dw_mvebu_ops,
d1998a9f	596	.of_to_plat = pcie_dw_mvebu_of_to_plat,
182ba1a7	597	.probe = pcie_dw_mvebu_probe,
41575d8e	598	.priv_auto = sizeof(struct pcie_dw_mvebu),
182ba1a7	599	};