[J-u-boot.git] / include / configs / rsk7264.h

/*
 * Configuation settings for the Renesas RSK2+SH7264 board
 *
 * Copyright (C) 2011 Renesas Electronics Europe Ltd.
 * Copyright (C) 2008 Nobuhiro Iwamatsu
 * Copyright (C) 2008 Renesas Solutions Corp.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __RSK7264_H
#define __RSK7264_H

#undef DEBUG
#define CONFIG_SH2A		1
#define CONFIG_CPU_SH7264	1
#define CONFIG_RSK7264		1

#ifndef _CONFIG_CMD_DEFAULT_H
# include <config_cmd_default.h>
#endif

#define CONFIG_BAUDRATE		115200
#define CONFIG_BOOTARGS		"console=ttySC3,115200"
#define CONFIG_BOOTDELAY	3
#define CONFIG_SYS_BAUDRATE_TABLE	{ CONFIG_BAUDRATE }

#define CONFIG_SYS_LONGHELP	1	/* undef to save memory	*/
#define CONFIG_SYS_CBSIZE	256	/* Buffer size for input from the Console */
#define CONFIG_SYS_PBSIZE	256	/* Buffer size for Console output */
#define CONFIG_SYS_MAXARGS	16	/* max args accepted for monitor commands */

/* Serial */
#define CONFIG_SCIF_CONSOLE	1
#define CONFIG_CONS_SCIF3	1

/* Memory */
/* u-boot relocated to top 256KB of ram */
#define CONFIG_SYS_TEXT_BASE		0x0CFC0000
#define CONFIG_SYS_SDRAM_BASE		0x0C000000
#define CONFIG_SYS_SDRAM_SIZE		(64 * 1024 * 1024)

#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_TEXT_BASE - 0x100000)
#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)
#define CONFIG_SYS_MONITOR_LEN		(128 * 1024)
#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 4*1024*1024)

/* Flash */
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_CFI_WIDTH 	FLASH_CFI_16BIT
#define CONFIG_SYS_FLASH_BASE		0x20000000 /* Non-cached */
#define CONFIG_SYS_MAX_FLASH_BANKS	1
#define CONFIG_SYS_MAX_FLASH_SECT	512

#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_OFFSET	(128 * 1024)
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
#define CONFIG_ENV_SECT_SIZE	(128 * 1024)
#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE

/* Board Clock */
#define CONFIG_SYS_CLK_FREQ	36000000
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CMT_CLK_DIVIDER		32	/* 8 (default), 32, 128 or 512 */
#define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)

/* Network interface */
#define CONFIG_SMC911X
#define CONFIG_SMC911X_16_BIT
#define CONFIG_SMC911X_BASE	0x28000000

#endif	/* __RSK7264_H */
Commit	Line	Data
7fbeb642	1	/*
efa4e1b9	2	* Configuation settings for the Renesas RSK2+SH7264 board
7fbeb642 PE	3	*
	4	* Copyright (C) 2011 Renesas Electronics Europe Ltd.
	5	* Copyright (C) 2008 Nobuhiro Iwamatsu
	6	* Copyright (C) 2008 Renesas Solutions Corp.
	7	*
1a459660	8	* SPDX-License-Identifier: GPL-2.0+
7fbeb642 PE	9	*/
	10
	11	#ifndef __RSK7264_H
	12	#define __RSK7264_H
	13
	14	#undef DEBUG
7fbeb642 PE	15	#define CONFIG_SH2A 1
7fbeb642 PE	16	#define CONFIG_CPU_SH7264 1
efa4e1b9	17	#define CONFIG_RSK7264 1
7fbeb642	18
efa4e1b9 PE	19	#ifndef _CONFIG_CMD_DEFAULT_H
	20	# include <config_cmd_default.h>
	21	#endif
7fbeb642 PE	22
	23	#define CONFIG_BAUDRATE 115200
	24	#define CONFIG_BOOTARGS "console=ttySC3,115200"
	25	#define CONFIG_BOOTDELAY 3
efa4e1b9	26	#define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE }
7fbeb642	27
efa4e1b9	28	#define CONFIG_SYS_LONGHELP 1 /* undef to save memory */
7fbeb642 PE	29	#define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */
	30	#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
	31	#define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */
7fbeb642	32
efa4e1b9	33	/* Serial */
7fbeb642 PE	34	#define CONFIG_SCIF_CONSOLE 1
	35	#define CONFIG_CONS_SCIF3 1
	36
efa4e1b9 PE	37	/* Memory */
	38	/* u-boot relocated to top 256KB of ram */
	39	#define CONFIG_SYS_TEXT_BASE 0x0CFC0000
	40	#define CONFIG_SYS_SDRAM_BASE 0x0C000000
7fbeb642 PE	41	#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
7fbeb642 PE	42
efa4e1b9 PE	43	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
efa4e1b9 PE	44	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000)
7fbeb642	45	#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
efa4e1b9 PE	46	#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
efa4e1b9 PE	47	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 410241024)
7fbeb642	48
efa4e1b9	49	/* Flash */
7fbeb642 PE	50	#define CONFIG_FLASH_CFI_DRIVER
	51	#define CONFIG_SYS_FLASH_CFI
	52	#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
efa4e1b9	53	#define CONFIG_SYS_FLASH_BASE 0x20000000 /* Non-cached */
7fbeb642	54	#define CONFIG_SYS_MAX_FLASH_BANKS 1
efa4e1b9	55	#define CONFIG_SYS_MAX_FLASH_SECT 512
7fbeb642	56
efa4e1b9 PE	57	#define CONFIG_ENV_IS_IN_FLASH 1
	58	#define CONFIG_ENV_OFFSET (128 * 1024)
	59	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
7fbeb642 PE	60	#define CONFIG_ENV_SECT_SIZE (128 * 1024)
7fbeb642 PE	61	#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
7fbeb642 PE	62
7fbeb642 PE	63	/* Board Clock */
117029c5	64	#define CONFIG_SYS_CLK_FREQ 36000000
684a501e NI	65	#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
684a501e NI	66	#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
efa4e1b9	67	#define CMT_CLK_DIVIDER 32 /* 8 (default), 32, 128 or 512 */
8f0960e8	68	#define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
7fbeb642 PE	69
7fbeb642 PE	70	/* Network interface */
7fbeb642 PE	71	#define CONFIG_SMC911X
7fbeb642 PE	72	#define CONFIG_SMC911X_16_BIT
efa4e1b9	73	#define CONFIG_SMC911X_BASE 0x28000000
7fbeb642 PE	74
7fbeb642 PE	75	#endif /* __RSK7264_H */