[J-u-boot.git] / include / configs / mcc200.h

/*
 * (C) Copyright 2006-2008
 * Wolfgang Denk, DENX Software Engineering, [email protected].
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC5200
#define CONFIG_MCC200		1	/* MCC200 board */

/*
 * Valid values for CONFIG_SYS_TEXT_BASE are:
 * 0xFC000000	boot low (standard configuration)
 * 0xFFF00000	boot high
 * 0x00100000	boot from RAM (for testing only)
 */
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE	0xFC000000
#endif

#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33MHz		*/

#define CONFIG_MISC_INIT_R

#define CONFIG_HIGH_BATS	1	/* High BATs supported			*/

/*
 * Serial console configuration
 *
 *  To select console on the one of 8 external UARTs,
 * define CONFIG_QUART_CONSOLE as 1, 2, 3, or 4 for the first Quad UART,
 * or as 5, 6, 7, or 8 for the second Quad UART.
 * COM11, COM12, COM13, COM14 are located on the second Quad UART.
 *
 *  CONFIG_PSC_CONSOLE must be undefined in this case.
 */
#if !defined(CONFIG_PRS200)
/* MCC200 configuration: */
#ifdef CONFIG_CONSOLE_COM12
#define CONFIG_QUART_CONSOLE	6	/* console is on UARTF of QUART2	*/
#else
#define CONFIG_QUART_CONSOLE	8	/* console is on UARTH of QUART2	*/
#endif
#else
/* PRS200 configuration: */
#undef CONFIG_QUART_CONSOLE
#endif /* CONFIG_PRS200 */
/*
 *  To select console on PSC1, define CONFIG_PSC_CONSOLE as 1
 * and undefine CONFIG_QUART_CONSOLE.
 */
#if !defined(CONFIG_PRS200)
/* MCC200 configuration: */
#define CONFIG_PSC_CONSOLE	1	/* PSC1 may be COM */
#define CONFIG_PSC_CONSOLE2	2	/* PSC2 is PSoC */
#else
/* PRS200 configuration: */
#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1		*/
#endif
#define CONFIG_BAUDRATE		115200
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }

#define CONFIG_MII		1

#define CONFIG_DOS_PARTITION

/* USB */
#define CONFIG_USB_OHCI
#define CONFIG_USB_STORAGE
/* automatic software updates (see board/mcc200/auto_update.c) */
#define CONFIG_AUTO_UPDATE 1


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_BEDBUG
#define CONFIG_CMD_FAT
#define CONFIG_CMD_I2C
#define CONFIG_CMD_USB

#undef	CONFIG_CMD_NET
#undef	CONFIG_CMD_NFS

/*
 * Autobooting
 */
#define CONFIG_BOOTDELAY	1	/* autoboot after 1 second */

#define CONFIG_PREBOOT	"echo;"	\
	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#ifdef CONFIG_PRS200
# define CONFIG_SYS__BOARDNAME		"prs200"
# define CONFIG_SYS__LINUX_CONSOLE	"ttyS0"
#else
# define CONFIG_SYS__BOARDNAME		"mcc200"
# define CONFIG_SYS__LINUX_CONSOLE	"ttyEU5"
#endif

/* Network */
#define CONFIG_ETHADDR	00:17:17:ff:00:00
#define CONFIG_IPADDR	10.76.9.29
#define CONFIG_SERVERIP	10.76.9.1

#include <version.h> /* For U-Boot version */

#define CONFIG_EXTRA_ENV_SETTINGS					\
	"ubootver=" U_BOOT_VERSION "\0"					\
	"netdev=eth0\0"							\
	"hostname=" CONFIG_SYS__BOARDNAME "\0"				\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/mtdblock2 "			\
		"rootfstype=cramfs\0"					\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"addcons=setenv bootargs ${bootargs} "				\
		"console=${console},${baudrate} "			\
		"ubootver=${ubootver} board=${board}\0"			\
	"flash_nfs=run nfsargs addip addcons;"				\
		"bootm ${kernel_addr}\0"				\
	"flash_self=run ramargs addip addcons;"				\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"net_nfs=tftp 200000 ${bootfile};"				\
		"run nfsargs addip addcons;bootm\0"			\
	"console=" CONFIG_SYS__LINUX_CONSOLE "\0"				\
	"rootpath=/opt/eldk/ppc_6xx\0"					\
	"bootfile=/tftpboot/" CONFIG_SYS__BOARDNAME "/uImage\0"		\
	"load=tftp 200000 /tftpboot/" CONFIG_SYS__BOARDNAME "/u-boot.bin\0"	\
	"text_base=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"		\
	"kernel_addr=0xFC0C0000\0"					\
	"update=protect off ${text_base} +${filesize};"			\
		"era ${text_base} +${filesize};"			\
		"cp.b 200000 ${text_base} ${filesize}\0"		\
	"unlock=yes\0"							\
	""

#define CONFIG_BOOTCOMMAND	"run flash_self"

#define CONFIG_SYS_HUSH_PARSER		1	/* use "hush" command parser	*/

/*
 * IPB Bus clocking configuration.
 */
#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */

/*
 * I2C configuration
 */
#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
#define CONFIG_SYS_I2C_MODULE		2	/* Select I2C module #1 or #2 */

#define CONFIG_SYS_I2C_SPEED		100000 /* 100 kHz */
#define CONFIG_SYS_I2C_SLAVE		0x7F

/*
 * Flash configuration (8,16 or 32 MB)
 * TEXT base always at 0xFFF00000
 * ENV_ADDR always at  0xFFF40000
 * FLASH_BASE at 0xFC000000 for 64 MB (only 32MB are supported, not enough addr lines!!!)
 *		 0xFE000000 for 32 MB
 *		 0xFF000000 for 16 MB
 *		 0xFF800000 for  8 MB
 */
#define CONFIG_SYS_FLASH_BASE		0xfc000000
#define CONFIG_SYS_FLASH_SIZE		0x04000000

#define CONFIG_SYS_FLASH_CFI				/* The flash is CFI compatible	*/
#define CONFIG_FLASH_CFI_DRIVER			/* Use common CFI driver	*/

#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }

#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/

#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
#define CONFIG_SYS_FLASH_PROTECTION	1	/* hardware flash protection		*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
#define CONFIG_SYS_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash	*/

#define CONFIG_ENV_IS_IN_FLASH	1	/* use FLASH for environment vars	*/

#define CONFIG_ENV_SECT_SIZE	0x40000	/* size of one complete sector	*/
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/

/* Address and size of Redundant Environment Sector	*/
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)

#define CONFIG_ENV_OVERWRITE	1	/* allow modification of vendor params */

#if CONFIG_SYS_TEXT_BASE == CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_LOWBOOT	1
#endif

/*
 * Memory map
 */
#define CONFIG_SYS_MBAR		0xf0000000
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_DEFAULT_MBAR	0x80000000

/* Use SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE	/* Size of used area in DPRAM */


#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#   define CONFIG_SYS_RAMBOOT		1
#endif

#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#define CONFIG_SYS_MALLOC_LEN		(512 << 10)	/* Reserve 512 kB for malloc()	*/
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*
 * Ethernet configuration
 */
/* #define CONFIG_MPC5xxx_FEC	1 */
/* #define CONFIG_MPC5xxx_FEC_MII100 */
/*
 * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
 */
/* #define CONFIG_MPC5xxx_FEC_MII10 */
#define CONFIG_PHY_ADDR		1

/*
 * LCD Splash Screen
 */
#if !defined(CONFIG_PRS200)
#define CONFIG_LCD		1
#define CONFIG_PROGRESSBAR 1
#endif

#if defined(CONFIG_LCD)
#define CONFIG_SPLASH_SCREEN	1
#define CONFIG_SYS_CONSOLE_IS_IN_ENV	1
#define LCD_BPP			LCD_MONOCHROME
#endif

/*
 * GPIO configuration
 */
/* 0x10000004 = 32MB SDRAM */
/* 0x90000004 = 64MB SDRAM */
#if defined(CONFIG_LCD)
/* set PSC2 in UART mode */
#define CONFIG_SYS_GPS_PORT_CONFIG	0x00000044
#else
#define CONFIG_SYS_GPS_PORT_CONFIG	0x00000004
#endif

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	*/
#else
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size	*/
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size	*/
#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/

#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */

#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs			*/
#if defined(CONFIG_CMD_KGDB)
#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
#endif

/*
 * Various low-level settings
 */
#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
#define CONFIG_SYS_HID0_FINAL		HID0_ICE

#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_BOOTCS_CFG		0x0004fb00
#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE

/* Quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */
#define CONFIG_SYS_CS2_START		0x80000000
#define CONFIG_SYS_CS2_SIZE		0x00001000
#define CONFIG_SYS_CS2_CFG		0x1d300

/* Second Quad UART @0x80010000 */
#define CONFIG_SYS_CS1_START		0x80010000
#define CONFIG_SYS_CS1_SIZE		0x00001000
#define CONFIG_SYS_CS1_CFG		0x1d300

/* Leica - build revision resistors */
/*
#define CONFIG_SYS_CS3_START		0x80020000
#define CONFIG_SYS_CS3_SIZE		0x00000004
#define CONFIG_SYS_CS3_CFG		0x1d300
*/

/*
 *  Select one of quarts as a default
 * console. If undefined - PSC console
 * wil be default
 */
#define CONFIG_SYS_CS_BURST		0x00000000
#define CONFIG_SYS_CS_DEADCYCLE	0x33333333

#define CONFIG_SYS_RESET_ADDRESS	0xff000000

/*
 * QUART Expanders support
 */
#if defined(CONFIG_QUART_CONSOLE)
/*
 * We'll use NS16550 chip routines,
 */
#define CONFIG_SYS_NS16550		1
#define CONFIG_SYS_NS16550_SERIAL	1
#define CONFIG_CONS_INDEX	1
/*
 *  To achieve necessary offset on SC16C554
 * A0-A2 (register select) pins with NS16550
 * functions (in struct NS16550), REG_SIZE
 * should be 4, because A0-A2 pins are connected
 * to DA2-DA4 address bus lines.
 */
#define CONFIG_SYS_NS16550_REG_SIZE	4
/*
 * LocalPlus Bus already inited in cpu_init_f(),
 * so can work with QUART's chip selects.
 * One of four SC16C554 UARTs is selected with
 * A3-A4 (DA5-DA6) lines.
 */
#if (CONFIG_QUART_CONSOLE > 0) && (CONFIG_QUART_CONSOLE < 5) && !defined(CONFIG_PRS200)
#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CS2_START | (CONFIG_QUART_CONSOLE - 1)<<5)
#elif (CONFIG_QUART_CONSOLE > 4) && (CONFIG_QUART_CONSOLE < 9)
#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CS1_START | (CONFIG_QUART_CONSOLE - 5)<<5)
#else
#error "Wrong QUART expander number."
#endif

/*
 * SC16C554 chip's external crystal oscillator frequency
 * is 7.3728 MHz
 */
#define CONFIG_SYS_NS16550_CLK		7372800
#endif /* CONFIG_QUART_CONSOLE */
/*-----------------------------------------------------------------------
 * USB stuff
 *-----------------------------------------------------------------------
 */
#define CONFIG_USB_CLOCK	0x0001BBBB
#define CONFIG_USB_CONFIG	0x00005000

#define CONFIG_AUTOBOOT_KEYED		/* use key strings to stop autoboot	*/
#define CONFIG_AUTOBOOT_STOP_STR	"432"
#define CONFIG_SILENT_CONSOLE	1

#endif /* __CONFIG_H */
Commit	Line	Data
86ea5f93	1	/*
a99715b8	2	* (C) Copyright 2006-2008
86ea5f93 WD	3	* Wolfgang Denk, DENX Software Engineering, [email protected].
86ea5f93 WD	4	*
3765b3e7	5	* SPDX-License-Identifier: GPL-2.0+
86ea5f93 WD	6	*/
	7
	8	#ifndef __CONFIG_H
	9	#define __CONFIG_H
	10
	11	/*
	12	* High Level Configuration Options
	13	* (easy to change)
	14	*/
	15
	16	#define CONFIG_MPC5200
b2a6dfe4	17	#define CONFIG_MCC200 1 /* MCC200 board */
86ea5f93	18
2ae18241 WD	19	/*
	20	* Valid values for CONFIG_SYS_TEXT_BASE are:
	21	* 0xFC000000 boot low (standard configuration)
	22	* 0xFFF00000 boot high
	23	* 0x00100000 boot from RAM (for testing only)
	24	*/
	25	#ifndef CONFIG_SYS_TEXT_BASE
	26	#define CONFIG_SYS_TEXT_BASE 0xFC000000
	27	#endif
	28
6d0f6bcf	29	#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */
86ea5f93 WD	30
	31	#define CONFIG_MISC_INIT_R
	32
31d82672 BB	33	#define CONFIG_HIGH_BATS 1 /* High BATs supported */
31d82672 BB	34
86ea5f93 WD	35	/*
86ea5f93 WD	36	* Serial console configuration
87791f3b WD	37	*
	38	* To select console on the one of 8 external UARTs,
	39	* define CONFIG_QUART_CONSOLE as 1, 2, 3, or 4 for the first Quad UART,
	40	* or as 5, 6, 7, or 8 for the second Quad UART.
463764c8	41	* COM11, COM12, COM13, COM14 are located on the second Quad UART.
87791f3b WD	42	*
	43	* CONFIG_PSC_CONSOLE must be undefined in this case.
	44	*/
ed1cf845 WD	45	#if !defined(CONFIG_PRS200)
ed1cf845 WD	46	/* MCC200 configuration: */
463764c8 WD	47	#ifdef CONFIG_CONSOLE_COM12
	48	#define CONFIG_QUART_CONSOLE 6 /* console is on UARTF of QUART2 */
	49	#else
	50	#define CONFIG_QUART_CONSOLE 8 /* console is on UARTH of QUART2 */
	51	#endif
ed1cf845 WD	52	#else
	53	/* PRS200 configuration: */
	54	#undef CONFIG_QUART_CONSOLE
	55	#endif /* CONFIG_PRS200 */
87791f3b WD	56	/*
	57	* To select console on PSC1, define CONFIG_PSC_CONSOLE as 1
	58	* and undefine CONFIG_QUART_CONSOLE.
86ea5f93	59	*/
ed1cf845 WD	60	#if !defined(CONFIG_PRS200)
ed1cf845 WD	61	/* MCC200 configuration: */
0fd30252 WD	62	#define CONFIG_PSC_CONSOLE 1 /* PSC1 may be COM */
0fd30252 WD	63	#define CONFIG_PSC_CONSOLE2 2 /* PSC2 is PSoC */
ed1cf845 WD	64	#else
	65	/* PRS200 configuration: */
	66	#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
	67	#endif
86ea5f93	68	#define CONFIG_BAUDRATE 115200
6d0f6bcf	69	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
86ea5f93	70
86ea5f93	71	#define CONFIG_MII 1
86ea5f93	72
86ea5f93 WD	73	#define CONFIG_DOS_PARTITION
	74
	75	/* USB */
86ea5f93	76	#define CONFIG_USB_OHCI
86ea5f93	77	#define CONFIG_USB_STORAGE
cdb97a66 AS	78	/* automatic software updates (see board/mcc200/auto_update.c) */
cdb97a66 AS	79	#define CONFIG_AUTO_UPDATE 1
86ea5f93	80
5dc11a51	81
7f5c0157 JL	82	/*
	83	* BOOTP options
	84	*/
	85	#define CONFIG_BOOTP_BOOTFILESIZE
	86	#define CONFIG_BOOTP_BOOTPATH
	87	#define CONFIG_BOOTP_GATEWAY
	88	#define CONFIG_BOOTP_HOSTNAME
	89
	90
86ea5f93	91	/*
5dc11a51	92	* Command line configuration.
86ea5f93	93	*/
5dc11a51 JL	94	#include <config_cmd_default.h>
	95
	96	#define CONFIG_CMD_BEDBUG
	97	#define CONFIG_CMD_FAT
	98	#define CONFIG_CMD_I2C
	99	#define CONFIG_CMD_USB
86ea5f93	100
a4d2636f	101	#undef CONFIG_CMD_NET
085ecde1	102	#undef CONFIG_CMD_NFS
86ea5f93 WD	103
	104	/*
	105	* Autobooting
	106	*/
a4d2636f	107	#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */
86ea5f93 WD	108
86ea5f93 WD	109	#define CONFIG_PREBOOT "echo;" \
32bf3d14	110	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
86ea5f93 WD	111	"echo"
	112
	113	#undef CONFIG_BOOTARGS
	114
ed1cf845	115	#ifdef CONFIG_PRS200
6d0f6bcf JCPV	116	# define CONFIG_SYS__BOARDNAME "prs200"
6d0f6bcf JCPV	117	# define CONFIG_SYS__LINUX_CONSOLE "ttyS0"
ed1cf845	118	#else
6d0f6bcf JCPV	119	# define CONFIG_SYS__BOARDNAME "mcc200"
6d0f6bcf JCPV	120	# define CONFIG_SYS__LINUX_CONSOLE "ttyEU5"
ed1cf845 WD	121	#endif
ed1cf845 WD	122
a4d2636f WD	123	/* Network */
	124	#define CONFIG_ETHADDR 00:17:17:ff:00:00
	125	#define CONFIG_IPADDR 10.76.9.29
	126	#define CONFIG_SERVERIP 10.76.9.1
	127
	128	#include <version.h> /* For U-Boot version */
	129
ed1cf845	130	#define CONFIG_EXTRA_ENV_SETTINGS \
a4d2636f	131	"ubootver=" U_BOOT_VERSION "\0" \
86ea5f93	132	"netdev=eth0\0" \
5368c55d	133	"hostname=" CONFIG_SYS__BOARDNAME "\0" \
86ea5f93 WD	134	"nfsargs=setenv bootargs root=/dev/nfs rw " \
86ea5f93 WD	135	"nfsroot=${serverip}:${rootpath}\0" \
a4d2636f WD	136	"ramargs=setenv bootargs root=/dev/mtdblock2 " \
a4d2636f WD	137	"rootfstype=cramfs\0" \
86ea5f93 WD	138	"addip=setenv bootargs ${bootargs} " \
	139	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	140	":${hostname}:${netdev}:off panic=1\0" \
113f64e0	141	"addcons=setenv bootargs ${bootargs} " \
a99715b8 DZ	142	"console=${console},${baudrate} " \
a99715b8 DZ	143	"ubootver=${ubootver} board=${board}\0" \
ed1cf845	144	"flash_nfs=run nfsargs addip addcons;" \
86ea5f93	145	"bootm ${kernel_addr}\0" \
ed1cf845	146	"flash_self=run ramargs addip addcons;" \
86ea5f93	147	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
ed1cf845 WD	148	"net_nfs=tftp 200000 ${bootfile};" \
ed1cf845 WD	149	"run nfsargs addip addcons;bootm\0" \
6d0f6bcf	150	"console=" CONFIG_SYS__LINUX_CONSOLE "\0" \
82f2e33a	151	"rootpath=/opt/eldk/ppc_6xx\0" \
6d0f6bcf JCPV	152	"bootfile=/tftpboot/" CONFIG_SYS__BOARDNAME "/uImage\0" \
6d0f6bcf JCPV	153	"load=tftp 200000 /tftpboot/" CONFIG_SYS__BOARDNAME "/u-boot.bin\0" \
5368c55d	154	"text_base=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
a4d2636f	155	"kernel_addr=0xFC0C0000\0" \
ed1cf845 WD	156	"update=protect off ${text_base} +${filesize};" \
	157	"era ${text_base} +${filesize};" \
	158	"cp.b 200000 ${text_base} ${filesize}\0" \
58ad4978	159	"unlock=yes\0" \
86ea5f93 WD	160	""
	161
	162	#define CONFIG_BOOTCOMMAND "run flash_self"
	163
6d0f6bcf	164	#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */
82f2e33a	165
86ea5f93 WD	166	/*
	167	* IPB Bus clocking configuration.
	168	*/
6d0f6bcf	169	#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
86ea5f93	170
86ea5f93 WD	171	/*
	172	* I2C configuration
	173	*/
	174	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
6d0f6bcf	175	#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
86ea5f93	176
6d0f6bcf JCPV	177	#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
6d0f6bcf JCPV	178	#define CONFIG_SYS_I2C_SLAVE 0x7F
86ea5f93	179
86ea5f93 WD	180	/*
	181	* Flash configuration (8,16 or 32 MB)
	182	* TEXT base always at 0xFFF00000
	183	* ENV_ADDR always at 0xFFF40000
58ad4978	184	* FLASH_BASE at 0xFC000000 for 64 MB (only 32MB are supported, not enough addr lines!!!)
360b4103 WD	185	* 0xFE000000 for 32 MB
	186	* 0xFF000000 for 16 MB
	187	* 0xFF800000 for 8 MB
86ea5f93	188	*/
6d0f6bcf JCPV	189	#define CONFIG_SYS_FLASH_BASE 0xfc000000
6d0f6bcf JCPV	190	#define CONFIG_SYS_FLASH_SIZE 0x04000000
86ea5f93	191
6d0f6bcf	192	#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
00b1883a	193	#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
86ea5f93	194
6d0f6bcf	195	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
86ea5f93	196
6d0f6bcf JCPV	197	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
6d0f6bcf JCPV	198	#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
86ea5f93	199
6d0f6bcf JCPV	200	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
6d0f6bcf JCPV	201	#define CONFIG_SYS_FLASH_PROTECTION 1 /* hardware flash protection */
86ea5f93	202
6d0f6bcf JCPV	203	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	204	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
86ea5f93	205
6d0f6bcf JCPV	206	#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
6d0f6bcf JCPV	207	#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
58ad4978	208
5a1aceb0	209	#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
58ad4978	210
0e8d1586	211	#define CONFIG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
6d0f6bcf	212	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
0e8d1586	213	#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
58ad4978 SR	214
58ad4978 SR	215	/* Address and size of Redundant Environment Sector */
0e8d1586 JCPV	216	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
0e8d1586 JCPV	217	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
58ad4978 SR	218
58ad4978 SR	219	#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */
86ea5f93	220
14d0a02a	221	#if CONFIG_SYS_TEXT_BASE == CONFIG_SYS_FLASH_BASE
6d0f6bcf	222	#define CONFIG_SYS_LOWBOOT 1
f149d864 WD	223	#endif
f149d864 WD	224
86ea5f93 WD	225	/*
	226	* Memory map
	227	*/
6d0f6bcf JCPV	228	#define CONFIG_SYS_MBAR 0xf0000000
	229	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	230	#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
86ea5f93 WD	231
86ea5f93 WD	232	/* Use SRAM until RAM will be available */
6d0f6bcf	233	#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
553f0982	234	#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
86ea5f93 WD	235
86ea5f93 WD	236
25ddd1fb	237	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	238	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
86ea5f93	239
14d0a02a	240	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
6d0f6bcf JCPV	241	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
6d0f6bcf JCPV	242	# define CONFIG_SYS_RAMBOOT 1
86ea5f93 WD	243	#endif
86ea5f93 WD	244
6d0f6bcf JCPV	245	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	246	#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */
	247	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
86ea5f93 WD	248
	249	/*
	250	* Ethernet configuration
	251	*/
86321fc1 BW	252	/* #define CONFIG_MPC5xxx_FEC 1 */
86321fc1 BW	253	/* #define CONFIG_MPC5xxx_FEC_MII100 */
86ea5f93	254	/*
86321fc1	255	* Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
86ea5f93	256	*/
86321fc1	257	/* #define CONFIG_MPC5xxx_FEC_MII10 */
58ad4978	258	#define CONFIG_PHY_ADDR 1
86ea5f93	259
e8143e72 WD	260	/*
	261	* LCD Splash Screen
	262	*/
360b4103	263	#if !defined(CONFIG_PRS200)
e8143e72	264	#define CONFIG_LCD 1
638dd145	265	#define CONFIG_PROGRESSBAR 1
360b4103 WD	266	#endif
360b4103 WD	267
e8143e72 WD	268	#if defined(CONFIG_LCD)
e8143e72 WD	269	#define CONFIG_SPLASH_SCREEN 1
6d0f6bcf	270	#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
360b4103	271	#define LCD_BPP LCD_MONOCHROME
e8143e72 WD	272	#endif
e8143e72 WD	273
86ea5f93 WD	274	/*
	275	* GPIO configuration
	276	*/
bfc81252 WD	277	/* 0x10000004 = 32MB SDRAM */
bfc81252 WD	278	/* 0x90000004 = 64MB SDRAM */
e8143e72 WD	279	#if defined(CONFIG_LCD)
e8143e72 WD	280	/* set PSC2 in UART mode */
6d0f6bcf	281	#define CONFIG_SYS_GPS_PORT_CONFIG 0x00000044
e8143e72	282	#else
6d0f6bcf	283	#define CONFIG_SYS_GPS_PORT_CONFIG 0x00000004
e8143e72	284	#endif
86ea5f93 WD	285
	286	/*
	287	* Miscellaneous configurable options
	288	*/
6d0f6bcf	289	#define CONFIG_SYS_LONGHELP /* undef to save memory */
5dc11a51	290	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	291	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
86ea5f93	292	#else
6d0f6bcf	293	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
86ea5f93	294	#endif
6d0f6bcf JCPV	295	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	296	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	297	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
86ea5f93	298
6d0f6bcf JCPV	299	#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
6d0f6bcf JCPV	300	#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
86ea5f93	301
6d0f6bcf	302	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
86ea5f93	303
6d0f6bcf	304	#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
5dc11a51	305	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	306	# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
5dc11a51 JL	307	#endif
5dc11a51 JL	308
86ea5f93 WD	309	/*
	310	* Various low-level settings
	311	*/
6d0f6bcf JCPV	312	#define CONFIG_SYS_HID0_INIT HID0_ICE \| HID0_ICFI
6d0f6bcf JCPV	313	#define CONFIG_SYS_HID0_FINAL HID0_ICE
86ea5f93	314
6d0f6bcf JCPV	315	#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
	316	#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
	317	#define CONFIG_SYS_BOOTCS_CFG 0x0004fb00
	318	#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
	319	#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
86ea5f93	320
05d8dce9	321	/* Quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */
6d0f6bcf JCPV	322	#define CONFIG_SYS_CS2_START 0x80000000
	323	#define CONFIG_SYS_CS2_SIZE 0x00001000
	324	#define CONFIG_SYS_CS2_CFG 0x1d300
05d8dce9	325
a874c8c6	326	/* Second Quad UART @0x80010000 */
6d0f6bcf JCPV	327	#define CONFIG_SYS_CS1_START 0x80010000
	328	#define CONFIG_SYS_CS1_SIZE 0x00001000
	329	#define CONFIG_SYS_CS1_CFG 0x1d300
a874c8c6	330
a4d2636f WD	331	/* Leica - build revision resistors */
a4d2636f WD	332	/*
6d0f6bcf JCPV	333	#define CONFIG_SYS_CS3_START 0x80020000
	334	#define CONFIG_SYS_CS3_SIZE 0x00000004
	335	#define CONFIG_SYS_CS3_CFG 0x1d300
a4d2636f WD	336	*/
a4d2636f WD	337
87791f3b WD	338	/*
	339	* Select one of quarts as a default
	340	* console. If undefined - PSC console
	341	* wil be default
	342	*/
6d0f6bcf JCPV	343	#define CONFIG_SYS_CS_BURST 0x00000000
6d0f6bcf JCPV	344	#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
86ea5f93	345
6d0f6bcf	346	#define CONFIG_SYS_RESET_ADDRESS 0xff000000
86ea5f93	347
87791f3b WD	348	/*
	349	* QUART Expanders support
	350	*/
	351	#if defined(CONFIG_QUART_CONSOLE)
	352	/*
	353	* We'll use NS16550 chip routines,
	354	*/
6d0f6bcf JCPV	355	#define CONFIG_SYS_NS16550 1
6d0f6bcf JCPV	356	#define CONFIG_SYS_NS16550_SERIAL 1
87791f3b WD	357	#define CONFIG_CONS_INDEX 1
	358	/*
	359	* To achieve necessary offset on SC16C554
	360	* A0-A2 (register select) pins with NS16550
	361	* functions (in struct NS16550), REG_SIZE
	362	* should be 4, because A0-A2 pins are connected
	363	* to DA2-DA4 address bus lines.
	364	*/
6d0f6bcf	365	#define CONFIG_SYS_NS16550_REG_SIZE 4
87791f3b WD	366	/*
	367	* LocalPlus Bus already inited in cpu_init_f(),
	368	* so can work with QUART's chip selects.
	369	* One of four SC16C554 UARTs is selected with
	370	* A3-A4 (DA5-DA6) lines.
	371	*/
ed1cf845	372	#if (CONFIG_QUART_CONSOLE > 0) && (CONFIG_QUART_CONSOLE < 5) && !defined(CONFIG_PRS200)
6d0f6bcf	373	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CS2_START \| (CONFIG_QUART_CONSOLE - 1)<<5)
87791f3b	374	#elif (CONFIG_QUART_CONSOLE > 4) && (CONFIG_QUART_CONSOLE < 9)
6d0f6bcf	375	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CS1_START \| (CONFIG_QUART_CONSOLE - 5)<<5)
efd988eb	376	#else
87791f3b WD	377	#error "Wrong QUART expander number."
	378	#endif
	379
	380	/*
	381	* SC16C554 chip's external crystal oscillator frequency
	382	* is 7.3728 MHz
	383	*/
6d0f6bcf	384	#define CONFIG_SYS_NS16550_CLK 7372800
87791f3b	385	#endif /* CONFIG_QUART_CONSOLE */
86ea5f93 WD	386	/*-----------------------------------------------------------------------
	387	* USB stuff
	388	*-----------------------------------------------------------------------
	389	*/
	390	#define CONFIG_USB_CLOCK 0x0001BBBB
	391	#define CONFIG_USB_CONFIG 0x00005000
	392
a4d2636f WD	393	#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */
	394	#define CONFIG_AUTOBOOT_STOP_STR "432"
	395	#define CONFIG_SILENT_CONSOLE 1
	396
86ea5f93	397	#endif /* __CONFIG_H */