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c2042f59 | 1 | /* |
2 | * Configuation settings for the Renesas Solutions Migo-R board | |
3 | * | |
4 | * Copyright (C) 2007 Nobuhiro Iwamatsu <[email protected]> | |
5 | * | |
1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
c2042f59 | 7 | */ |
8 | ||
9 | #ifndef __MIGO_R_H | |
10 | #define __MIGO_R_H | |
11 | ||
12 | #undef DEBUG | |
c2042f59 | 13 | #define CONFIG_CPU_SH7722 1 |
14 | #define CONFIG_MIGO_R 1 | |
15 | ||
16 | #define CONFIG_CMD_LOADB | |
17 | #define CONFIG_CMD_LOADS | |
18 | #define CONFIG_CMD_FLASH | |
19 | #define CONFIG_CMD_MEMORY | |
20 | #define CONFIG_CMD_NET | |
21 | #define CONFIG_CMD_PING | |
22 | #define CONFIG_CMD_NFS | |
c2042f59 | 23 | #define CONFIG_CMD_SDRAM |
bdab39d3 | 24 | #define CONFIG_CMD_SAVEENV |
c2042f59 | 25 | |
26 | #define CONFIG_BAUDRATE 115200 | |
27 | #define CONFIG_BOOTDELAY 3 | |
28 | #define CONFIG_BOOTARGS "console=ttySC0,115200 root=1f01" | |
c2042f59 | 29 | |
30 | #define CONFIG_VERSION_VARIABLE | |
31 | #undef CONFIG_SHOW_BOOT_PROGRESS | |
32 | ||
33 | /* SMC9111 */ | |
7194ab80 | 34 | #define CONFIG_SMC91111 |
c2042f59 | 35 | #define CONFIG_SMC91111_BASE (0xB0000000) |
36 | ||
37 | /* MEMORY */ | |
38 | #define MIGO_R_SDRAM_BASE (0x8C000000) | |
39 | #define MIGO_R_FLASH_BASE_1 (0xA0000000) | |
40 | #define MIGO_R_FLASH_BANK_SIZE (64 * 1024 * 1024) | |
41 | ||
8cd7379e | 42 | #define CONFIG_SYS_TEXT_BASE 0x8FFC0000 |
6d0f6bcf | 43 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
6d0f6bcf JCPV |
44 | #define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */ |
45 | #define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */ | |
46 | #define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */ | |
47 | #define CONFIG_SYS_BARGSIZE 512 /* Buffer size for Boot Arguments passed to kernel */ | |
48 | #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */ | |
c2042f59 | 49 | |
50 | /* SCIF */ | |
6c58a030 | 51 | #define CONFIG_SCIF_CONSOLE 1 |
c2042f59 | 52 | #define CONFIG_CONS_SCIF0 1 |
6d0f6bcf | 53 | #undef CONFIG_SYS_CONSOLE_INFO_QUIET /* Suppress display of console |
c2042f59 | 54 | information at boot */ |
6d0f6bcf JCPV |
55 | #undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE |
56 | #undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE | |
c2042f59 | 57 | |
6d0f6bcf JCPV |
58 | #define CONFIG_SYS_MEMTEST_START (MIGO_R_SDRAM_BASE) |
59 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024)) | |
c2042f59 | 60 | |
61 | /* Enable alternate, more extensive, memory test */ | |
6d0f6bcf | 62 | #undef CONFIG_SYS_ALT_MEMTEST |
c2042f59 | 63 | /* Scratch address used by the alternate memory test */ |
6d0f6bcf | 64 | #undef CONFIG_SYS_MEMTEST_SCRATCH |
c2042f59 | 65 | |
66 | /* Enable temporary baudrate change while serial download */ | |
6d0f6bcf | 67 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE |
c2042f59 | 68 | |
6d0f6bcf | 69 | #define CONFIG_SYS_SDRAM_BASE (MIGO_R_SDRAM_BASE) |
c2042f59 | 70 | /* maybe more, but if so u-boot doesn't know about it... */ |
6d0f6bcf | 71 | #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) |
c2042f59 | 72 | /* default load address for scripts ?!? */ |
6d0f6bcf | 73 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024) |
c2042f59 | 74 | |
75 | /* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */ | |
6d0f6bcf | 76 | #define CONFIG_SYS_MONITOR_BASE (MIGO_R_FLASH_BASE_1) |
c2042f59 | 77 | /* Monitor size */ |
6d0f6bcf | 78 | #define CONFIG_SYS_MONITOR_LEN (128 * 1024) |
c2042f59 | 79 | /* Size of DRAM reserved for malloc() use */ |
6d0f6bcf | 80 | #define CONFIG_SYS_MALLOC_LEN (256 * 1024) |
6d0f6bcf | 81 | #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) |
c2042f59 | 82 | |
83 | /* FLASH */ | |
6d0f6bcf | 84 | #define CONFIG_SYS_FLASH_CFI |
00b1883a | 85 | #define CONFIG_FLASH_CFI_DRIVER |
6d0f6bcf | 86 | #undef CONFIG_SYS_FLASH_QUIET_TEST |
c2042f59 | 87 | /* print 'E' for empty sector on flinfo */ |
6d0f6bcf | 88 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
c2042f59 | 89 | /* Physical start address of Flash memory */ |
6d0f6bcf | 90 | #define CONFIG_SYS_FLASH_BASE (MIGO_R_FLASH_BASE_1) |
c2042f59 | 91 | /* Max number of sectors on each Flash chip */ |
6d0f6bcf | 92 | #define CONFIG_SYS_MAX_FLASH_SECT 512 |
c2042f59 | 93 | |
94 | /* if you use all NOR Flash , you change dip-switch. Please see MIGO_R01 Manual. */ | |
6d0f6bcf JCPV |
95 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 |
96 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + (0 * MIGO_R_FLASH_BANK_SIZE) } | |
c2042f59 | 97 | |
98 | /* Timeout for Flash erase operations (in ms) */ | |
6d0f6bcf | 99 | #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) |
c2042f59 | 100 | /* Timeout for Flash write operations (in ms) */ |
6d0f6bcf | 101 | #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) |
c2042f59 | 102 | /* Timeout for Flash set sector lock bit operations (in ms) */ |
6d0f6bcf | 103 | #define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) |
c2042f59 | 104 | /* Timeout for Flash clear lock bit operations (in ms) */ |
6d0f6bcf | 105 | #define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) |
c2042f59 | 106 | |
107 | /* Use hardware flash sectors protection instead of U-Boot software protection */ | |
6d0f6bcf JCPV |
108 | #undef CONFIG_SYS_FLASH_PROTECTION |
109 | #undef CONFIG_SYS_DIRECT_FLASH_TFTP | |
c2042f59 | 110 | |
111 | /* ENV setting */ | |
5a1aceb0 | 112 | #define CONFIG_ENV_IS_IN_FLASH |
c2042f59 | 113 | #define CONFIG_ENV_OVERWRITE 1 |
0e8d1586 JCPV |
114 | #define CONFIG_ENV_SECT_SIZE (128 * 1024) |
115 | #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) | |
6d0f6bcf JCPV |
116 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) |
117 | /* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */ | |
118 | #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) | |
0e8d1586 | 119 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) |
c2042f59 | 120 | |
121 | /* Board Clock */ | |
122 | #define CONFIG_SYS_CLK_FREQ 33333333 | |
684a501e NI |
123 | #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ |
124 | #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ | |
be45c632 | 125 | #define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */ |
c2042f59 | 126 | |
127 | #endif /* __MIGO_R_H */ |