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dm: core: Create a new header file for 'compat' features
[J-u-boot.git] / drivers / fpga / fpga.c
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83d290c5 1// SPDX-License-Identifier: GPL-2.0+
e2211743
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2/*
3 * (C) Copyright 2002
4 * Rich Ireland, Enterasys Networks, [email protected].
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5 */
6
f6555d90 7/* Generic FPGA support */
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8#include <common.h> /* core U-Boot definitions */
9#include <xilinx.h> /* xilinx specific definitions */
10#include <altera.h> /* altera specific definitions */
3b8ac464 11#include <lattice.h>
336d4615 12#include <dm/device_compat.h>
e2211743 13
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14/* Local definitions */
15#ifndef CONFIG_MAX_FPGA_DEVICES
16#define CONFIG_MAX_FPGA_DEVICES 5
17#endif
18
e2211743 19/* Local static data */
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20static int next_desc = FPGA_INVALID_DEVICE;
21static fpga_desc desc_table[CONFIG_MAX_FPGA_DEVICES];
22
f6555d90
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23/*
24 * fpga_no_sup
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25 * 'no support' message function
26 */
f6555d90 27static void fpga_no_sup(char *fn, char *msg)
e2211743 28{
f6555d90
MS
29 if (fn && msg)
30 printf("%s: No support for %s.\n", fn, msg);
31 else if (msg)
32 printf("No support for %s.\n", msg);
33 else
62a3b7dd 34 printf("No FPGA support!\n");
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35}
36
37
38/* fpga_get_desc
39 * map a device number to a descriptor
40 */
ebd322de 41const fpga_desc *const fpga_get_desc(int devnum)
e2211743 42{
f6555d90 43 fpga_desc *desc = (fpga_desc *)NULL;
e2211743 44
f6555d90 45 if ((devnum >= 0) && (devnum < next_desc)) {
e2211743 46 desc = &desc_table[devnum];
f6555d90
MS
47 debug("%s: found fpga descriptor #%d @ 0x%p\n",
48 __func__, devnum, desc);
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49 }
50
51 return desc;
52}
53
f6555d90
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54/*
55 * fpga_validate
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56 * generic parameter checking code
57 */
6631db47
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58const fpga_desc *const fpga_validate(int devnum, const void *buf,
59 size_t bsize, char *fn)
e2211743 60{
f6555d90 61 const fpga_desc *desc = fpga_get_desc(devnum);
e2211743 62
f6555d90
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63 if (!desc)
64 printf("%s: Invalid device number %d\n", fn, devnum);
e2211743 65
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66 if (!buf) {
67 printf("%s: Null buffer.\n", fn);
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68 return (fpga_desc * const)NULL;
69 }
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70 return desc;
71}
72
f6555d90
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73/*
74 * fpga_dev_info
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75 * generic multiplexing code
76 */
f6555d90 77static int fpga_dev_info(int devnum)
e2211743 78{
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79 int ret_val = FPGA_FAIL; /* assume failure */
80 const fpga_desc * const desc = fpga_get_desc(devnum);
e2211743 81
f6555d90
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82 if (desc) {
83 debug("%s: Device Descriptor @ 0x%p\n",
84 __func__, desc->devdesc);
e2211743 85
f6555d90 86 switch (desc->devtype) {
e2211743 87 case fpga_xilinx:
0133502e 88#if defined(CONFIG_FPGA_XILINX)
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89 printf("Xilinx Device\nDescriptor @ 0x%p\n", desc);
90 ret_val = xilinx_info(desc->devdesc);
e2211743 91#else
f6555d90 92 fpga_no_sup((char *)__func__, "Xilinx devices");
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93#endif
94 break;
95 case fpga_altera:
0133502e 96#if defined(CONFIG_FPGA_ALTERA)
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97 printf("Altera Device\nDescriptor @ 0x%p\n", desc);
98 ret_val = altera_info(desc->devdesc);
e2211743 99#else
f6555d90 100 fpga_no_sup((char *)__func__, "Altera devices");
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101#endif
102 break;
3b8ac464 103 case fpga_lattice:
439f6f7e 104#if defined(CONFIG_FPGA_LATTICE)
3b8ac464
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105 printf("Lattice Device\nDescriptor @ 0x%p\n", desc);
106 ret_val = lattice_info(desc->devdesc);
439f6f7e 107#else
f6555d90 108 fpga_no_sup((char *)__func__, "Lattice devices");
439f6f7e 109#endif
3b8ac464 110 break;
e2211743 111 default:
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112 printf("%s: Invalid or unsupported device type %d\n",
113 __func__, desc->devtype);
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114 }
115 } else {
f6555d90 116 printf("%s: Invalid device number %d\n", __func__, devnum);
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117 }
118
119 return ret_val;
120}
121
f6555d90 122/*
905bca6c 123 * fpga_init is usually called from misc_init_r() and MUST be called
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124 * before any of the other fpga functions are used.
125 */
6385b281 126void fpga_init(void)
e2211743 127{
e2211743 128 next_desc = 0;
f6555d90 129 memset(desc_table, 0, sizeof(desc_table));
e2211743 130
ee976c1b 131 debug("%s\n", __func__);
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132}
133
f6555d90
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134/*
135 * fpga_count
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136 * Basic interface function to get the current number of devices available.
137 */
f6555d90 138int fpga_count(void)
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139{
140 return next_desc;
141}
142
f6555d90
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143/*
144 * fpga_add
6385b281 145 * Add the device descriptor to the device table.
e2211743 146 */
f6555d90 147int fpga_add(fpga_type devtype, void *desc)
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148{
149 int devnum = FPGA_INVALID_DEVICE;
150
cda1e3fb
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151 if (!desc) {
152 printf("%s: NULL device descriptor\n", __func__);
153 return devnum;
154 }
155
f6555d90
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156 if (next_desc < 0) {
157 printf("%s: FPGA support not initialized!\n", __func__);
158 } else if ((devtype > fpga_min_type) && (devtype < fpga_undefined)) {
cda1e3fb
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159 if (next_desc < CONFIG_MAX_FPGA_DEVICES) {
160 devnum = next_desc;
161 desc_table[next_desc].devtype = devtype;
162 desc_table[next_desc++].devdesc = desc;
e2211743 163 } else {
cda1e3fb
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164 printf("%s: Exceeded Max FPGA device count\n",
165 __func__);
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166 }
167 } else {
f6555d90 168 printf("%s: Unsupported FPGA type %d\n", __func__, devtype);
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169 }
170
171 return devnum;
172}
173
8b93a92f
GS
174/*
175 * Return 1 if the fpga data is partial.
176 * This is only required for fpga drivers that support bitstream_type.
177 */
178int __weak fpga_is_partial_data(int devnum, size_t img_len)
179{
180 return 0;
181}
182
52c20644
MS
183/*
184 * Convert bitstream data and load into the fpga
185 */
7a78bd26
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186int __weak fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
187 bitstream_type bstype)
52c20644
MS
188{
189 printf("Bitstream support not implemented for this FPGA device\n");
190 return FPGA_FAIL;
191}
192
1a897668
SDPP
193#if defined(CONFIG_CMD_FPGA_LOADFS)
194int fpga_fsload(int devnum, const void *buf, size_t size,
195 fpga_fs_info *fpga_fsinfo)
196{
197 int ret_val = FPGA_FAIL; /* assume failure */
198 const fpga_desc *desc = fpga_validate(devnum, buf, size,
199 (char *)__func__);
200
201 if (desc) {
202 switch (desc->devtype) {
203 case fpga_xilinx:
204#if defined(CONFIG_FPGA_XILINX)
205 ret_val = xilinx_loadfs(desc->devdesc, buf, size,
206 fpga_fsinfo);
207#else
208 fpga_no_sup((char *)__func__, "Xilinx devices");
209#endif
210 break;
211 default:
212 printf("%s: Invalid or unsupported device type %d\n",
213 __func__, desc->devtype);
214 }
215 }
216
217 return ret_val;
218}
219#endif
220
cedd48e2
SDPP
221#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
222int fpga_loads(int devnum, const void *buf, size_t size,
223 struct fpga_secure_info *fpga_sec_info)
224{
225 int ret_val = FPGA_FAIL;
226
227 const fpga_desc *desc = fpga_validate(devnum, buf, size,
228 (char *)__func__);
229
230 if (desc) {
231 switch (desc->devtype) {
232 case fpga_xilinx:
233#if defined(CONFIG_FPGA_XILINX)
234 ret_val = xilinx_loads(desc->devdesc, buf, size,
235 fpga_sec_info);
236#else
237 fpga_no_sup((char *)__func__, "Xilinx devices");
238#endif
239 break;
240 default:
241 printf("%s: Invalid or unsupported device type %d\n",
242 __func__, desc->devtype);
243 }
244 }
245
246 return ret_val;
247}
248#endif
249
e2211743 250/*
f6555d90 251 * Generic multiplexing code
e2211743 252 */
7a78bd26 253int fpga_load(int devnum, const void *buf, size_t bsize, bitstream_type bstype)
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254{
255 int ret_val = FPGA_FAIL; /* assume failure */
f6555d90
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256 const fpga_desc *desc = fpga_validate(devnum, buf, bsize,
257 (char *)__func__);
e2211743 258
f6555d90
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259 if (desc) {
260 switch (desc->devtype) {
e2211743 261 case fpga_xilinx:
0133502e 262#if defined(CONFIG_FPGA_XILINX)
7a78bd26
MS
263 ret_val = xilinx_load(desc->devdesc, buf, bsize,
264 bstype);
e2211743 265#else
f6555d90 266 fpga_no_sup((char *)__func__, "Xilinx devices");
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267#endif
268 break;
269 case fpga_altera:
0133502e 270#if defined(CONFIG_FPGA_ALTERA)
f6555d90 271 ret_val = altera_load(desc->devdesc, buf, bsize);
e2211743 272#else
f6555d90 273 fpga_no_sup((char *)__func__, "Altera devices");
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274#endif
275 break;
3b8ac464 276 case fpga_lattice:
439f6f7e 277#if defined(CONFIG_FPGA_LATTICE)
3b8ac464 278 ret_val = lattice_load(desc->devdesc, buf, bsize);
439f6f7e 279#else
f6555d90 280 fpga_no_sup((char *)__func__, "Lattice devices");
439f6f7e 281#endif
3b8ac464 282 break;
e2211743 283 default:
f6555d90
MS
284 printf("%s: Invalid or unsupported device type %d\n",
285 __func__, desc->devtype);
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286 }
287 }
288
289 return ret_val;
290}
291
f6555d90
MS
292/*
293 * fpga_dump
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294 * generic multiplexing code
295 */
e6a857da 296int fpga_dump(int devnum, const void *buf, size_t bsize)
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297{
298 int ret_val = FPGA_FAIL; /* assume failure */
f6555d90
MS
299 const fpga_desc *desc = fpga_validate(devnum, buf, bsize,
300 (char *)__func__);
e2211743 301
f6555d90
MS
302 if (desc) {
303 switch (desc->devtype) {
e2211743 304 case fpga_xilinx:
0133502e 305#if defined(CONFIG_FPGA_XILINX)
f6555d90 306 ret_val = xilinx_dump(desc->devdesc, buf, bsize);
e2211743 307#else
f6555d90 308 fpga_no_sup((char *)__func__, "Xilinx devices");
e2211743
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309#endif
310 break;
311 case fpga_altera:
0133502e 312#if defined(CONFIG_FPGA_ALTERA)
f6555d90 313 ret_val = altera_dump(desc->devdesc, buf, bsize);
e2211743 314#else
f6555d90 315 fpga_no_sup((char *)__func__, "Altera devices");
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316#endif
317 break;
3b8ac464 318 case fpga_lattice:
439f6f7e 319#if defined(CONFIG_FPGA_LATTICE)
3b8ac464 320 ret_val = lattice_dump(desc->devdesc, buf, bsize);
439f6f7e 321#else
f6555d90 322 fpga_no_sup((char *)__func__, "Lattice devices");
439f6f7e 323#endif
3b8ac464 324 break;
e2211743 325 default:
f6555d90
MS
326 printf("%s: Invalid or unsupported device type %d\n",
327 __func__, desc->devtype);
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328 }
329 }
330
331 return ret_val;
332}
333
f6555d90
MS
334/*
335 * fpga_info
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336 * front end to fpga_dev_info. If devnum is invalid, report on all
337 * available devices.
338 */
f6555d90 339int fpga_info(int devnum)
e2211743 340{
f6555d90
MS
341 if (devnum == FPGA_INVALID_DEVICE) {
342 if (next_desc > 0) {
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343 int dev;
344
f6555d90
MS
345 for (dev = 0; dev < next_desc; dev++)
346 fpga_dev_info(dev);
347
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348 return FPGA_SUCCESS;
349 } else {
f6555d90 350 printf("%s: No FPGA devices available.\n", __func__);
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351 return FPGA_FAIL;
352 }
353 }
e2211743 354
f6555d90
MS
355 return fpga_dev_info(devnum);
356}
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