[J-u-boot.git] / include / configs / stout.h

/*
 * include/configs/stout.h
 *     This file is Stout board configuration.
 *
 * Copyright (C) 2015 Renesas Electronics Europe GmbH
 * Copyright (C) 2015 Renesas Electronics Corporation
 * Copyright (C) 2015 Cogent Embedded, Inc.
 *
 * SPDX-License-Identifier: GPL-2.0
 */

#ifndef __STOUT_H
#define __STOUT_H

#undef DEBUG
#define CONFIG_R8A7790
#define CONFIG_ARCH_RMOBILE_BOARD_STRING "Stout"

#include "rcar-gen2-common.h"

#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
#define CONFIG_SYS_TEXT_BASE	0xB0000000
#else
#define CONFIG_SYS_TEXT_BASE	0xE8080000
#endif

/* STACK */
#if defined(CONFIGF_RMOBILE_EXTRAM_BOOT)
#define CONFIG_SYS_INIT_SP_ADDR		0xB003FFFC
#else
#define CONFIG_SYS_INIT_SP_ADDR		0xE827FFFC
#endif
#define STACK_AREA_SIZE			0xC000
#define LOW_LEVEL_MERAM_STACK	\
		(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)

/* MEMORY */
#define RCAR_GEN2_SDRAM_BASE		0x40000000
#define RCAR_GEN2_SDRAM_SIZE		(1024u * 1024 * 1024)
#define RCAR_GEN2_UBOOT_SDRAM_SIZE	(512 * 1024 * 1024)

/* SCIF */
#define CONFIG_SCIF_A

/* SPI */
#define CONFIG_SPI
#define CONFIG_SH_QSPI
#define CONFIG_SPI_FLASH_QUAD

/* SH Ether */
#define CONFIG_SH_ETHER
#define CONFIG_SH_ETHER_USE_PORT	0
#define CONFIG_SH_ETHER_PHY_ADDR	0x1
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
#define CONFIG_SH_ETHER_ALIGNE_SIZE	64
#define CONFIG_SH_ETHER_CACHE_WRITEBACK
#define CONFIG_SH_ETHER_CACHE_INVALIDATE
#define CONFIG_PHY_MICREL
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_RCAR
#define CONFIG_SYS_RCAR_I2C0_SPEED	400000
#define CONFIG_SYS_RCAR_I2C1_SPEED	400000
#define CONFIG_SYS_RCAR_I2C2_SPEED	400000
#define CONFIG_SYS_RCAR_I2C3_SPEED	400000
#define CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS	4

#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */

/* Board Clock */
#define RMOBILE_XTAL_CLK	20000000u
#define CONFIG_SYS_CLK_FREQ	RMOBILE_XTAL_CLK
#define CONFIG_SH_TMU_CLK_FREQ	(CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */
#define CONFIG_PLL1_CLK_FREQ	(CONFIG_SYS_CLK_FREQ * 156 / 2)
#define CONFIG_PLL1_DIV2_CLK_FREQ	(CONFIG_PLL1_CLK_FREQ / 2)
#define CONFIG_MP_CLK_FREQ	(CONFIG_PLL1_DIV2_CLK_FREQ / 15)
#define CONFIG_HP_CLK_FREQ	(CONFIG_PLL1_CLK_FREQ / 12)

#define CONFIG_SYS_TMU_CLK_DIV	4

/* USB */
#define CONFIG_USB_EHCI_RMOBILE
#define CONFIG_USB_MAX_CONTROLLER_COUNT	3

/* Module stop status bits */
/* INTC-RT */
#define CONFIG_SMSTP0_ENA	0x00400000
/* MSIF, SCIFA0 */
#define CONFIG_SMSTP2_ENA	0x00002010
/* INTC-SYS, IRQC */
#define CONFIG_SMSTP4_ENA	0x00000180

/* SDHI */
#define CONFIG_SH_SDHI_FREQ	97500000

#endif	/* __STOUT_H */
Commit	Line	Data
21871138 VB	1	/*
	2	* include/configs/stout.h
	3	* This file is Stout board configuration.
	4	*
	5	* Copyright (C) 2015 Renesas Electronics Europe GmbH
	6	* Copyright (C) 2015 Renesas Electronics Corporation
	7	* Copyright (C) 2015 Cogent Embedded, Inc.
	8	*
	9	* SPDX-License-Identifier: GPL-2.0
	10	*/
	11
	12	#ifndef __STOUT_H
	13	#define __STOUT_H
	14
	15	#undef DEBUG
	16	#define CONFIG_R8A7790
1cc95f6e	17	#define CONFIG_ARCH_RMOBILE_BOARD_STRING "Stout"
21871138 VB	18
	19	#include "rcar-gen2-common.h"
	20
1cc95f6e	21	#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
21871138 VB	22	#define CONFIG_SYS_TEXT_BASE 0xB0000000
	23	#else
	24	#define CONFIG_SYS_TEXT_BASE 0xE8080000
	25	#endif
	26
	27	/* STACK */
	28	#if defined(CONFIGF_RMOBILE_EXTRAM_BOOT)
	29	#define CONFIG_SYS_INIT_SP_ADDR 0xB003FFFC
	30	#else
	31	#define CONFIG_SYS_INIT_SP_ADDR 0xE827FFFC
	32	#endif
	33	#define STACK_AREA_SIZE 0xC000
	34	#define LOW_LEVEL_MERAM_STACK \
	35	(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
	36
	37	/* MEMORY */
	38	#define RCAR_GEN2_SDRAM_BASE 0x40000000
	39	#define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024)
	40	#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
	41
	42	/* SCIF */
21871138 VB	43	#define CONFIG_SCIF_A
	44
	45	/* SPI */
	46	#define CONFIG_SPI
	47	#define CONFIG_SH_QSPI
21871138	48	#define CONFIG_SPI_FLASH_QUAD
21871138 VB	49
	50	/* SH Ether */
	51	#define CONFIG_SH_ETHER
	52	#define CONFIG_SH_ETHER_USE_PORT 0
	53	#define CONFIG_SH_ETHER_PHY_ADDR 0x1
	54	#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
	55	#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
	56	#define CONFIG_SH_ETHER_CACHE_WRITEBACK
	57	#define CONFIG_SH_ETHER_CACHE_INVALIDATE
21871138 VB	58	#define CONFIG_PHY_MICREL
	59	#define CONFIG_BITBANGMII
	60	#define CONFIG_BITBANGMII_MULTI
	61
	62	/* I2C */
	63	#define CONFIG_SYS_I2C
	64	#define CONFIG_SYS_I2C_RCAR
	65	#define CONFIG_SYS_RCAR_I2C0_SPEED 400000
	66	#define CONFIG_SYS_RCAR_I2C1_SPEED 400000
	67	#define CONFIG_SYS_RCAR_I2C2_SPEED 400000
	68	#define CONFIG_SYS_RCAR_I2C3_SPEED 400000
	69	#define CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS 4
	70
	71	#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
	72
	73	/* Board Clock */
	74	#define RMOBILE_XTAL_CLK 20000000u
	75	#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
	76	#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */
	77	#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2)
	78	#define CONFIG_PLL1_DIV2_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 2)
	79	#define CONFIG_MP_CLK_FREQ (CONFIG_PLL1_DIV2_CLK_FREQ / 15)
	80	#define CONFIG_HP_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 12)
	81
	82	#define CONFIG_SYS_TMU_CLK_DIV 4
	83
	84	/* USB */
21871138 VB	85	#define CONFIG_USB_EHCI_RMOBILE
21871138 VB	86	#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
21871138	87
21871138 VB	88	/* Module stop status bits */
	89	/* INTC-RT */
	90	#define CONFIG_SMSTP0_ENA 0x00400000
	91	/* MSIF, SCIFA0 */
	92	#define CONFIG_SMSTP2_ENA 0x00002010
	93	/* INTC-SYS, IRQC */
	94	#define CONFIG_SMSTP4_ENA 0x00000180
	95
	96	/* SDHI */
	97	#define CONFIG_SH_SDHI_FREQ 97500000
	98
	99	#endif /* __STOUT_H */