[J-u-boot.git] / include / configs / strider.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * (C) Copyright 2014
 * Dirk Eibach,  Guntermann & Drunck GmbH, [email protected]
 *
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_E300		1 /* E300 family */
#define CONFIG_MPC83xx		1 /* MPC83xx family */

#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC83xx_ESDHC_ADDR

/*
 * System IO Config
 */
#define CONFIG_SYS_SICRH (\
	SICRH_ESDHC_A_SD |\
	SICRH_ESDHC_B_SD |\
	SICRH_ESDHC_C_SD |\
	SICRH_GPIO_A_GPIO |\
	SICRH_GPIO_B_GPIO |\
	SICRH_IEEE1588_A_GPIO |\
	SICRH_USB |\
	SICRH_GTM_GPIO |\
	SICRH_IEEE1588_B_GPIO |\
	SICRH_ETSEC2_GPIO |\
	SICRH_GPIOSEL_1 |\
	SICRH_TMROBI_V3P3 |\
	SICRH_TSOBI1_V2P5 |\
	SICRH_TSOBI2_V2P5)	/* 0x0037f103 */
#define CONFIG_SYS_SICRL (\
	SICRL_SPI_PF0 |\
	SICRL_UART_PF0 |\
	SICRL_IRQ_PF0 |\
	SICRL_I2C2_PF0 |\
	SICRL_ETSEC1_TX_CLK)	/* 0x00000000 */

/*
 * IMMR new address
 */
#define CONFIG_SYS_IMMR		0xE0000000

/*
 * SERDES
 */
#define CONFIG_FSL_SERDES
#define CONFIG_FSL_SERDES1	0xe3000

/*
 * Arbiter Setup
 */
#define CONFIG_SYS_ACR_PIPE_DEP	3 /* Arbiter pipeline depth is 4 */
#define CONFIG_SYS_ACR_RPTCNT	3 /* Arbiter repeat count is 4 */
#define CONFIG_SYS_SPCR_TSECEP	3 /* eTSEC emergency priority is highest */

/*
 * DDR Setup
 */
#define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory */
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
#define CONFIG_SYS_DDRCDR_VALUE	(DDRCDR_EN \
				| DDRCDR_PZ_LOZ \
				| DDRCDR_NZ_LOZ \
				| DDRCDR_ODT \
				| DDRCDR_Q_DRN)
				/* 0x7b880001 */
/*
 * Manually set up DDR parameters
 * consist of one chip NT5TU64M16HG from NANYA
 */

#define CONFIG_SYS_DDR_SIZE		128 /* MB */

#define CONFIG_SYS_DDR_CS0_BNDS	0x00000007
#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
				| CSCONFIG_ODT_RD_NEVER \
				| CSCONFIG_ODT_WR_ONLY_CURRENT \
				| CSCONFIG_BANK_BIT_3 \
				| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
				/* 0x80010102 */
#define CONFIG_SYS_DDR_TIMING_3	0
#define CONFIG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
				| (0 << TIMING_CFG0_WRT_SHIFT) \
				| (0 << TIMING_CFG0_RRT_SHIFT) \
				| (0 << TIMING_CFG0_WWT_SHIFT) \
				| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
				| (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
				| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
				| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
				/* 0x00260802 */
#define CONFIG_SYS_DDR_TIMING_1	((2 << TIMING_CFG1_PRETOACT_SHIFT) \
				| (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
				| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
				| (7 << TIMING_CFG1_CASLAT_SHIFT) \
				| (9 << TIMING_CFG1_REFREC_SHIFT) \
				| (2 << TIMING_CFG1_WRREC_SHIFT) \
				| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
				| (2 << TIMING_CFG1_WRTORD_SHIFT))
				/* 0x26279222 */
#define CONFIG_SYS_DDR_TIMING_2	((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
				| (4 << TIMING_CFG2_CPO_SHIFT) \
				| (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
				| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
				| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
				| (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
				/* 0x021848c5 */
#define CONFIG_SYS_DDR_INTERVAL	((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \
				| (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
				/* 0x08240100 */
#define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SREN \
				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
				| SDRAM_CFG_DBW_16)
				/* 0x43100000 */

#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000 /* 1 posted refresh */
#define CONFIG_SYS_DDR_MODE		((0x0440 << SDRAM_MODE_ESD_SHIFT) \
				| (0x0242 << SDRAM_MODE_SD_SHIFT))
				/* ODT 150ohm CL=4, AL=0 on SDRAM */
#define CONFIG_SYS_DDR_MODE2		0x00000000

/*
 * Memory test
 */
#define CONFIG_SYS_MEMTEST_START	0x00001000 /* memtest region */
#define CONFIG_SYS_MEMTEST_END		0x07f00000

/*
 * The reserved memory
 */
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE /* start of monitor */

#define CONFIG_SYS_MONITOR_LEN	(384 * 1024) /* Reserve 384 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN	(512 * 1024) /* Reserved for malloc */

/*
 * Initial RAM Base Address Setup
 */
#define CONFIG_SYS_INIT_RAM_LOCK	1
#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM */
#define CONFIG_SYS_GBL_DATA_OFFSET	\
	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)

/*
 * Local Bus Configuration & Clock Setup
 */
#define CONFIG_SYS_LCRR_DBYP		LCRR_DBYP
#define CONFIG_SYS_LCRR_CLKDIV		LCRR_CLKDIV_2
#define CONFIG_SYS_LBC_LBCR		0x00040000

/*
 * FLASH on the Local Bus
 */
#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
#define CONFIG_FLASH_CFI_LEGACY
#define CONFIG_SYS_FLASH_LEGACY_512Kx16

#define CONFIG_SYS_FLASH_BASE		0xFE000000 /* FLASH base address */
#define CONFIG_SYS_FLASH_SIZE		8 /* FLASH size is up to 8M */

/* Window base at flash base */
#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_8MB)

#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE \
				| BR_PS_16	/* 16 bit port */ \
				| BR_MS_GPCM	/* MSEL = GPCM */ \
				| BR_V)		/* valid */
#define CONFIG_SYS_OR0_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
				| OR_UPM_XAM \
				| OR_GPCM_CSNT \
				| OR_GPCM_ACS_DIV2 \
				| OR_GPCM_XACS \
				| OR_GPCM_SCY_15 \
				| OR_GPCM_TRLX_SET \
				| OR_GPCM_EHTR_SET)

#define CONFIG_SYS_MAX_FLASH_BANKS	1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	135

#define CONFIG_SYS_FLASH_ERASE_TOUT	60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500 /* Flash Write Timeout (ms) */

/*
 * FPGA
 */
#define CONFIG_SYS_FPGA0_BASE		0xE0600000
#define CONFIG_SYS_FPGA0_SIZE		1 /* FPGA size is 1M */

/* Window base at FPGA base */
#define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_FPGA0_BASE
#define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_1MB)

#define CONFIG_SYS_BR1_PRELIM	(CONFIG_SYS_FPGA0_BASE \
				| BR_PS_16	/* 16 bit port */ \
				| BR_MS_GPCM	/* MSEL = GPCM */ \
				| BR_V)		/* valid */

#define CONFIG_SYS_OR1_PRELIM   (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \
				| OR_UPM_XAM \
				| OR_GPCM_CSNT \
				| OR_GPCM_SCY_5 \
				| OR_GPCM_TRLX_CLEAR \
				| OR_GPCM_EHTR_CLEAR)

#define CONFIG_SYS_FPGA_BASE(k)		CONFIG_SYS_FPGA0_BASE
#define CONFIG_SYS_FPGA_DONE(k)		0x0010

#define CONFIG_SYS_FPGA_COUNT		1

#define CONFIG_SYS_MCLINK_MAX		3

#define CONFIG_SYS_FPGA_PTR \
	{ (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }

#define CONFIG_SYS_FPGA_NO_RFL_HI

/*
 * Serial Port
 */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#define CONFIG_SYS_BAUDRATE_TABLE  \
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR + 0x4500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR + 0x4600)

/* Pass open firmware flat tree */

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	400000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000

#define CONFIG_PCA953X			/* NXP PCA9554 */
#define CONFIG_SYS_I2C_PCA953X_WIDTH    { {0x24, 16}, {0x25, 16}, {0x26, 16}, \
					  {0x3c, 8}, {0x3d, 8}, {0x3e, 8} }

#define CONFIG_PCA9698			/* NXP PCA9698 */

#define CONFIG_SYS_I2C_IHS
#define CONFIG_SYS_I2C_IHS_CH0
#define CONFIG_SYS_I2C_IHS_SPEED_0		50000
#define CONFIG_SYS_I2C_IHS_SLAVE_0		0x7F
#define CONFIG_SYS_I2C_IHS_CH1
#define CONFIG_SYS_I2C_IHS_SPEED_1		50000
#define CONFIG_SYS_I2C_IHS_SLAVE_1		0x7F
#define CONFIG_SYS_I2C_IHS_CH2
#define CONFIG_SYS_I2C_IHS_SPEED_2		50000
#define CONFIG_SYS_I2C_IHS_SLAVE_2		0x7F
#define CONFIG_SYS_I2C_IHS_CH3
#define CONFIG_SYS_I2C_IHS_SPEED_3		50000
#define CONFIG_SYS_I2C_IHS_SLAVE_3		0x7F

#ifdef CONFIG_STRIDER_CON_DP
#define CONFIG_SYS_I2C_IHS_DUAL
#define CONFIG_SYS_I2C_IHS_CH0_1
#define CONFIG_SYS_I2C_IHS_SPEED_0_1		50000
#define CONFIG_SYS_I2C_IHS_SLAVE_0_1		0x7F
#define CONFIG_SYS_I2C_IHS_CH1_1
#define CONFIG_SYS_I2C_IHS_SPEED_1_1		50000
#define CONFIG_SYS_I2C_IHS_SLAVE_1_1		0x7F
#define CONFIG_SYS_I2C_IHS_CH2_1
#define CONFIG_SYS_I2C_IHS_SPEED_2_1		50000
#define CONFIG_SYS_I2C_IHS_SLAVE_2_1		0x7F
#define CONFIG_SYS_I2C_IHS_CH3_1
#define CONFIG_SYS_I2C_IHS_SPEED_3_1		50000
#define CONFIG_SYS_I2C_IHS_SLAVE_3_1		0x7F
#endif

/*
 * Software (bit-bang) I2C driver configuration
 */
#define CONFIG_SYS_I2C_SOFT
#define CONFIG_SOFT_I2C_READ_REPEATED_START
#define CONFIG_SYS_I2C_SOFT_SPEED		50000
#define CONFIG_SYS_I2C_SOFT_SLAVE		0x7F
#define I2C_SOFT_DECLARATIONS2
#define CONFIG_SYS_I2C_SOFT_SPEED_2		50000
#define CONFIG_SYS_I2C_SOFT_SLAVE_2		0x7F
#define I2C_SOFT_DECLARATIONS3
#define CONFIG_SYS_I2C_SOFT_SPEED_3		50000
#define CONFIG_SYS_I2C_SOFT_SLAVE_3		0x7F
#define I2C_SOFT_DECLARATIONS4
#define CONFIG_SYS_I2C_SOFT_SPEED_4		50000
#define CONFIG_SYS_I2C_SOFT_SLAVE_4		0x7F
#if defined(CONFIG_STRIDER_CON) || defined(CONFIG_STRIDER_CON_DP)
#define I2C_SOFT_DECLARATIONS5
#define CONFIG_SYS_I2C_SOFT_SPEED_5		50000
#define CONFIG_SYS_I2C_SOFT_SLAVE_5		0x7F
#define I2C_SOFT_DECLARATIONS6
#define CONFIG_SYS_I2C_SOFT_SPEED_6		50000
#define CONFIG_SYS_I2C_SOFT_SLAVE_6		0x7F
#define I2C_SOFT_DECLARATIONS7
#define CONFIG_SYS_I2C_SOFT_SPEED_7		50000
#define CONFIG_SYS_I2C_SOFT_SLAVE_7		0x7F
#define I2C_SOFT_DECLARATIONS8
#define CONFIG_SYS_I2C_SOFT_SPEED_8		50000
#define CONFIG_SYS_I2C_SOFT_SLAVE_8		0x7F
#endif
#ifdef CONFIG_STRIDER_CON_DP
#define I2C_SOFT_DECLARATIONS9
#define CONFIG_SYS_I2C_SOFT_SPEED_9		50000
#define CONFIG_SYS_I2C_SOFT_SLAVE_9		0x7F
#define I2C_SOFT_DECLARATIONS10
#define CONFIG_SYS_I2C_SOFT_SPEED_10		50000
#define CONFIG_SYS_I2C_SOFT_SLAVE_10		0x7F
#define I2C_SOFT_DECLARATIONS11
#define CONFIG_SYS_I2C_SOFT_SPEED_11		50000
#define CONFIG_SYS_I2C_SOFT_SLAVE_11		0x7F
#define I2C_SOFT_DECLARATIONS12
#define CONFIG_SYS_I2C_SOFT_SPEED_12		50000
#define CONFIG_SYS_I2C_SOFT_SLAVE_12		0x7F
#endif

#ifdef CONFIG_STRIDER_CON
#define CONFIG_SYS_ICS8N3QV01_I2C		{5, 6, 7, 8}
#define CONFIG_SYS_CH7301_I2C			{5, 6, 7, 8}
#define CONFIG_SYS_ADV7611_I2C			{5, 6, 7, 8}
#define CONFIG_SYS_DP501_I2C			{1, 2, 3, 4}
#define CONFIG_STRIDER_FANS			{ {10, 0x4c}, {11, 0x4c}, \
						  {12, 0x4c} }
#elif defined(CONFIG_STRIDER_CON_DP)
#define CONFIG_SYS_ICS8N3QV01_I2C		{13, 14, 15, 16, 17, 18, 19, 20}
#define CONFIG_SYS_CH7301_I2C			{1, 3, 5, 7}
#define CONFIG_SYS_ADV7611_I2C			{1, 3, 5, 7}
#define CONFIG_SYS_DP501_I2C			{1, 3, 5, 7, 2, 4, 6, 8}
#define CONFIG_STRIDER_FANS			{ {10, 0x4c}, {11, 0x4c}, \
						  {12, 0x4c} }
#elif defined(CONFIG_STRIDER_CPU_DP)
#define CONFIG_SYS_CH7301_I2C			{1, 2, 3, 4}
#define CONFIG_SYS_ADV7611_I2C			{1, 2, 3, 4}
#define CONFIG_SYS_DP501_I2C			{1, 2, 3, 4}
#define CONFIG_STRIDER_FANS			{ {6, 0x4c}, {7, 0x4c}, \
						  {8, 0x4c} }
#else
#define CONFIG_SYS_CH7301_I2C			{1, 2, 3, 4}
#define CONFIG_SYS_ADV7611_I2C			{1, 2, 3, 4}
#define CONFIG_SYS_DP501_I2C			{1, 2, 3, 4}
#define CONFIG_STRIDER_FANS			{ {2, 0x18}, {3, 0x18}, \
						  {4, 0x18} }
#endif

#ifndef __ASSEMBLY__
void fpga_gpio_set(unsigned int bus, int pin);
void fpga_gpio_clear(unsigned int bus, int pin);
int fpga_gpio_get(unsigned int bus, int pin);
void fpga_control_set(unsigned int bus, int pin);
void fpga_control_clear(unsigned int bus, int pin);
#endif

#ifdef CONFIG_STRIDER_CON
#define I2C_SDA_GPIO	((I2C_ADAP_HWNR > 3) ? 0x0200 : 0x0040)
#define I2C_SCL_GPIO	((I2C_ADAP_HWNR > 3) ? 0x0100 : 0x0020)
#define I2C_FPGA_IDX	((I2C_ADAP_HWNR > 3) ? \
			 (I2C_ADAP_HWNR - 4) : I2C_ADAP_HWNR)
#elif defined(CONFIG_STRIDER_CON_DP)
#define I2C_SDA_GPIO	((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200)
#define I2C_SCL_GPIO	((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100)
#define I2C_FPGA_IDX	(I2C_ADAP_HWNR % 4)
#else
#define I2C_SDA_GPIO	0x0040
#define I2C_SCL_GPIO	0x0020
#define I2C_FPGA_IDX	I2C_ADAP_HWNR
#endif

#ifdef CONFIG_STRIDER_CON_DP
#define I2C_ACTIVE \
	do { \
		if (I2C_ADAP_HWNR > 7) \
			fpga_control_set(I2C_FPGA_IDX, 0x0004); \
		else \
			fpga_control_clear(I2C_FPGA_IDX, 0x0004); \
	} while (0)
#else
#define I2C_ACTIVE	{ }
#endif

#define I2C_TRISTATE	{ }
#define I2C_READ \
	(fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0)
#define I2C_SDA(bit) \
	do { \
		if (bit) \
			fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \
		else \
			fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \
	} while (0)
#define I2C_SCL(bit) \
	do { \
		if (bit) \
			fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \
		else \
			fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \
	} while (0)
#define I2C_DELAY	udelay(25)	/* 1/4 I2C clock duration */

/*
 * Software (bit-bang) MII driver configuration
 */
#define CONFIG_BITBANGMII		/* bit-bang MII PHY management */
#define CONFIG_BITBANGMII_MULTI

/*
 * OSD Setup
 */
#define CONFIG_SYS_OSD_SCREENS		1
#define CONFIG_SYS_DP501_DIFFERENTIAL
#define CONFIG_SYS_DP501_VCAPCTRL0	0x01 /* DDR mode 0, DE for H/VSYNC */

#ifdef CONFIG_STRIDER_CON_DP
#define CONFIG_SYS_OSD_DH
#endif

/*
 * General PCI
 * Addresses are mapped 1-1.
 */
#define CONFIG_SYS_PCIE1_BASE		0xA0000000
#define CONFIG_SYS_PCIE1_MEM_BASE	0xA0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS	0xA0000000
#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000
#define CONFIG_SYS_PCIE1_CFG_BASE	0xB0000000
#define CONFIG_SYS_PCIE1_CFG_SIZE	0x01000000
#define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
#define CONFIG_SYS_PCIE1_IO_PHYS	0xB1000000
#define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000

/* enable PCIE clock */
#define CONFIG_SYS_SCCR_PCIEXP1CM	1

#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCIE

#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1

/*
 * TSEC
 */
#define CONFIG_SYS_TSEC1_OFFSET	0x24000
#define CONFIG_SYS_TSEC1	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)

/*
 * TSEC ethernet configuration
 */
#define CONFIG_TSEC1
#define CONFIG_TSEC1_NAME	"eTSEC0"
#define TSEC1_PHY_ADDR		1
#define TSEC1_PHYIDX		0
#define TSEC1_FLAGS		0

/* Options are: eTSEC[0-1] */
#define CONFIG_ETHPRIME		"eTSEC0"

/*
 * Environment
 */
#if 1
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + \
				 CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SECT_SIZE	0x10000 /* 64K(one sector) for env */
#define CONFIG_ENV_SIZE		0x2000
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
#else
#define CONFIG_ENV_SIZE		0x2000		/* 8KB */
#endif

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */

/*
 * Command line configuration.
 */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LOAD_ADDR		0x2000000 /* default load address */
#define CONFIG_SYS_HZ		1000	/* decrementer freq: 1ms ticks */

#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size */

#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 256 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(256 << 20) /* Initial Memory map for Linux */

/*
 * Core HID Setup
 */
#define CONFIG_SYS_HID0_INIT	0x000000000
#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
				 HID0_ENABLE_INSTRUCTION_CACHE | \
				 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
#define CONFIG_SYS_HID2		HID2_HBE

/*
 * Environment Configuration
 */

#define CONFIG_ENV_OVERWRITE

#if defined(CONFIG_TSEC_ENET)
#define CONFIG_HAS_ETH0
#endif

#define CONFIG_LOADADDR	800000	/* default location for tftp and bootm */


#define CONFIG_HOSTNAME		"hrcon"
#define CONFIG_ROOTPATH		"/opt/nfsroot"
#define CONFIG_BOOTFILE		"uImage"

#define CONFIG_PREBOOT		/* enable preboot variable */

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"consoledev=ttyS1\0"						\
	"u-boot=u-boot.bin\0"						\
	"kernel_addr=1000000\0"					\
	"fdt_addr=C00000\0"						\
	"fdtfile=hrcon.dtb\0"				\
	"load=tftp ${loadaddr} ${u-boot}\0"				\
	"update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)	\
		" +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
		" +${filesize};cp.b ${fileaddr} "			\
		__stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"	\
	"upd=run load update\0"						\

#define CONFIG_NFSBOOTCOMMAND						\
	"setenv bootargs root=/dev/nfs rw "				\
	"nfsroot=$serverip:$rootpath "					\
	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
	"console=$consoledev,$baudrate $othbootargs;"			\
	"tftp ${kernel_addr} $bootfile;"				\
	"tftp ${fdt_addr} $fdtfile;"					\
	"bootm ${kernel_addr} - ${fdt_addr}"

#define CONFIG_MMCBOOTCOMMAND						\
	"setenv bootargs root=/dev/mmcblk0p3 rw rootwait "		\
	"console=$consoledev,$baudrate $othbootargs;"			\
	"ext2load mmc 0:2 ${kernel_addr} $bootfile;"			\
	"ext2load mmc 0:2 ${fdt_addr} $fdtfile;"			\
	"bootm ${kernel_addr} - ${fdt_addr}"

#define CONFIG_BOOTCOMMAND		CONFIG_MMCBOOTCOMMAND

#endif	/* __CONFIG_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
a3f9d6c7 DE	2	/*
a3f9d6c7 DE	3	* (C) Copyright 2014
d38826a3	4	* Dirk Eibach, Guntermann & Drunck GmbH, [email protected]
a3f9d6c7	5	*
a3f9d6c7 DE	6	*/
	7
	8	#ifndef __CONFIG_H
	9	#define __CONFIG_H
	10
	11	/*
	12	* High Level Configuration Options
	13	*/
	14	#define CONFIG_E300 1 /* E300 family */
	15	#define CONFIG_MPC83xx 1 /* MPC83xx family */
a3f9d6c7	16
a3f9d6c7	17	#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
a3f9d6c7	18
a3f9d6c7 DE	19	/*
	20	* System IO Config
	21	*/
	22	#define CONFIG_SYS_SICRH (\
	23	SICRH_ESDHC_A_SD \|\
	24	SICRH_ESDHC_B_SD \|\
	25	SICRH_ESDHC_C_SD \|\
	26	SICRH_GPIO_A_GPIO \|\
	27	SICRH_GPIO_B_GPIO \|\
	28	SICRH_IEEE1588_A_GPIO \|\
	29	SICRH_USB \|\
	30	SICRH_GTM_GPIO \|\
	31	SICRH_IEEE1588_B_GPIO \|\
	32	SICRH_ETSEC2_GPIO \|\
	33	SICRH_GPIOSEL_1 \|\
	34	SICRH_TMROBI_V3P3 \|\
	35	SICRH_TSOBI1_V2P5 \|\
	36	SICRH_TSOBI2_V2P5) /* 0x0037f103 */
	37	#define CONFIG_SYS_SICRL (\
	38	SICRL_SPI_PF0 \|\
	39	SICRL_UART_PF0 \|\
	40	SICRL_IRQ_PF0 \|\
	41	SICRL_I2C2_PF0 \|\
	42	SICRL_ETSEC1_TX_CLK) /* 0x00000000 */
	43
	44	/*
	45	* IMMR new address
	46	*/
	47	#define CONFIG_SYS_IMMR 0xE0000000
	48
	49	/*
	50	* SERDES
	51	*/
	52	#define CONFIG_FSL_SERDES
	53	#define CONFIG_FSL_SERDES1 0xe3000
	54
	55	/*
	56	* Arbiter Setup
	57	*/
	58	#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
	59	#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
	60	#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
	61
	62	/*
	63	* DDR Setup
	64	*/
	65	#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
	66	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
	67	#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
	68	#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
	69	#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
	70	\| DDRCDR_PZ_LOZ \
	71	\| DDRCDR_NZ_LOZ \
	72	\| DDRCDR_ODT \
	73	\| DDRCDR_Q_DRN)
	74	/* 0x7b880001 */
	75	/*
	76	* Manually set up DDR parameters
	77	* consist of one chip NT5TU64M16HG from NANYA
	78	*/
	79
	80	#define CONFIG_SYS_DDR_SIZE 128 /* MB */
	81
	82	#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
83	#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
84	\| CSCONFIG_ODT_RD_NEVER \
85	\| CSCONFIG_ODT_WR_ONLY_CURRENT \
86	\| CSCONFIG_BANK_BIT_3 \
87	\| CSCONFIG_ROW_BIT_13 \| CSCONFIG_COL_BIT_10)
88	/* 0x80010102 */
89	#define CONFIG_SYS_DDR_TIMING_3 0
90	#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
91	\| (0 << TIMING_CFG0_WRT_SHIFT) \
92	\| (0 << TIMING_CFG0_RRT_SHIFT) \
93	\| (0 << TIMING_CFG0_WWT_SHIFT) \
94	\| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
95	\| (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
96	\| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
97	\| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
98	/* 0x00260802 */
99	#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
100	\| (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
101	\| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
102	\| (7 << TIMING_CFG1_CASLAT_SHIFT) \
103	\| (9 << TIMING_CFG1_REFREC_SHIFT) \
104	\| (2 << TIMING_CFG1_WRREC_SHIFT) \
105	\| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
106	\| (2 << TIMING_CFG1_WRTORD_SHIFT))
107	/* 0x26279222 */
108	#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
109	\| (4 << TIMING_CFG2_CPO_SHIFT) \
110	\| (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
111	\| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
112	\| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
113	\| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
114	\| (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
115	/* 0x021848c5 */
116	#define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \
117	\| (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
118	/* 0x08240100 */
119	#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
120	\| SDRAM_CFG_SDRAM_TYPE_DDR2 \
121	\| SDRAM_CFG_DBW_16)
122	/* 0x43100000 */
123
124	#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
125	#define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \
126	\| (0x0242 << SDRAM_MODE_SD_SHIFT))
127	/* ODT 150ohm CL=4, AL=0 on SDRAM */
128	#define CONFIG_SYS_DDR_MODE2 0x00000000
129
130	/*
131	* Memory test
132	*/
133	#define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */
134	#define CONFIG_SYS_MEMTEST_END 0x07f00000
135
136	/*
137	* The reserved memory
138	*/
139	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
140
141	#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
142	#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
143
144	/*
145	* Initial RAM Base Address Setup
146	*/
147	#define CONFIG_SYS_INIT_RAM_LOCK 1
148	#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
149	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
150	#define CONFIG_SYS_GBL_DATA_OFFSET \
151	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
152
153	/*
154	* Local Bus Configuration & Clock Setup
155	*/
156	#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
157	#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
158	#define CONFIG_SYS_LBC_LBCR 0x00040000
159
160	/*
161	* FLASH on the Local Bus
162	*/
a3f9d6c7 DE	163	#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
	164	#define CONFIG_FLASH_CFI_LEGACY
	165	#define CONFIG_SYS_FLASH_LEGACY_512Kx16
a3f9d6c7 DE	166
	167	#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
	168	#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */
a3f9d6c7 DE	169
	170	/* Window base at flash base */
	171	#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
	172	#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN \| LBLAWAR_8MB)
	173
	174	#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
	175	\| BR_PS_16 /* 16 bit port */ \
	176	\| BR_MS_GPCM /* MSEL = GPCM */ \
	177	\| BR_V) /* valid */
	178	#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
	179	\| OR_UPM_XAM \
	180	\| OR_GPCM_CSNT \
	181	\| OR_GPCM_ACS_DIV2 \
	182	\| OR_GPCM_XACS \
	183	\| OR_GPCM_SCY_15 \
	184	\| OR_GPCM_TRLX_SET \
	185	\| OR_GPCM_EHTR_SET)
	186
	187	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
	188	#define CONFIG_SYS_MAX_FLASH_SECT 135
	189
	190	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	191	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
	192
	193	/*
	194	* FPGA
	195	*/
	196	#define CONFIG_SYS_FPGA0_BASE 0xE0600000
	197	#define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */
	198
	199	/* Window base at FPGA base */
	200	#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA0_BASE
	201	#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN \| LBLAWAR_1MB)
	202
	203	#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA0_BASE \
	204	\| BR_PS_16 /* 16 bit port */ \
	205	\| BR_MS_GPCM /* MSEL = GPCM */ \
	206	\| BR_V) /* valid */
a119357c RP	207
a119357c RP	208	#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \
a3f9d6c7 DE	209	\| OR_UPM_XAM \
a3f9d6c7 DE	210	\| OR_GPCM_CSNT \
a119357c RP	211	\| OR_GPCM_SCY_5 \
	212	\| OR_GPCM_TRLX_CLEAR \
	213	\| OR_GPCM_EHTR_CLEAR)
a3f9d6c7 DE	214
	215	#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
	216	#define CONFIG_SYS_FPGA_DONE(k) 0x0010
	217
	218	#define CONFIG_SYS_FPGA_COUNT 1
	219
	220	#define CONFIG_SYS_MCLINK_MAX 3
	221
	222	#define CONFIG_SYS_FPGA_PTR \
	223	{ (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
	224
	225	#define CONFIG_SYS_FPGA_NO_RFL_HI
	226
	227	/*
	228	* Serial Port
	229	*/
a3f9d6c7 DE	230	#define CONFIG_SYS_NS16550_SERIAL
	231	#define CONFIG_SYS_NS16550_REG_SIZE 1
	232	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
	233
	234	#define CONFIG_SYS_BAUDRATE_TABLE \
	235	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
	236
	237	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
	238	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
	239
a3f9d6c7	240	/* Pass open firmware flat tree */
a3f9d6c7 DE	241
	242	/* I2C */
	243	#define CONFIG_SYS_I2C
	244	#define CONFIG_SYS_I2C_FSL
	245	#define CONFIG_SYS_FSL_I2C_SPEED 400000
	246	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	247	#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
	248
	249	#define CONFIG_PCA953X /* NXP PCA9554 */
47098056 DE	250	#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x24, 16}, {0x25, 16}, {0x26, 16}, \
	251	{0x3c, 8}, {0x3d, 8}, {0x3e, 8} }
	252
a3f9d6c7 DE	253	#define CONFIG_PCA9698 /* NXP PCA9698 */
	254
	255	#define CONFIG_SYS_I2C_IHS
	256	#define CONFIG_SYS_I2C_IHS_CH0
	257	#define CONFIG_SYS_I2C_IHS_SPEED_0 50000
	258	#define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F
	259	#define CONFIG_SYS_I2C_IHS_CH1
	260	#define CONFIG_SYS_I2C_IHS_SPEED_1 50000
	261	#define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F
	262	#define CONFIG_SYS_I2C_IHS_CH2
	263	#define CONFIG_SYS_I2C_IHS_SPEED_2 50000
	264	#define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F
	265	#define CONFIG_SYS_I2C_IHS_CH3
	266	#define CONFIG_SYS_I2C_IHS_SPEED_3 50000
	267	#define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F
	268
1d2541ba DE	269	#ifdef CONFIG_STRIDER_CON_DP
	270	#define CONFIG_SYS_I2C_IHS_DUAL
	271	#define CONFIG_SYS_I2C_IHS_CH0_1
	272	#define CONFIG_SYS_I2C_IHS_SPEED_0_1 50000
	273	#define CONFIG_SYS_I2C_IHS_SLAVE_0_1 0x7F
	274	#define CONFIG_SYS_I2C_IHS_CH1_1
	275	#define CONFIG_SYS_I2C_IHS_SPEED_1_1 50000
	276	#define CONFIG_SYS_I2C_IHS_SLAVE_1_1 0x7F
	277	#define CONFIG_SYS_I2C_IHS_CH2_1
	278	#define CONFIG_SYS_I2C_IHS_SPEED_2_1 50000
	279	#define CONFIG_SYS_I2C_IHS_SLAVE_2_1 0x7F
	280	#define CONFIG_SYS_I2C_IHS_CH3_1
	281	#define CONFIG_SYS_I2C_IHS_SPEED_3_1 50000
	282	#define CONFIG_SYS_I2C_IHS_SLAVE_3_1 0x7F
	283	#endif
	284
a3f9d6c7 DE	285	/*
	286	* Software (bit-bang) I2C driver configuration
	287	*/
	288	#define CONFIG_SYS_I2C_SOFT
	289	#define CONFIG_SOFT_I2C_READ_REPEATED_START
	290	#define CONFIG_SYS_I2C_SOFT_SPEED 50000
	291	#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
	292	#define I2C_SOFT_DECLARATIONS2
	293	#define CONFIG_SYS_I2C_SOFT_SPEED_2 50000
	294	#define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F
	295	#define I2C_SOFT_DECLARATIONS3
	296	#define CONFIG_SYS_I2C_SOFT_SPEED_3 50000
	297	#define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F
	298	#define I2C_SOFT_DECLARATIONS4
	299	#define CONFIG_SYS_I2C_SOFT_SPEED_4 50000
	300	#define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F
1d2541ba	301	#if defined(CONFIG_STRIDER_CON) \|\| defined(CONFIG_STRIDER_CON_DP)
a3f9d6c7 DE	302	#define I2C_SOFT_DECLARATIONS5
	303	#define CONFIG_SYS_I2C_SOFT_SPEED_5 50000
	304	#define CONFIG_SYS_I2C_SOFT_SLAVE_5 0x7F
	305	#define I2C_SOFT_DECLARATIONS6
	306	#define CONFIG_SYS_I2C_SOFT_SPEED_6 50000
	307	#define CONFIG_SYS_I2C_SOFT_SLAVE_6 0x7F
	308	#define I2C_SOFT_DECLARATIONS7
	309	#define CONFIG_SYS_I2C_SOFT_SPEED_7 50000
	310	#define CONFIG_SYS_I2C_SOFT_SLAVE_7 0x7F
	311	#define I2C_SOFT_DECLARATIONS8
	312	#define CONFIG_SYS_I2C_SOFT_SPEED_8 50000
	313	#define CONFIG_SYS_I2C_SOFT_SLAVE_8 0x7F
	314	#endif
1d2541ba DE	315	#ifdef CONFIG_STRIDER_CON_DP
	316	#define I2C_SOFT_DECLARATIONS9
	317	#define CONFIG_SYS_I2C_SOFT_SPEED_9 50000
	318	#define CONFIG_SYS_I2C_SOFT_SLAVE_9 0x7F
	319	#define I2C_SOFT_DECLARATIONS10
	320	#define CONFIG_SYS_I2C_SOFT_SPEED_10 50000
	321	#define CONFIG_SYS_I2C_SOFT_SLAVE_10 0x7F
	322	#define I2C_SOFT_DECLARATIONS11
	323	#define CONFIG_SYS_I2C_SOFT_SPEED_11 50000
	324	#define CONFIG_SYS_I2C_SOFT_SLAVE_11 0x7F
	325	#define I2C_SOFT_DECLARATIONS12
	326	#define CONFIG_SYS_I2C_SOFT_SPEED_12 50000
	327	#define CONFIG_SYS_I2C_SOFT_SLAVE_12 0x7F
	328	#endif
a3f9d6c7 DE	329
	330	#ifdef CONFIG_STRIDER_CON
	331	#define CONFIG_SYS_ICS8N3QV01_I2C {5, 6, 7, 8}
	332	#define CONFIG_SYS_CH7301_I2C {5, 6, 7, 8}
	333	#define CONFIG_SYS_ADV7611_I2C {5, 6, 7, 8}
	334	#define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
1d2541ba DE	335	#define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \
	336	{12, 0x4c} }
	337	#elif defined(CONFIG_STRIDER_CON_DP)
	338	#define CONFIG_SYS_ICS8N3QV01_I2C {13, 14, 15, 16, 17, 18, 19, 20}
	339	#define CONFIG_SYS_CH7301_I2C {1, 3, 5, 7}
	340	#define CONFIG_SYS_ADV7611_I2C {1, 3, 5, 7}
	341	#define CONFIG_SYS_DP501_I2C {1, 3, 5, 7, 2, 4, 6, 8}
a3f9d6c7 DE	342	#define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \
a3f9d6c7 DE	343	{12, 0x4c} }
145510cc DE	344	#elif defined(CONFIG_STRIDER_CPU_DP)
	345	#define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4}
	346	#define CONFIG_SYS_ADV7611_I2C {1, 2, 3, 4}
	347	#define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
	348	#define CONFIG_STRIDER_FANS { {6, 0x4c}, {7, 0x4c}, \
	349	{8, 0x4c} }
a3f9d6c7 DE	350	#else
	351	#define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4}
	352	#define CONFIG_SYS_ADV7611_I2C {1, 2, 3, 4}
	353	#define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
	354	#define CONFIG_STRIDER_FANS { {2, 0x18}, {3, 0x18}, \
	355	{4, 0x18} }
	356	#endif
	357
	358	#ifndef __ASSEMBLY__
	359	void fpga_gpio_set(unsigned int bus, int pin);
	360	void fpga_gpio_clear(unsigned int bus, int pin);
	361	int fpga_gpio_get(unsigned int bus, int pin);
1d2541ba DE	362	void fpga_control_set(unsigned int bus, int pin);
1d2541ba DE	363	void fpga_control_clear(unsigned int bus, int pin);
a3f9d6c7 DE	364	#endif
	365
	366	#ifdef CONFIG_STRIDER_CON
	367	#define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0200 : 0x0040)
	368	#define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0100 : 0x0020)
	369	#define I2C_FPGA_IDX ((I2C_ADAP_HWNR > 3) ? \
	370	(I2C_ADAP_HWNR - 4) : I2C_ADAP_HWNR)
1d2541ba DE	371	#elif defined(CONFIG_STRIDER_CON_DP)
	372	#define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200)
	373	#define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100)
	374	#define I2C_FPGA_IDX (I2C_ADAP_HWNR % 4)
a3f9d6c7 DE	375	#else
	376	#define I2C_SDA_GPIO 0x0040
	377	#define I2C_SCL_GPIO 0x0020
	378	#define I2C_FPGA_IDX I2C_ADAP_HWNR
	379	#endif
1d2541ba DE	380
	381	#ifdef CONFIG_STRIDER_CON_DP
	382	#define I2C_ACTIVE \
	383	do { \
	384	if (I2C_ADAP_HWNR > 7) \
	385	fpga_control_set(I2C_FPGA_IDX, 0x0004); \
	386	else \
	387	fpga_control_clear(I2C_FPGA_IDX, 0x0004); \
	388	} while (0)
	389	#else
a3f9d6c7	390	#define I2C_ACTIVE { }
1d2541ba DE	391	#endif
1d2541ba DE	392
a3f9d6c7 DE	393	#define I2C_TRISTATE { }
	394	#define I2C_READ \
	395	(fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0)
	396	#define I2C_SDA(bit) \
	397	do { \
	398	if (bit) \
	399	fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \
	400	else \
	401	fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \
	402	} while (0)
	403	#define I2C_SCL(bit) \
	404	do { \
	405	if (bit) \
	406	fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \
	407	else \
	408	fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \
	409	} while (0)
	410	#define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */
	411
	412	/*
	413	* Software (bit-bang) MII driver configuration
	414	*/
	415	#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
	416	#define CONFIG_BITBANGMII_MULTI
	417
	418	/*
	419	* OSD Setup
	420	*/
	421	#define CONFIG_SYS_OSD_SCREENS 1
	422	#define CONFIG_SYS_DP501_DIFFERENTIAL
	423	#define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */
	424
1d2541ba DE	425	#ifdef CONFIG_STRIDER_CON_DP
	426	#define CONFIG_SYS_OSD_DH
	427	#endif
	428
a3f9d6c7 DE	429	/*
	430	* General PCI
	431	* Addresses are mapped 1-1.
	432	*/
	433	#define CONFIG_SYS_PCIE1_BASE 0xA0000000
	434	#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
	435	#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
	436	#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
	437	#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
	438	#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
	439	#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
	440	#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
	441	#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
	442
	443	/* enable PCIE clock */
	444	#define CONFIG_SYS_SCCR_PCIEXP1CM 1
	445
a3f9d6c7 DE	446	#define CONFIG_PCI_INDIRECT_BRIDGE
	447	#define CONFIG_PCIE
	448
a3f9d6c7 DE	449	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
	450	#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
	451
	452	/*
	453	* TSEC
	454	*/
a3f9d6c7 DE	455	#define CONFIG_SYS_TSEC1_OFFSET 0x24000
	456	#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
	457
	458	/*
	459	* TSEC ethernet configuration
	460	*/
a3f9d6c7 DE	461	#define CONFIG_TSEC1
	462	#define CONFIG_TSEC1_NAME "eTSEC0"
	463	#define TSEC1_PHY_ADDR 1
	464	#define TSEC1_PHYIDX 0
	465	#define TSEC1_FLAGS 0
	466
	467	/* Options are: eTSEC[0-1] */
	468	#define CONFIG_ETHPRIME "eTSEC0"
	469
	470	/*
	471	* Environment
	472	*/
	473	#if 1
a3f9d6c7 DE	474	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
	475	CONFIG_SYS_MONITOR_LEN)
	476	#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
	477	#define CONFIG_ENV_SIZE 0x2000
	478	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
	479	#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
	480	#else
a3f9d6c7 DE	481	#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
	482	#endif
	483
	484	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	485	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
	486
	487	/*
	488	* Command line configuration.
	489	*/
a3f9d6c7	490
a3f9d6c7 DE	491	/*
	492	* Miscellaneous configurable options
	493	*/
a3f9d6c7 DE	494	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
	495	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
	496
a3f9d6c7 DE	497	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
a3f9d6c7 DE	498
a3f9d6c7 DE	499	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	500
	501	/*
	502	* For booting Linux, the board info and command line data
	503	* have to be in the first 256 MB of memory, since this is
	504	* the maximum mapped by the Linux kernel during initialization.
	505	*/
	506	#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
	507
	508	/*
	509	* Core HID Setup
	510	*/
	511	#define CONFIG_SYS_HID0_INIT 0x000000000
	512	#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \| \
	513	HID0_ENABLE_INSTRUCTION_CACHE \| \
	514	HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
	515	#define CONFIG_SYS_HID2 HID2_HBE
	516
a3f9d6c7 DE	517	/*
	518	* Environment Configuration
	519	*/
	520
	521	#define CONFIG_ENV_OVERWRITE
	522
	523	#if defined(CONFIG_TSEC_ENET)
	524	#define CONFIG_HAS_ETH0
	525	#endif
	526
a3f9d6c7 DE	527	#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
a3f9d6c7 DE	528
a3f9d6c7	529
5bc0543d	530	#define CONFIG_HOSTNAME "hrcon"
a3f9d6c7 DE	531	#define CONFIG_ROOTPATH "/opt/nfsroot"
	532	#define CONFIG_BOOTFILE "uImage"
	533
	534	#define CONFIG_PREBOOT /* enable preboot variable */
	535
	536	#define CONFIG_EXTRA_ENV_SETTINGS \
	537	"netdev=eth0\0" \
	538	"consoledev=ttyS1\0" \
	539	"u-boot=u-boot.bin\0" \
	540	"kernel_addr=1000000\0" \
	541	"fdt_addr=C00000\0" \
	542	"fdtfile=hrcon.dtb\0" \
	543	"load=tftp ${loadaddr} ${u-boot}\0" \
	544	"update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
	545	" +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
	546	" +${filesize};cp.b ${fileaddr} " \
	547	__stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
	548	"upd=run load update\0" \
	549
	550	#define CONFIG_NFSBOOTCOMMAND \
	551	"setenv bootargs root=/dev/nfs rw " \
	552	"nfsroot=$serverip:$rootpath " \
	553	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
	554	"console=$consoledev,$baudrate $othbootargs;" \
	555	"tftp ${kernel_addr} $bootfile;" \
	556	"tftp ${fdt_addr} $fdtfile;" \
	557	"bootm ${kernel_addr} - ${fdt_addr}"
	558
	559	#define CONFIG_MMCBOOTCOMMAND \
	560	"setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \
	561	"console=$consoledev,$baudrate $othbootargs;" \
	562	"ext2load mmc 0:2 ${kernel_addr} $bootfile;" \
	563	"ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \
	564	"bootm ${kernel_addr} - ${fdt_addr}"
	565
	566	#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
	567
a3f9d6c7	568	#endif /* __CONFIG_H */