[J-u-boot.git] / include / configs / MPC8313ERDB_NOR.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010.
 */
/*
 * mpc8313epb board configuration file
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_E300		1

#ifndef CONFIG_SYS_MONITOR_BASE
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
#endif

#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_FSL_ELBC 1

/*
 * On-board devices
 *
 * TSEC1 is VSC switch
 * TSEC2 is SoC TSEC
 */
#define CONFIG_VSC7385_ENET
#define CONFIG_TSEC2

#define CONFIG_SYS_IMMR		0xE0000000

#define CONFIG_SYS_MEMTEST_START	0x00001000
#define CONFIG_SYS_MEMTEST_END		0x07f00000

/* Early revs of this board will lock up hard when attempting
 * to access the PMC registers, unless a JTAG debugger is
 * connected, or some resistor modifications are made.
 */
#define CONFIG_SYS_8313ERDB_BROKEN_PMC 1

#define CONFIG_SYS_ACR_PIPE_DEP	3	/* Arbiter pipeline depth (0-3) */
#define CONFIG_SYS_ACR_RPTCNT		3	/* Arbiter repeat count (0-7) */

/*
 * Device configurations
 */

/* Vitesse 7385 */

#ifdef CONFIG_VSC7385_ENET

#define CONFIG_TSEC1

/* The flash address and size of the VSC7385 firmware image */
#define CONFIG_VSC7385_IMAGE		0xFE7FE000
#define CONFIG_VSC7385_IMAGE_SIZE	8192

#endif

/*
 * DDR Setup
 */
#define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE

/*
 * Manually set up DDR parameters, as this board does not
 * seem to have the SPD connected to I2C.
 */
#define CONFIG_SYS_DDR_SIZE	128		/* MB */
#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
				| CSCONFIG_ODT_RD_NEVER \
				| CSCONFIG_ODT_WR_ONLY_CURRENT \
				| CSCONFIG_ROW_BIT_13 \
				| CSCONFIG_COL_BIT_10)
				/* 0x80010102 */

#define CONFIG_SYS_DDR_TIMING_3	0x00000000
#define CONFIG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
				| (0 << TIMING_CFG0_WRT_SHIFT) \
				| (0 << TIMING_CFG0_RRT_SHIFT) \
				| (0 << TIMING_CFG0_WWT_SHIFT) \
				| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
				| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
				| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
				| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
				/* 0x00220802 */
#define CONFIG_SYS_DDR_TIMING_1	((3 << TIMING_CFG1_PRETOACT_SHIFT) \
				| (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \
				| (3 << TIMING_CFG1_ACTTORW_SHIFT) \
				| (5 << TIMING_CFG1_CASLAT_SHIFT) \
				| (10 << TIMING_CFG1_REFREC_SHIFT) \
				| (3 << TIMING_CFG1_WRREC_SHIFT) \
				| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
				| (2 << TIMING_CFG1_WRTORD_SHIFT))
				/* 0x3835a322 */
#define CONFIG_SYS_DDR_TIMING_2	((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
				| (5 << TIMING_CFG2_CPO_SHIFT) \
				| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
				| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
				| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
				| (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
				/* 0x129048c6 */ /* P9-45,may need tuning */
#define CONFIG_SYS_DDR_INTERVAL	((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \
				| (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
				/* 0x05100500 */
#if defined(CONFIG_DDR_2T_TIMING)
#define CONFIG_SYS_SDRAM_CFG	(SDRAM_CFG_SREN \
				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
				| SDRAM_CFG_DBW_32 \
				| SDRAM_CFG_2T_EN)
				/* 0x43088000 */
#else
#define CONFIG_SYS_SDRAM_CFG	(SDRAM_CFG_SREN \
				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
				| SDRAM_CFG_DBW_32)
				/* 0x43080000 */
#endif
#define CONFIG_SYS_SDRAM_CFG2		0x00401000
/* set burst length to 8 for 32-bit data path */
#define CONFIG_SYS_DDR_MODE	((0x4448 << SDRAM_MODE_ESD_SHIFT) \
				| (0x0632 << SDRAM_MODE_SD_SHIFT))
				/* 0x44480632 */
#define CONFIG_SYS_DDR_MODE_2	0x8000C000

#define CONFIG_SYS_DDR_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
				/*0x02000000*/
#define CONFIG_SYS_DDRCDR_VALUE	(DDRCDR_EN \
				| DDRCDR_PZ_NOMZ \
				| DDRCDR_NZ_NOMZ \
				| DDRCDR_M_ODR)

/*
 * FLASH on the Local Bus
 */
#define CONFIG_SYS_FLASH_BASE		0xFE000000	/* start of FLASH   */
#define CONFIG_SYS_FLASH_SIZE		8	/* flash size in MB */
#define CONFIG_SYS_FLASH_PROTECTION	1	/* Use h/w Flash protection. */
#define CONFIG_SYS_FLASH_EMPTY_INFO		/* display empty sectors */

#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE \
					| BR_PS_16	/* 16 bit port */ \
					| BR_MS_GPCM	/* MSEL = GPCM */ \
					| BR_V)		/* valid */
#define CONFIG_SYS_OR0_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
				| OR_GPCM_XACS \
				| OR_GPCM_SCY_9 \
				| OR_GPCM_EHTR \
				| OR_GPCM_EAD)
				/* 0xFF006FF7	TODO SLOW 16 MB flash size */
					/* window base at flash base */
#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
					/* 16 MB window size */
#define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_16MB)

#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	135	/* sectors per device */

#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */

#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \
	!defined(CONFIG_SPL_BUILD)
#define CONFIG_SYS_RAMBOOT
#endif

#define CONFIG_SYS_INIT_RAM_LOCK	1
#define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000	/* Initial RAM addr */
#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in RAM*/

#define CONFIG_SYS_GBL_DATA_OFFSET	\
			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
#define CONFIG_SYS_MONITOR_LEN	(512 * 1024)	/* Reserve 512 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN	(512 * 1024)	/* Reserved for malloc */

/*
 * Local Bus LCRR and LBCR regs
 */
#define CONFIG_SYS_LCRR_EADC	LCRR_EADC_1
#define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_4
#define CONFIG_SYS_LBC_LBCR	(0x00040000 /* TODO */ \
				| (0xFF << LBCR_BMT_SHIFT) \
				| 0xF)	/* 0x0004ff0f */

				/* LB refresh timer prescal, 266MHz/32 */
#define CONFIG_SYS_LBC_MRTPR	0x20000000  /*TODO */

/* drivers/mtd/nand/nand.c */
#define CONFIG_SYS_NAND_BASE		0xE2800000

#define CONFIG_MTD_PARTITION

#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_NAND_FSL_ELBC 1
#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)

#define CONFIG_SYS_BR1_PRELIM	(CONFIG_SYS_NAND_BASE \
				| BR_DECC_CHK_GEN	/* Use HW ECC */ \
				| BR_PS_8		/* 8 bit port */ \
				| BR_MS_FCM		/* MSEL = FCM */ \
				| BR_V)			/* valid */
#define CONFIG_SYS_OR1_PRELIM	\
				(P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
				| OR_FCM_CSCT \
				| OR_FCM_CST \
				| OR_FCM_CHT \
				| OR_FCM_SCY_1 \
				| OR_FCM_TRLX \
				| OR_FCM_EHTR)
				/* 0xFFFF8396 */

/* Still needed for spl_minimal.c */
#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM
#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM

#define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_NAND_BASE
#define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_32KB)

#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM

/* local bus write LED / read status buffer (BCSR) mapping */
#define CONFIG_SYS_BCSR_ADDR		0xFA000000
#define CONFIG_SYS_BCSR_SIZE		(32 * 1024)	/* 0x00008000 */
					/* map at 0xFA000000 on LCS3 */
#define CONFIG_SYS_BR3_PRELIM		(CONFIG_SYS_BCSR_ADDR \
					| BR_PS_8	/* 8 bit port */ \
					| BR_MS_GPCM	/* MSEL = GPCM */ \
					| BR_V)		/* valid */
					/* 0xFA000801 */
#define CONFIG_SYS_OR3_PRELIM		(P2SZ_TO_AM(CONFIG_SYS_BCSR_SIZE) \
					| OR_GPCM_CSNT \
					| OR_GPCM_ACS_DIV2 \
					| OR_GPCM_XACS \
					| OR_GPCM_SCY_15 \
					| OR_GPCM_TRLX_SET \
					| OR_GPCM_EHTR_SET \
					| OR_GPCM_EAD)
					/* 0xFFFF8FF7 */
#define CONFIG_SYS_LBLAWBAR3_PRELIM	CONFIG_SYS_BCSR_ADDR
#define CONFIG_SYS_LBLAWAR3_PRELIM	(LBLAWAR_EN | LBLAWAR_32KB)

/* Vitesse 7385 */

#ifdef CONFIG_VSC7385_ENET

					/* VSC7385 Base address on LCS2 */
#define CONFIG_SYS_VSC7385_BASE		0xF0000000
#define CONFIG_SYS_VSC7385_SIZE		(128 * 1024)	/* 0x00020000 */

#define CONFIG_SYS_BR2_PRELIM		(CONFIG_SYS_VSC7385_BASE \
					| BR_PS_8	/* 8 bit port */ \
					| BR_MS_GPCM	/* MSEL = GPCM */ \
					| BR_V)		/* valid */
#define CONFIG_SYS_OR2_PRELIM		(P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \
					| OR_GPCM_CSNT \
					| OR_GPCM_XACS \
					| OR_GPCM_SCY_15 \
					| OR_GPCM_SETA \
					| OR_GPCM_TRLX_SET \
					| OR_GPCM_EHTR_SET \
					| OR_GPCM_EAD)
					/* 0xFFFE09FF */

					/* Access window base at VSC7385 base */
#define CONFIG_SYS_LBLAWBAR2_PRELIM	CONFIG_SYS_VSC7385_BASE
#define CONFIG_SYS_LBLAWAR2_PRELIM	(LBLAWAR_EN | LBLAWAR_128KB)

#endif

#define CONFIG_MPC83XX_GPIO 1

/*
 * Serial Port
 */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1

#define CONFIG_SYS_BAUDRATE_TABLE	\
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	400000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
#define CONFIG_SYS_FSL_I2C2_SPEED	400000
#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }

/*
 * General PCI
 * Addresses are mapped 1-1.
 */
#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCI1_IO_BASE	0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS	0xE2000000
#define CONFIG_SYS_PCI1_IO_SIZE	0x00100000	/* 1M */

#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057	/* Motorola */

/*
 * TSEC
 */

#define CONFIG_GMII			/* MII PHY management */

#ifdef CONFIG_TSEC1
#define CONFIG_HAS_ETH0
#define CONFIG_TSEC1_NAME	"TSEC0"
#define CONFIG_SYS_TSEC1_OFFSET	0x24000
#define TSEC1_PHY_ADDR		0x1c
#define TSEC1_FLAGS		TSEC_GIGABIT
#define TSEC1_PHYIDX		0
#endif

#ifdef CONFIG_TSEC2
#define CONFIG_HAS_ETH1
#define CONFIG_TSEC2_NAME	"TSEC1"
#define CONFIG_SYS_TSEC2_OFFSET	0x25000
#define TSEC2_PHY_ADDR		4
#define TSEC2_FLAGS		TSEC_GIGABIT
#define TSEC2_PHYIDX		0
#endif

/* Options are: TSEC[0-1] */
#define CONFIG_ETHPRIME			"TSEC1"

/*
 * Configure on-board RTC
 */
#define CONFIG_RTC_DS1337
#define CONFIG_SYS_I2C_RTC_ADDR		0x68

/*
 * Environment
 */
#if !defined(CONFIG_SYS_RAMBOOT)
	#define CONFIG_ENV_ADDR		\
			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
	#define CONFIG_ENV_SECT_SIZE	0x10000	/* 64K(one sector) for env */
	#define CONFIG_ENV_SIZE		0x2000

/* Address and size of Redundant Environment Sector */
#else
	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
	#define CONFIG_ENV_SIZE		0x2000
#endif

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE

/*
 * Command line configuration.
 */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */

				/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 256 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
				/* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)
#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */

#define CONFIG_SYS_RCWH_PCIHOST 0x80000000	/* PCIHOST  */

#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))

/* System IO Config */
#define CONFIG_SYS_SICRH	(SICRH_TSOBI1 | SICRH_TSOBI2)	/* RGMII */
			/* Enable Internal USB Phy and GPIO on LCD Connector */
#define CONFIG_SYS_SICRL	(SICRL_USBDR_10 | SICRL_LBC)

#define CONFIG_SYS_HID0_INIT	0x000000000
#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
				 HID0_ENABLE_INSTRUCTION_CACHE | \
				 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)

#define CONFIG_SYS_HID2 HID2_HBE

/*
 * Environment Configuration
 */
#define CONFIG_ENV_OVERWRITE

#define CONFIG_NETDEV		"eth1"

#define CONFIG_HOSTNAME		"mpc8313erdb"
#define CONFIG_ROOTPATH		"/nfs/root/path"
#define CONFIG_BOOTFILE		"uImage"
				/* U-Boot image on TFTP server */
#define CONFIG_UBOOTPATH	"u-boot.bin"
#define CONFIG_FDTFILE		"mpc8313erdb.dtb"

				/* default location for tftp and bootm */
#define CONFIG_LOADADDR		800000

#define CONFIG_EXTRA_ENV_SETTINGS \
	"netdev=" CONFIG_NETDEV "\0"					\
	"ethprime=TSEC1\0"						\
	"uboot=" CONFIG_UBOOTPATH "\0"					\
	"tftpflash=tftpboot $loadaddr $uboot; "				\
		"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
			" +$filesize; "	\
		"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
			" +$filesize; "	\
		"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
			" $filesize; "	\
		"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
			" +$filesize; "	\
		"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
			" $filesize\0"	\
	"fdtaddr=780000\0"						\
	"fdtfile=" CONFIG_FDTFILE "\0"					\
	"console=ttyS0\0"						\
	"setbootargs=setenv bootargs "					\
		"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
	"setipargs=setenv bootargs nfsroot=$serverip:$rootpath "	 \
		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
							"$netdev:off " \
		"root=$rootdev rw console=$console,$baudrate $othbootargs\0"

#define CONFIG_NFSBOOTCOMMAND						\
	"setenv rootdev /dev/nfs;"					\
	"run setbootargs;"						\
	"run setipargs;"						\
	"tftp $loadaddr $bootfile;"					\
	"tftp $fdtaddr $fdtfile;"					\
	"bootm $loadaddr - $fdtaddr"

#define CONFIG_RAMBOOTCOMMAND						\
	"setenv rootdev /dev/ram;"					\
	"run setbootargs;"						\
	"tftp $ramdiskaddr $ramdiskfile;"				\
	"tftp $loadaddr $bootfile;"					\
	"tftp $fdtaddr $fdtfile;"					\
	"bootm $loadaddr $ramdiskaddr $fdtaddr"

#endif	/* __CONFIG_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
96b8a054	2	/*
e8d3ca8b	3	* Copyright (C) Freescale Semiconductor, Inc. 2006, 2010.
96b8a054 SW	4	*/
	5	/*
	6	* mpc8313epb board configuration file
	7	*/
	8
	9	#ifndef __CONFIG_H
	10	#define __CONFIG_H
	11
	12	/*
	13	* High Level Configuration Options
	14	*/
	15	#define CONFIG_E300 1
96b8a054	16
f1c574d4 SW	17	#ifndef CONFIG_SYS_MONITOR_BASE
	18	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
	19	#endif
	20
842033e6	21	#define CONFIG_PCI_INDIRECT_BRIDGE
0914f483	22	#define CONFIG_FSL_ELBC 1
96b8a054	23
89c7784e TT	24	/*
89c7784e TT	25	* On-board devices
4ce1e23b YS	26	*
	27	* TSEC1 is VSC switch
	28	* TSEC2 is SoC TSEC
89c7784e TT	29	*/
89c7784e TT	30	#define CONFIG_VSC7385_ENET
4ce1e23b	31	#define CONFIG_TSEC2
89c7784e	32
6d0f6bcf	33	#define CONFIG_SYS_IMMR 0xE0000000
96b8a054	34
6d0f6bcf JCPV	35	#define CONFIG_SYS_MEMTEST_START 0x00001000
6d0f6bcf JCPV	36	#define CONFIG_SYS_MEMTEST_END 0x07f00000
96b8a054 SW	37
	38	/* Early revs of this board will lock up hard when attempting
	39	* to access the PMC registers, unless a JTAG debugger is
	40	* connected, or some resistor modifications are made.
	41	*/
6d0f6bcf	42	#define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
96b8a054	43
6d0f6bcf JCPV	44	#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
6d0f6bcf JCPV	45	#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
96b8a054	46
89c7784e TT	47	/*
	48	* Device configurations
	49	*/
	50
	51	/* Vitesse 7385 */
	52
	53	#ifdef CONFIG_VSC7385_ENET
	54
4ce1e23b	55	#define CONFIG_TSEC1
89c7784e TT	56
	57	/* The flash address and size of the VSC7385 firmware image */
	58	#define CONFIG_VSC7385_IMAGE 0xFE7FE000
	59	#define CONFIG_VSC7385_IMAGE_SIZE 8192
	60
	61	#endif
	62
96b8a054 SW	63	/*
	64	* DDR Setup
	65	*/
261c07bc	66	#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
6d0f6bcf JCPV	67	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
6d0f6bcf JCPV	68	#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
96b8a054 SW	69
	70	/*
	71	* Manually set up DDR parameters, as this board does not
	72	* seem to have the SPD connected to I2C.
	73	*/
261c07bc	74	#define CONFIG_SYS_DDR_SIZE 128 /* MB */
2e651b24	75	#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
2fef4020 JH	76	\| CSCONFIG_ODT_RD_NEVER \
2fef4020 JH	77	\| CSCONFIG_ODT_WR_ONLY_CURRENT \
261c07bc JH	78	\| CSCONFIG_ROW_BIT_13 \
261c07bc JH	79	\| CSCONFIG_COL_BIT_10)
e1d8ed2c	80	/* 0x80010102 */
96b8a054	81
6d0f6bcf	82	#define CONFIG_SYS_DDR_TIMING_3 0x00000000
261c07bc JH	83	#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
	84	\| (0 << TIMING_CFG0_WRT_SHIFT) \
	85	\| (0 << TIMING_CFG0_RRT_SHIFT) \
	86	\| (0 << TIMING_CFG0_WWT_SHIFT) \
	87	\| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
	88	\| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
	89	\| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
	90	\| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
96b8a054	91	/* 0x00220802 */
261c07bc JH	92	#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
	93	\| (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \
	94	\| (3 << TIMING_CFG1_ACTTORW_SHIFT) \
	95	\| (5 << TIMING_CFG1_CASLAT_SHIFT) \
	96	\| (10 << TIMING_CFG1_REFREC_SHIFT) \
	97	\| (3 << TIMING_CFG1_WRREC_SHIFT) \
	98	\| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
	99	\| (2 << TIMING_CFG1_WRTORD_SHIFT))
e1d8ed2c	100	/* 0x3835a322 */
261c07bc JH	101	#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
	102	\| (5 << TIMING_CFG2_CPO_SHIFT) \
	103	\| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
	104	\| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
	105	\| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
	106	\| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
	107	\| (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
e1d8ed2c	108	/* 0x129048c6 / / P9-45,may need tuning */
261c07bc JH	109	#define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \
261c07bc JH	110	\| (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
e1d8ed2c	111	/* 0x05100500 */
96b8a054	112	#if defined(CONFIG_DDR_2T_TIMING)
261c07bc	113	#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
bbea46f7	114	\| SDRAM_CFG_SDRAM_TYPE_DDR2 \
2fef4020 JH	115	\| SDRAM_CFG_DBW_32 \
	116	\| SDRAM_CFG_2T_EN)
	117	/* 0x43088000 */
96b8a054	118	#else
261c07bc	119	#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
bbea46f7	120	\| SDRAM_CFG_SDRAM_TYPE_DDR2 \
2fef4020	121	\| SDRAM_CFG_DBW_32)
96b8a054 SW	122	/* 0x43080000 */
96b8a054 SW	123	#endif
6d0f6bcf	124	#define CONFIG_SYS_SDRAM_CFG2 0x00401000
96b8a054	125	/* set burst length to 8 for 32-bit data path */
261c07bc JH	126	#define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
261c07bc JH	127	\| (0x0632 << SDRAM_MODE_SD_SHIFT))
e1d8ed2c	128	/* 0x44480632 */
261c07bc	129	#define CONFIG_SYS_DDR_MODE_2 0x8000C000
96b8a054	130
6d0f6bcf	131	#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
96b8a054	132	/0x02000000/
261c07bc	133	#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
96b8a054 SW	134	\| DDRCDR_PZ_NOMZ \
96b8a054 SW	135	\| DDRCDR_NZ_NOMZ \
261c07bc	136	\| DDRCDR_M_ODR)
96b8a054 SW	137
	138	/*
	139	* FLASH on the Local Bus
	140	*/
6d0f6bcf	141	#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
261c07bc	142	#define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */
16aaca21	143	#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
261c07bc	144	#define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
261c07bc	145
16aaca21	146	#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
7d6a0982 JH	147	\| BR_PS_16 /* 16 bit port */ \
	148	\| BR_MS_GPCM /* MSEL = GPCM */ \
	149	\| BR_V) /* valid */
16aaca21	150	#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
96b8a054 SW	151	\| OR_GPCM_XACS \
	152	\| OR_GPCM_SCY_9 \
	153	\| OR_GPCM_EHTR \
261c07bc	154	\| OR_GPCM_EAD)
96b8a054	155	/* 0xFF006FF7 TODO SLOW 16 MB flash size */
261c07bc JH	156	/* window base at flash base */
261c07bc JH	157	#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
7d6a0982 JH	158	/* 16 MB window size */
7d6a0982 JH	159	#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN \| LBLAWAR_16MB)
96b8a054	160
261c07bc JH	161	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
261c07bc JH	162	#define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */
96b8a054	163
6d0f6bcf JCPV	164	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
6d0f6bcf JCPV	165	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
96b8a054	166
261c07bc	167	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \
22f4442d	168	!defined(CONFIG_SPL_BUILD)
6d0f6bcf	169	#define CONFIG_SYS_RAMBOOT
96b8a054 SW	170	#endif
96b8a054 SW	171
6d0f6bcf	172	#define CONFIG_SYS_INIT_RAM_LOCK 1
261c07bc JH	173	#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
261c07bc JH	174	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
96b8a054	175
261c07bc JH	176	#define CONFIG_SYS_GBL_DATA_OFFSET \
261c07bc JH	177	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	178	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
96b8a054	179
6d0f6bcf	180	/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
16c8c170	181	#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
261c07bc	182	#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
96b8a054 SW	183
	184	/*
	185	* Local Bus LCRR and LBCR regs
	186	*/
c7190f02 KP	187	#define CONFIG_SYS_LCRR_EADC LCRR_EADC_1
c7190f02 KP	188	#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
261c07bc JH	189	#define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \
	190	\| (0xFF << LBCR_BMT_SHIFT) \
	191	\| 0xF) /* 0x0004ff0f */
96b8a054	192
261c07bc JH	193	/* LB refresh timer prescal, 266MHz/32 */
261c07bc JH	194	#define CONFIG_SYS_LBC_MRTPR 0x20000000 /TODO /
96b8a054	195
16aaca21	196	/* drivers/mtd/nand/nand.c */
6d0f6bcf	197	#define CONFIG_SYS_NAND_BASE 0xE2800000
e4c09508	198
e8d3ca8b	199	#define CONFIG_MTD_PARTITION
e8d3ca8b	200
6d0f6bcf	201	#define CONFIG_SYS_MAX_NAND_DEVICE 1
acdab5c3	202	#define CONFIG_NAND_FSL_ELBC 1
6d0f6bcf	203	#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
7d6a0982	204	#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
e4c09508	205
16aaca21	206	#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \
7d6a0982	207	\| BR_DECC_CHK_GEN /* Use HW ECC */ \
261c07bc	208	\| BR_PS_8 /* 8 bit port */ \
a7676ea7	209	\| BR_MS_FCM /* MSEL = FCM */ \
261c07bc	210	\| BR_V) /* valid */
16aaca21	211	#define CONFIG_SYS_OR1_PRELIM \
7d6a0982	212	(P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
96b8a054 SW	213	\| OR_FCM_CSCT \
	214	\| OR_FCM_CST \
	215	\| OR_FCM_CHT \
	216	\| OR_FCM_SCY_1 \
	217	\| OR_FCM_TRLX \
261c07bc	218	\| OR_FCM_EHTR)
96b8a054	219	/* 0xFFFF8396 */
e4c09508	220
16aaca21 MS	221	/* Still needed for spl_minimal.c */
	222	#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM
	223	#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
e4c09508	224
6d0f6bcf	225	#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
7d6a0982	226	#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN \| LBLAWAR_32KB)
96b8a054	227
6d0f6bcf JCPV	228	#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
6d0f6bcf JCPV	229	#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
e4c09508	230
7d6a0982 JH	231	/* local bus write LED / read status buffer (BCSR) mapping */
	232	#define CONFIG_SYS_BCSR_ADDR 0xFA000000
	233	#define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */
	234	/* map at 0xFA000000 on LCS3 */
	235	#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_BCSR_ADDR \
	236	\| BR_PS_8 /* 8 bit port */ \
	237	\| BR_MS_GPCM /* MSEL = GPCM */ \
	238	\| BR_V) /* valid */
	239	/* 0xFA000801 */
	240	#define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BCSR_SIZE) \
	241	\| OR_GPCM_CSNT \
	242	\| OR_GPCM_ACS_DIV2 \
	243	\| OR_GPCM_XACS \
	244	\| OR_GPCM_SCY_15 \
	245	\| OR_GPCM_TRLX_SET \
	246	\| OR_GPCM_EHTR_SET \
	247	\| OR_GPCM_EAD)
	248	/* 0xFFFF8FF7 */
	249	#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_BCSR_ADDR
	250	#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN \| LBLAWAR_32KB)
89c7784e TT	251
	252	/* Vitesse 7385 */
	253
89c7784e TT	254	#ifdef CONFIG_VSC7385_ENET
89c7784e TT	255
7d6a0982 JH	256	/* VSC7385 Base address on LCS2 */
	257	#define CONFIG_SYS_VSC7385_BASE 0xF0000000
	258	#define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */
	259
	260	#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \
	261	\| BR_PS_8 /* 8 bit port */ \
	262	\| BR_MS_GPCM /* MSEL = GPCM */ \
	263	\| BR_V) /* valid */
	264	#define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \
	265	\| OR_GPCM_CSNT \
	266	\| OR_GPCM_XACS \
	267	\| OR_GPCM_SCY_15 \
	268	\| OR_GPCM_SETA \
	269	\| OR_GPCM_TRLX_SET \
	270	\| OR_GPCM_EHTR_SET \
	271	\| OR_GPCM_EAD)
	272	/* 0xFFFE09FF */
	273
261c07bc JH	274	/* Access window base at VSC7385 base */
261c07bc JH	275	#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE
7d6a0982	276	#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN \| LBLAWAR_128KB)
96b8a054	277
89c7784e	278	#endif
96b8a054	279
0eaf8f9e	280	#define CONFIG_MPC83XX_GPIO 1
0eaf8f9e	281
96b8a054 SW	282	/*
	283	* Serial Port
	284	*/
6d0f6bcf JCPV	285	#define CONFIG_SYS_NS16550_SERIAL
6d0f6bcf JCPV	286	#define CONFIG_SYS_NS16550_REG_SIZE 1
96b8a054	287
6d0f6bcf	288	#define CONFIG_SYS_BAUDRATE_TABLE \
96b8a054 SW	289	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
96b8a054 SW	290
6d0f6bcf JCPV	291	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
6d0f6bcf JCPV	292	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
96b8a054	293
96b8a054	294	/* I2C */
00f792e0 HS	295	#define CONFIG_SYS_I2C
	296	#define CONFIG_SYS_I2C_FSL
	297	#define CONFIG_SYS_FSL_I2C_SPEED 400000
	298	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	299	#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
	300	#define CONFIG_SYS_FSL_I2C2_SPEED 400000
	301	#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
	302	#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
	303	#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
96b8a054	304
96b8a054 SW	305	/*
	306	* General PCI
	307	* Addresses are mapped 1-1.
	308	*/
6d0f6bcf JCPV	309	#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
	310	#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
	311	#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
	312	#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
	313	#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
	314	#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
	315	#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
	316	#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
	317	#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
96b8a054	318
6d0f6bcf	319	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
96b8a054 SW	320
96b8a054 SW	321	/*
89c7784e	322	* TSEC
96b8a054	323	*/
96b8a054	324
89c7784e	325	#define CONFIG_GMII /* MII PHY management */
96b8a054	326
89c7784e TT	327	#ifdef CONFIG_TSEC1
89c7784e TT	328	#define CONFIG_HAS_ETH0
255a3577	329	#define CONFIG_TSEC1_NAME "TSEC0"
6d0f6bcf	330	#define CONFIG_SYS_TSEC1_OFFSET 0x24000
89c7784e TT	331	#define TSEC1_PHY_ADDR 0x1c
	332	#define TSEC1_FLAGS TSEC_GIGABIT
	333	#define TSEC1_PHYIDX 0
	334	#endif
	335
	336	#ifdef CONFIG_TSEC2
	337	#define CONFIG_HAS_ETH1
255a3577	338	#define CONFIG_TSEC2_NAME "TSEC1"
6d0f6bcf	339	#define CONFIG_SYS_TSEC2_OFFSET 0x25000
89c7784e TT	340	#define TSEC2_PHY_ADDR 4
	341	#define TSEC2_FLAGS TSEC_GIGABIT
	342	#define TSEC2_PHYIDX 0
	343	#endif
	344
96b8a054 SW	345	/* Options are: TSEC[0-1] */
	346	#define CONFIG_ETHPRIME "TSEC1"
	347
	348	/*
	349	* Configure on-board RTC
	350	*/
	351	#define CONFIG_RTC_DS1337
6d0f6bcf	352	#define CONFIG_SYS_I2C_RTC_ADDR 0x68
96b8a054 SW	353
	354	/*
	355	* Environment
	356	*/
16aaca21	357	#if !defined(CONFIG_SYS_RAMBOOT)
261c07bc JH	358	#define CONFIG_ENV_ADDR \
261c07bc JH	359	(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
0e8d1586 JCPV	360	#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
0e8d1586 JCPV	361	#define CONFIG_ENV_SIZE 0x2000
96b8a054 SW	362
	363	/* Address and size of Redundant Environment Sector */
	364	#else
6d0f6bcf	365	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
0e8d1586	366	#define CONFIG_ENV_SIZE 0x2000
96b8a054 SW	367	#endif
	368
	369	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	370	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
96b8a054	371
079a136c JL	372	/*
	373	* BOOTP options
	374	*/
	375	#define CONFIG_BOOTP_BOOTFILESIZE
079a136c	376
8ea5499a JL	377	/*
	378	* Command line configuration.
	379	*/
96b8a054	380
96b8a054 SW	381	/*
	382	* Miscellaneous configurable options
	383	*/
6d0f6bcf	384	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
6d0f6bcf	385	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
96b8a054	386
261c07bc JH	387	/* Boot Argument Buffer Size */
261c07bc JH	388	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
96b8a054 SW	389
	390	/*
	391	* For booting Linux, the board info and command line data
9f530d59	392	* have to be in the first 256 MB of memory, since this is
96b8a054 SW	393	* the maximum mapped by the Linux kernel during initialization.
96b8a054 SW	394	*/
261c07bc JH	395	/* Initial Memory map for Linux*/
261c07bc JH	396	#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
63865278	397	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
96b8a054	398
6d0f6bcf	399	#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
96b8a054	400
ff3bb0c4	401	#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
96b8a054 SW	402
96b8a054 SW	403	/* System IO Config */
6d0f6bcf	404	#define CONFIG_SYS_SICRH (SICRH_TSOBI1 \| SICRH_TSOBI2) /* RGMII */
0eaf8f9e JH	405	/* Enable Internal USB Phy and GPIO on LCD Connector */
0eaf8f9e JH	406	#define CONFIG_SYS_SICRL (SICRL_USBDR_10 \| SICRL_LBC)
96b8a054	407
6d0f6bcf JCPV	408	#define CONFIG_SYS_HID0_INIT 0x000000000
6d0f6bcf JCPV	409	#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \| \
1a2e203b KP	410	HID0_ENABLE_INSTRUCTION_CACHE \| \
1a2e203b KP	411	HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
96b8a054	412
6d0f6bcf	413	#define CONFIG_SYS_HID2 HID2_HBE
96b8a054	414
96b8a054 SW	415	/*
	416	* Environment Configuration
	417	*/
	418	#define CONFIG_ENV_OVERWRITE
	419
261c07bc	420	#define CONFIG_NETDEV "eth1"
96b8a054	421
5bc0543d	422	#define CONFIG_HOSTNAME "mpc8313erdb"
8b3637c6	423	#define CONFIG_ROOTPATH "/nfs/root/path"
b3f44c21	424	#define CONFIG_BOOTFILE "uImage"
261c07bc JH	425	/* U-Boot image on TFTP server */
	426	#define CONFIG_UBOOTPATH "u-boot.bin"
	427	#define CONFIG_FDTFILE "mpc8313erdb.dtb"
96b8a054	428
261c07bc JH	429	/* default location for tftp and bootm */
261c07bc JH	430	#define CONFIG_LOADADDR 800000
96b8a054	431
96b8a054	432	#define CONFIG_EXTRA_ENV_SETTINGS \
261c07bc	433	"netdev=" CONFIG_NETDEV "\0" \
96b8a054	434	"ethprime=TSEC1\0" \
261c07bc	435	"uboot=" CONFIG_UBOOTPATH "\0" \
53677ef1	436	"tftpflash=tftpboot $loadaddr $uboot; " \
5368c55d MV	437	"protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
	438	" +$filesize; " \
	439	"erase " __stringify(CONFIG_SYS_TEXT_BASE) \
	440	" +$filesize; " \
	441	"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
	442	" $filesize; " \
	443	"protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
	444	" +$filesize; " \
	445	"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
	446	" $filesize\0" \
79f516bc	447	"fdtaddr=780000\0" \
261c07bc	448	"fdtfile=" CONFIG_FDTFILE "\0" \
96b8a054 SW	449	"console=ttyS0\0" \
	450	"setbootargs=setenv bootargs " \
	451	"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
53677ef1	452	"setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
261c07bc JH	453	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
261c07bc JH	454	"$netdev:off " \
96b8a054 SW	455	"root=$rootdev rw console=$console,$baudrate $othbootargs\0"
	456
	457	#define CONFIG_NFSBOOTCOMMAND \
	458	"setenv rootdev /dev/nfs;" \
53677ef1 WD	459	"run setbootargs;" \
53677ef1 WD	460	"run setipargs;" \
96b8a054 SW	461	"tftp $loadaddr $bootfile;" \
	462	"tftp $fdtaddr $fdtfile;" \
	463	"bootm $loadaddr - $fdtaddr"
	464
	465	#define CONFIG_RAMBOOTCOMMAND \
	466	"setenv rootdev /dev/ram;" \
	467	"run setbootargs;" \
	468	"tftp $ramdiskaddr $ramdiskfile;" \
	469	"tftp $loadaddr $bootfile;" \
	470	"tftp $fdtaddr $fdtfile;" \
	471	"bootm $loadaddr $ramdiskaddr $fdtaddr"
	472
96b8a054	473	#endif /* __CONFIG_H */