[J-u-boot.git] / include / configs / MPC8308RDB.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
 * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, [email protected]
 *
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_E300		1 /* E300 family */

#ifdef CONFIG_MMC
#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC83xx_ESDHC_ADDR
#define CONFIG_SYS_FSL_ESDHC_USE_PIO
#endif

/*
 * On-board devices
 *
 * TSEC1 is SoC TSEC
 * TSEC2 is VSC switch
 */
#define CONFIG_TSEC1
#define CONFIG_VSC7385_ENET

/*
 * System IO Config
 */
#define CONFIG_SYS_SICRH (\
	SICRH_ESDHC_A_SD |\
	SICRH_ESDHC_B_SD |\
	SICRH_ESDHC_C_SD |\
	SICRH_GPIO_A_TSEC2 |\
	SICRH_GPIO_B_TSEC2_GTX_CLK125 |\
	SICRH_IEEE1588_A_GPIO |\
	SICRH_USB |\
	SICRH_GTM_GPIO |\
	SICRH_IEEE1588_B_GPIO |\
	SICRH_ETSEC2_CRS |\
	SICRH_GPIOSEL_1 |\
	SICRH_TMROBI_V3P3 |\
	SICRH_TSOBI1_V2P5 |\
	SICRH_TSOBI2_V2P5)	/* 0x01b7d103 */
#define CONFIG_SYS_SICRL (\
	SICRL_SPI_PF0 |\
	SICRL_UART_PF0 |\
	SICRL_IRQ_PF0 |\
	SICRL_I2C2_PF0 |\
	SICRL_ETSEC1_GTX_CLK125)	/* 0x00000040 */

/*
 * IMMR new address
 */
#define CONFIG_SYS_IMMR		0xE0000000

/*
 * SERDES
 */
#define CONFIG_FSL_SERDES
#define CONFIG_FSL_SERDES1	0xe3000

/*
 * Arbiter Setup
 */
#define CONFIG_SYS_ACR_PIPE_DEP	3 /* Arbiter pipeline depth is 4 */
#define CONFIG_SYS_ACR_RPTCNT	3 /* Arbiter repeat count is 4 */
#define CONFIG_SYS_SPCR_TSECEP	3 /* eTSEC emergency priority is highest */

/*
 * DDR Setup
 */
#define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory */
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
#define CONFIG_SYS_DDRCDR_VALUE	(DDRCDR_EN \
				| DDRCDR_PZ_LOZ \
				| DDRCDR_NZ_LOZ \
				| DDRCDR_ODT \
				| DDRCDR_Q_DRN)
				/* 0x7b880001 */
/*
 * Manually set up DDR parameters
 * consist of two chips HY5PS12621BFP-C4 from HYNIX
 */

#define CONFIG_SYS_DDR_SIZE		128 /* MB */

#define CONFIG_SYS_DDR_CS0_BNDS	0x00000007
#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
				| CSCONFIG_ODT_RD_NEVER \
				| CSCONFIG_ODT_WR_ONLY_CURRENT \
				| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
				/* 0x80010102 */
#define CONFIG_SYS_DDR_TIMING_3	0x00000000
#define CONFIG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
				| (0 << TIMING_CFG0_WRT_SHIFT) \
				| (0 << TIMING_CFG0_RRT_SHIFT) \
				| (0 << TIMING_CFG0_WWT_SHIFT) \
				| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
				| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
				| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
				| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
				/* 0x00220802 */
#define CONFIG_SYS_DDR_TIMING_1	((2 << TIMING_CFG1_PRETOACT_SHIFT) \
				| (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
				| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
				| (5 << TIMING_CFG1_CASLAT_SHIFT) \
				| (6 << TIMING_CFG1_REFREC_SHIFT) \
				| (2 << TIMING_CFG1_WRREC_SHIFT) \
				| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
				| (2 << TIMING_CFG1_WRTORD_SHIFT))
				/* 0x27256222 */
#define CONFIG_SYS_DDR_TIMING_2	((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
				| (4 << TIMING_CFG2_CPO_SHIFT) \
				| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
				| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
				| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
				| (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
				/* 0x121048c5 */
#define CONFIG_SYS_DDR_INTERVAL	((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
				| (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
				/* 0x03600100 */
#define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SREN \
				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
				| SDRAM_CFG_DBW_32)
				/* 0x43080000 */

#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000 /* 1 posted refresh */
#define CONFIG_SYS_DDR_MODE		((0x0448 << SDRAM_MODE_ESD_SHIFT) \
				| (0x0232 << SDRAM_MODE_SD_SHIFT))
				/* ODT 150ohm CL=3, AL=1 on SDRAM */
#define CONFIG_SYS_DDR_MODE2		0x00000000

/*
 * Memory test
 */
#define CONFIG_SYS_MEMTEST_START	0x00001000 /* memtest region */
#define CONFIG_SYS_MEMTEST_END		0x07f00000

/*
 * The reserved memory
 */
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE /* start of monitor */

#define CONFIG_SYS_MONITOR_LEN	(512 * 1024) /* Reserve 512 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN	(512 * 1024) /* Reserved for malloc */

/*
 * Initial RAM Base Address Setup
 */
#define CONFIG_SYS_INIT_RAM_LOCK	1
#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM */
#define CONFIG_SYS_GBL_DATA_OFFSET	\
	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)

/*
 * Local Bus Configuration & Clock Setup
 */
#define CONFIG_SYS_LCRR_DBYP		LCRR_DBYP
#define CONFIG_SYS_LCRR_CLKDIV		LCRR_CLKDIV_2
#define CONFIG_SYS_LBC_LBCR		0x00040000

/*
 * FLASH on the Local Bus
 */
#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT

#define CONFIG_SYS_FLASH_BASE		0xFE000000 /* FLASH base address */
#define CONFIG_SYS_FLASH_SIZE		8 /* FLASH size is 8M */

/* Window base at flash base */
#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_8MB)

#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE \
				| BR_PS_16	/* 16 bit port */ \
				| BR_MS_GPCM	/* MSEL = GPCM */ \
				| BR_V)		/* valid */
#define CONFIG_SYS_OR0_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
				| OR_UPM_XAM \
				| OR_GPCM_CSNT \
				| OR_GPCM_ACS_DIV2 \
				| OR_GPCM_XACS \
				| OR_GPCM_SCY_15 \
				| OR_GPCM_TRLX_SET \
				| OR_GPCM_EHTR_SET)

#define CONFIG_SYS_MAX_FLASH_BANKS	1 /* number of banks */
/* 127 64KB sectors and 8 8KB top sectors per device */
#define CONFIG_SYS_MAX_FLASH_SECT	135

#define CONFIG_SYS_FLASH_ERASE_TOUT	60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500 /* Flash Write Timeout (ms) */

/*
 * NAND Flash on the Local Bus
 */
#define CONFIG_SYS_NAND_BASE	0xE0600000		/* 0xE0600000 */
#define CONFIG_SYS_NAND_WINDOW_SIZE	(32 * 1024)	/* 0x00008000 */
#define CONFIG_SYS_BR1_PRELIM	(CONFIG_SYS_NAND_BASE \
				| BR_DECC_CHK_GEN	/* Use HW ECC */ \
				| BR_PS_8		/* 8 bit Port */ \
				| BR_MS_FCM		/* MSEL = FCM */ \
				| BR_V)			/* valid */
#define CONFIG_SYS_OR1_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
				| OR_FCM_CSCT \
				| OR_FCM_CST \
				| OR_FCM_CHT \
				| OR_FCM_SCY_1 \
				| OR_FCM_TRLX \
				| OR_FCM_EHTR)
				/* 0xFFFF8396 */

#define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_NAND_BASE
#define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_32KB)

#ifdef CONFIG_VSC7385_ENET
#define CONFIG_TSEC2
					/* VSC7385 Base address on CS2 */
#define CONFIG_SYS_VSC7385_BASE		0xF0000000
#define CONFIG_SYS_VSC7385_SIZE		(128 * 1024) /* 0x00020000 */
#define CONFIG_SYS_BR2_PRELIM		(CONFIG_SYS_VSC7385_BASE \
					| BR_PS_8	/* 8-bit port */ \
					| BR_MS_GPCM	/* MSEL = GPCM */ \
					| BR_V)		/* valid */
					/* 0xF0000801 */
#define CONFIG_SYS_OR2_PRELIM		(P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \
					| OR_GPCM_CSNT \
					| OR_GPCM_XACS \
					| OR_GPCM_SCY_15 \
					| OR_GPCM_SETA \
					| OR_GPCM_TRLX_SET \
					| OR_GPCM_EHTR_SET)
					/* 0xFFFE09FF */
/* Access window base at VSC7385 base */
#define CONFIG_SYS_LBLAWBAR2_PRELIM	CONFIG_SYS_VSC7385_BASE
/* Access window size 128K */
#define CONFIG_SYS_LBLAWAR2_PRELIM	(LBLAWAR_EN | LBLAWAR_128KB)
/* The flash address and size of the VSC7385 firmware image */
#define CONFIG_VSC7385_IMAGE		0xFE7FE000
#define CONFIG_VSC7385_IMAGE_SIZE	8192
#endif
/*
 * Serial Port
 */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#define CONFIG_SYS_BAUDRATE_TABLE  \
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR + 0x4500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR + 0x4600)

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	400000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
#define CONFIG_SYS_FSL_I2C2_SPEED	400000
#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x51} }

/*
 * SPI on header J8
 *
 * WARNING: enabling this will break TSEC2 (connected to the Vitesse switch)
 * due to a pinmux conflict between GPIO9 (SPI chip select )and the TSEC2 pins.
 */
#ifdef CONFIG_MPC8XXX_SPI
#define CONFIG_USE_SPIFLASH
#endif

/*
 * Board info - revision and where boot from
 */
#define CONFIG_SYS_I2C_PCF8574A_ADDR	0x39

/*
 * Config on-board RTC
 */
#define CONFIG_RTC_DS1337	/* ds1339 on board, use ds1337 rtc via i2c */
#define CONFIG_SYS_I2C_RTC_ADDR	0x68 /* at address 0x68 */

/*
 * General PCI
 * Addresses are mapped 1-1.
 */
#define CONFIG_SYS_PCIE1_BASE		0xA0000000
#define CONFIG_SYS_PCIE1_MEM_BASE	0xA0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS	0xA0000000
#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000
#define CONFIG_SYS_PCIE1_CFG_BASE	0xB0000000
#define CONFIG_SYS_PCIE1_CFG_SIZE	0x01000000
#define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
#define CONFIG_SYS_PCIE1_IO_PHYS	0xB1000000
#define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000

/* enable PCIE clock */
#define CONFIG_SYS_SCCR_PCIEXP1CM	1

#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCIE

#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1

/*
 * TSEC
 */
#define CONFIG_SYS_TSEC1_OFFSET	0x24000
#define CONFIG_SYS_TSEC1	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
#define CONFIG_SYS_TSEC2_OFFSET	0x25000
#define CONFIG_SYS_TSEC2	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)

/*
 * TSEC ethernet configuration
 */
#define CONFIG_TSEC1_NAME	"eTSEC0"
#define CONFIG_TSEC2_NAME	"eTSEC1"
#define TSEC1_PHY_ADDR		2
#define TSEC2_PHY_ADDR		1
#define TSEC1_PHYIDX		0
#define TSEC2_PHYIDX		0
#define TSEC1_FLAGS		TSEC_GIGABIT
#define TSEC2_FLAGS		TSEC_GIGABIT

/* Options are: eTSEC[0-1] */
#define CONFIG_ETHPRIME		"eTSEC0"

/*
 * Environment
 */
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + \
				 CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SECT_SIZE	0x10000 /* 64K(one sector) for env */
#define CONFIG_ENV_SIZE		0x2000
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE

/*
 * Command line configuration.
 */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LOAD_ADDR		0x2000000 /* default load address */

#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size */

/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 256 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(256 << 20) /* Initial Memory map for Linux */
#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */

/*
 * Core HID Setup
 */
#define CONFIG_SYS_HID0_INIT	0x000000000
#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
				 HID0_ENABLE_INSTRUCTION_CACHE | \
				 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
#define CONFIG_SYS_HID2		HID2_HBE

/*
 * Environment Configuration
 */

#define CONFIG_ENV_OVERWRITE

#if defined(CONFIG_TSEC_ENET)
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#endif

#define CONFIG_LOADADDR	800000	/* default location for tftp and bootm */


#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"consoledev=ttyS0\0"						\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"addtty=setenv bootargs ${bootargs}"				\
		" console=${consoledev},${baudrate}\0"			\
	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
	"addmisc=setenv bootargs ${bootargs}\0"				\
	"kernel_addr=FE080000\0"					\
	"fdt_addr=FE280000\0"						\
	"ramdisk_addr=FE290000\0"					\
	"u-boot=mpc8308rdb/u-boot.bin\0"				\
	"kernel_addr_r=1000000\0"					\
	"fdt_addr_r=C00000\0"						\
	"hostname=mpc8308rdb\0"						\
	"bootfile=mpc8308rdb/uImage\0"					\
	"fdtfile=mpc8308rdb/mpc8308rdb.dtb\0"				\
	"rootpath=/opt/eldk-4.2/ppc_6xx\0"				\
	"flash_self=run ramargs addip addtty addmtd addmisc;"		\
		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
	"flash_nfs=run nfsargs addip addtty addmtd addmisc;"		\
		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
	"net_nfs=tftp ${kernel_addr_r} ${bootfile};"			\
		"tftp ${fdt_addr_r} ${fdtfile};"			\
		"run nfsargs addip addtty addmtd addmisc;"		\
		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
	"bootcmd=run flash_self\0"					\
	"load=tftp ${loadaddr} ${u-boot}\0"				\
	"update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)	\
		" +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
		" +${filesize};cp.b ${fileaddr} "			\
		__stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"	\
	"upd=run load update\0"						\

#endif	/* __CONFIG_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
5fb17030 IY	2	/*
	3	* Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
	4	* Copyright (C) 2010 Ilya Yanok, Emcraft Systems, [email protected]
	5	*
5fb17030 IY	6	*/
	7
	8	#ifndef __CONFIG_H
	9	#define __CONFIG_H
	10
	11	/*
	12	* High Level Configuration Options
	13	*/
	14	#define CONFIG_E300 1 /* E300 family */
5fb17030	15
db1fc7d2	16	#ifdef CONFIG_MMC
db1fc7d2	17	#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
db1fc7d2	18	#define CONFIG_SYS_FSL_ESDHC_USE_PIO
db1fc7d2 IS	19	#endif
db1fc7d2 IS	20
5fb17030 IY	21	/*
	22	* On-board devices
	23	*
	24	* TSEC1 is SoC TSEC
	25	* TSEC2 is VSC switch
	26	*/
	27	#define CONFIG_TSEC1
	28	#define CONFIG_VSC7385_ENET
	29
5fb17030 IY	30	/*
	31	* System IO Config
	32	*/
65ea7589 IY	33	#define CONFIG_SYS_SICRH (\
	34	SICRH_ESDHC_A_SD \|\
	35	SICRH_ESDHC_B_SD \|\
	36	SICRH_ESDHC_C_SD \|\
	37	SICRH_GPIO_A_TSEC2 \|\
	38	SICRH_GPIO_B_TSEC2_GTX_CLK125 \|\
	39	SICRH_IEEE1588_A_GPIO \|\
	40	SICRH_USB \|\
	41	SICRH_GTM_GPIO \|\
	42	SICRH_IEEE1588_B_GPIO \|\
	43	SICRH_ETSEC2_CRS \|\
	44	SICRH_GPIOSEL_1 \|\
	45	SICRH_TMROBI_V3P3 \|\
	46	SICRH_TSOBI1_V2P5 \|\
	47	SICRH_TSOBI2_V2P5) /* 0x01b7d103 */
	48	#define CONFIG_SYS_SICRL (\
	49	SICRL_SPI_PF0 \|\
	50	SICRL_UART_PF0 \|\
	51	SICRL_IRQ_PF0 \|\
	52	SICRL_I2C2_PF0 \|\
	53	SICRL_ETSEC1_GTX_CLK125) /* 0x00000040 */
5fb17030 IY	54
	55	/*
	56	* IMMR new address
	57	*/
	58	#define CONFIG_SYS_IMMR 0xE0000000
	59
	60	/*
	61	* SERDES
	62	*/
	63	#define CONFIG_FSL_SERDES
	64	#define CONFIG_FSL_SERDES1 0xe3000
	65
	66	/*
	67	* Arbiter Setup
	68	*/
	69	#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
	70	#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
	71	#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
	72
	73	/*
	74	* DDR Setup
	75	*/
	76	#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
	77	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
	78	#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
	79	#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
	80	#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
	81	\| DDRCDR_PZ_LOZ \
	82	\| DDRCDR_NZ_LOZ \
	83	\| DDRCDR_ODT \
	84	\| DDRCDR_Q_DRN)
	85	/* 0x7b880001 */
	86	/*
	87	* Manually set up DDR parameters
	88	* consist of two chips HY5PS12621BFP-C4 from HYNIX
	89	*/
	90
	91	#define CONFIG_SYS_DDR_SIZE 128 /* MB */
	92
	93	#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
	94	#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
2fef4020 JH	95	\| CSCONFIG_ODT_RD_NEVER \
2fef4020 JH	96	\| CSCONFIG_ODT_WR_ONLY_CURRENT \
5fb17030 IY	97	\| CSCONFIG_ROW_BIT_13 \| CSCONFIG_COL_BIT_10)
	98	/* 0x80010102 */
	99	#define CONFIG_SYS_DDR_TIMING_3 0x00000000
	100	#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
	101	\| (0 << TIMING_CFG0_WRT_SHIFT) \
	102	\| (0 << TIMING_CFG0_RRT_SHIFT) \
	103	\| (0 << TIMING_CFG0_WWT_SHIFT) \
	104	\| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
	105	\| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
	106	\| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
	107	\| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
	108	/* 0x00220802 */
	109	#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
	110	\| (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
	111	\| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
	112	\| (5 << TIMING_CFG1_CASLAT_SHIFT) \
	113	\| (6 << TIMING_CFG1_REFREC_SHIFT) \
	114	\| (2 << TIMING_CFG1_WRREC_SHIFT) \
	115	\| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
	116	\| (2 << TIMING_CFG1_WRTORD_SHIFT))
	117	/* 0x27256222 */
	118	#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
	119	\| (4 << TIMING_CFG2_CPO_SHIFT) \
	120	\| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
	121	\| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
	122	\| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
	123	\| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
	124	\| (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
	125	/* 0x121048c5 */
	126	#define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
	127	\| (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
	128	/* 0x03600100 */
	129	#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
	130	\| SDRAM_CFG_SDRAM_TYPE_DDR2 \
2fef4020	131	\| SDRAM_CFG_DBW_32)
5fb17030 IY	132	/* 0x43080000 */
	133
	134	#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
	135	#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
	136	\| (0x0232 << SDRAM_MODE_SD_SHIFT))
	137	/* ODT 150ohm CL=3, AL=1 on SDRAM */
	138	#define CONFIG_SYS_DDR_MODE2 0x00000000
	139
	140	/*
	141	* Memory test
	142	*/
	143	#define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */
	144	#define CONFIG_SYS_MEMTEST_END 0x07f00000
	145
	146	/*
	147	* The reserved memory
	148	*/
14d0a02a	149	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
5fb17030	150
16c8c170	151	#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
5fb17030 IY	152	#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
	153
	154	/*
	155	* Initial RAM Base Address Setup
	156	*/
	157	#define CONFIG_SYS_INIT_RAM_LOCK 1
	158	#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
34f81968	159	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
5fb17030	160	#define CONFIG_SYS_GBL_DATA_OFFSET \
25ddd1fb	161	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
5fb17030 IY	162
	163	/*
	164	* Local Bus Configuration & Clock Setup
	165	*/
	166	#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
	167	#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
	168	#define CONFIG_SYS_LBC_LBCR 0x00040000
	169
	170	/*
	171	* FLASH on the Local Bus
	172	*/
5fb17030 IY	173	#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
	174
	175	#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
	176	#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */
5fb17030 IY	177
	178	/* Window base at flash base */
	179	#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
65ea7589	180	#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN \| LBLAWAR_8MB)
5fb17030	181
7d6a0982 JH	182	#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
	183	\| BR_PS_16 /* 16 bit port */ \
	184	\| BR_MS_GPCM /* MSEL = GPCM */ \
	185	\| BR_V) /* valid */
	186	#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
5fb17030 IY	187	\| OR_UPM_XAM \
	188	\| OR_GPCM_CSNT \
	189	\| OR_GPCM_ACS_DIV2 \
	190	\| OR_GPCM_XACS \
	191	\| OR_GPCM_SCY_15 \
7d6a0982 JH	192	\| OR_GPCM_TRLX_SET \
7d6a0982 JH	193	\| OR_GPCM_EHTR_SET)
5fb17030 IY	194
	195	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
	196	/* 127 64KB sectors and 8 8KB top sectors per device */
	197	#define CONFIG_SYS_MAX_FLASH_SECT 135
	198
	199	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	200	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
	201
	202	/*
	203	* NAND Flash on the Local Bus
	204	*/
34f81968	205	#define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */
7d6a0982	206	#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) /* 0x00008000 */
34f81968	207	#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \
7d6a0982 JH	208	\| BR_DECC_CHK_GEN /* Use HW ECC */ \
7d6a0982 JH	209	\| BR_PS_8 /* 8 bit Port */ \
5fb17030	210	\| BR_MS_FCM /* MSEL = FCM */ \
34f81968	211	\| BR_V) /* valid */
7d6a0982	212	#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
5fb17030 IY	213	\| OR_FCM_CSCT \
	214	\| OR_FCM_CST \
	215	\| OR_FCM_CHT \
	216	\| OR_FCM_SCY_1 \
	217	\| OR_FCM_TRLX \
34f81968	218	\| OR_FCM_EHTR)
5fb17030 IY	219	/* 0xFFFF8396 */
	220
	221	#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
65ea7589	222	#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN \| LBLAWAR_32KB)
5fb17030 IY	223
	224	#ifdef CONFIG_VSC7385_ENET
	225	#define CONFIG_TSEC2
7d6a0982	226	/* VSC7385 Base address on CS2 */
5fb17030	227	#define CONFIG_SYS_VSC7385_BASE 0xF0000000
7d6a0982 JH	228	#define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */
	229	#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \
	230	\| BR_PS_8 /* 8-bit port */ \
	231	\| BR_MS_GPCM /* MSEL = GPCM */ \
	232	\| BR_V) /* valid */
	233	/* 0xF0000801 */
	234	#define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \
	235	\| OR_GPCM_CSNT \
	236	\| OR_GPCM_XACS \
	237	\| OR_GPCM_SCY_15 \
	238	\| OR_GPCM_SETA \
	239	\| OR_GPCM_TRLX_SET \
	240	\| OR_GPCM_EHTR_SET)
	241	/* 0xFFFE09FF */
5fb17030 IY	242	/* Access window base at VSC7385 base */
	243	#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE
	244	/* Access window size 128K */
65ea7589	245	#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN \| LBLAWAR_128KB)
5fb17030 IY	246	/* The flash address and size of the VSC7385 firmware image */
	247	#define CONFIG_VSC7385_IMAGE 0xFE7FE000
	248	#define CONFIG_VSC7385_IMAGE_SIZE 8192
	249	#endif
	250	/*
	251	* Serial Port
	252	*/
5fb17030 IY	253	#define CONFIG_SYS_NS16550_SERIAL
	254	#define CONFIG_SYS_NS16550_REG_SIZE 1
	255	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
	256
	257	#define CONFIG_SYS_BAUDRATE_TABLE \
	258	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
	259
	260	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
	261	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
	262
5fb17030	263	/* I2C */
00f792e0 HS	264	#define CONFIG_SYS_I2C
	265	#define CONFIG_SYS_I2C_FSL
	266	#define CONFIG_SYS_FSL_I2C_SPEED 400000
	267	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	268	#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
	269	#define CONFIG_SYS_FSL_I2C2_SPEED 400000
	270	#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
	271	#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
	272	#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
5fb17030	273
ea1ea54e IS	274	/*
	275	* SPI on header J8
	276	*
	277	* WARNING: enabling this will break TSEC2 (connected to the Vitesse switch)
	278	* due to a pinmux conflict between GPIO9 (SPI chip select )and the TSEC2 pins.
	279	*/
	280	#ifdef CONFIG_MPC8XXX_SPI
ea1ea54e	281	#define CONFIG_USE_SPIFLASH
ea1ea54e	282	#endif
5fb17030 IY	283
	284	/*
	285	* Board info - revision and where boot from
	286	*/
	287	#define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39
	288
	289	/*
	290	* Config on-board RTC
	291	*/
	292	#define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */
	293	#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
	294
	295	/*
	296	* General PCI
	297	* Addresses are mapped 1-1.
	298	*/
	299	#define CONFIG_SYS_PCIE1_BASE 0xA0000000
	300	#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
	301	#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
	302	#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
	303	#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
	304	#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
	305	#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
	306	#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
	307	#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
	308
65ea7589 IY	309	/* enable PCIE clock */
65ea7589 IY	310	#define CONFIG_SYS_SCCR_PCIEXP1CM 1
5fb17030	311
842033e6	312	#define CONFIG_PCI_INDIRECT_BRIDGE
5fb17030 IY	313	#define CONFIG_PCIE
5fb17030 IY	314
5fb17030 IY	315	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
	316	#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
	317
	318	/*
	319	* TSEC
	320	*/
5fb17030 IY	321	#define CONFIG_SYS_TSEC1_OFFSET 0x24000
	322	#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
	323	#define CONFIG_SYS_TSEC2_OFFSET 0x25000
	324	#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
	325
	326	/*
	327	* TSEC ethernet configuration
	328	*/
5fb17030 IY	329	#define CONFIG_TSEC1_NAME "eTSEC0"
	330	#define CONFIG_TSEC2_NAME "eTSEC1"
	331	#define TSEC1_PHY_ADDR 2
	332	#define TSEC2_PHY_ADDR 1
	333	#define TSEC1_PHYIDX 0
	334	#define TSEC2_PHYIDX 0
	335	#define TSEC1_FLAGS TSEC_GIGABIT
	336	#define TSEC2_FLAGS TSEC_GIGABIT
	337
	338	/* Options are: eTSEC[0-1] */
	339	#define CONFIG_ETHPRIME "eTSEC0"
	340
	341	/*
	342	* Environment
	343	*/
5fb17030 IY	344	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
	345	CONFIG_SYS_MONITOR_LEN)
	346	#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
	347	#define CONFIG_ENV_SIZE 0x2000
	348	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
	349	#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
	350
	351	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	352	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
	353
	354	/*
	355	* BOOTP options
	356	*/
	357	#define CONFIG_BOOTP_BOOTFILESIZE
5fb17030 IY	358
	359	/*
	360	* Command line configuration.
	361	*/
5fb17030	362
5fb17030 IY	363	/*
	364	* Miscellaneous configurable options
	365	*/
5fb17030	366	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
5fb17030 IY	367
	368	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
	369
5fb17030 IY	370	/* Boot Argument Buffer Size */
5fb17030 IY	371	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
5fb17030 IY	372
	373	/*
	374	* For booting Linux, the board info and command line data
9f530d59	375	* have to be in the first 256 MB of memory, since this is
5fb17030 IY	376	* the maximum mapped by the Linux kernel during initialization.
5fb17030 IY	377	*/
9f530d59	378	#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
63865278	379	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
5fb17030 IY	380
	381	/*
	382	* Core HID Setup
	383	*/
	384	#define CONFIG_SYS_HID0_INIT 0x000000000
	385	#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \| \
	386	HID0_ENABLE_INSTRUCTION_CACHE \| \
	387	HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
	388	#define CONFIG_SYS_HID2 HID2_HBE
	389
5fb17030 IY	390	/*
	391	* Environment Configuration
	392	*/
	393
	394	#define CONFIG_ENV_OVERWRITE
	395
	396	#if defined(CONFIG_TSEC_ENET)
	397	#define CONFIG_HAS_ETH0
	398	#define CONFIG_HAS_ETH1
	399	#endif
	400
5fb17030 IY	401	#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
5fb17030 IY	402
5fb17030	403
5fb17030 IY	404	#define CONFIG_EXTRA_ENV_SETTINGS \
	405	"netdev=eth0\0" \
	406	"consoledev=ttyS0\0" \
	407	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	408	"nfsroot=${serverip}:${rootpath}\0" \
	409	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	410	"addip=setenv bootargs ${bootargs} " \
	411	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	412	":${hostname}:${netdev}:off panic=1\0" \
	413	"addtty=setenv bootargs ${bootargs}" \
	414	" console=${consoledev},${baudrate}\0" \
	415	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
	416	"addmisc=setenv bootargs ${bootargs}\0" \
	417	"kernel_addr=FE080000\0" \
	418	"fdt_addr=FE280000\0" \
	419	"ramdisk_addr=FE290000\0" \
	420	"u-boot=mpc8308rdb/u-boot.bin\0" \
	421	"kernel_addr_r=1000000\0" \
	422	"fdt_addr_r=C00000\0" \
	423	"hostname=mpc8308rdb\0" \
	424	"bootfile=mpc8308rdb/uImage\0" \
	425	"fdtfile=mpc8308rdb/mpc8308rdb.dtb\0" \
	426	"rootpath=/opt/eldk-4.2/ppc_6xx\0" \
	427	"flash_self=run ramargs addip addtty addmtd addmisc;" \
	428	"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
	429	"flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
	430	"bootm ${kernel_addr} - ${fdt_addr}\0" \
	431	"net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
	432	"tftp ${fdt_addr_r} ${fdtfile};" \
	433	"run nfsargs addip addtty addmtd addmisc;" \
	434	"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
	435	"bootcmd=run flash_self\0" \
	436	"load=tftp ${loadaddr} ${u-boot}\0" \
93ea89f0 MV	437	"update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
93ea89f0 MV	438	" +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
5fb17030	439	" +${filesize};cp.b ${fileaddr} " \
93ea89f0	440	__stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
5fb17030 IY	441	"upd=run load update\0" \
	442
	443	#endif /* __CONFIG_H */