[J-u-boot.git] / include / configs / MPC8560ADS.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright 2004, 2011 Freescale Semiconductor.
 * (C) Copyright 2002,2003 Motorola,Inc.
 * Xianghua Xiao <[email protected]>
 */

/*
 * mpc8560ads board configuration file
 *
 * Please refer to doc/README.mpc85xx for more info.
 *
 * Make sure you change the MAC address and other network params first,
 * search for CONFIG_SERVERIP, etc. in this file.
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/* High Level Configuration Options */
#define CONFIG_CPM2		1	/* has CPM2 */

/*
 * default CCARBAR is at 0xff700000
 * assume U-Boot is less than 0.5MB
 */

#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
#undef CONFIG_ETHER_ON_FCC             /* cpm FCC ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_RESET_PHY_R	1	/* Call reset_phy() */

/*
 * sysclk for MPC85xx
 *
 * Two valid values are:
 *    33000000
 *    66000000
 *
 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
 * is likely the desired value here, so that is now the default.
 * The board, however, can run at 66MHz.  In any event, this value
 * must match the settings of some switches.  Details can be found
 * in the README.mpc85xxads.
 */

#ifndef CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_CLK_FREQ	33000000
#endif

/*
 * These can be toggled for performance analysis, otherwise use default.
 */
#define CONFIG_L2_CACHE			/* toggle L2 cache */
#define CONFIG_BTB			/* toggle branch predition */

#define CONFIG_SYS_INIT_DBCR DBCR_IDM		/* Enable Debug Exceptions */

#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest region */
#define CONFIG_SYS_MEMTEST_END		0x00400000

#define CONFIG_SYS_CCSRBAR		0xe0000000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR

/* DDR Setup */
#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_SPD

#define CONFIG_MEM_INIT_VALUE		0xDeadBeef

#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE

#define CONFIG_DIMM_SLOTS_PER_CTLR	1
#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)

/* I2C addresses of SPD EEPROMs */
#define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */

/* These are used when DDR doesn't use SPD.  */
#define CONFIG_SYS_SDRAM_SIZE	128		/* DDR is 128MB */
#define CONFIG_SYS_DDR_CS0_BNDS	0x00000007	/* 0-128MB */
#define CONFIG_SYS_DDR_CS0_CONFIG	0x80000002
#define CONFIG_SYS_DDR_TIMING_1	0x37344321
#define CONFIG_SYS_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
#define CONFIG_SYS_DDR_CONTROL		0xc2000000	/* unbuffered,no DYN_PWR */
#define CONFIG_SYS_DDR_MODE		0x00000062	/* DLL,normal,seq,4/2.5 */
#define CONFIG_SYS_DDR_INTERVAL	0x05200100	/* autocharge,no open page */

/*
 * SDRAM on the Local Bus
 */
#define CONFIG_SYS_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
#define CONFIG_SYS_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */

#define CONFIG_SYS_FLASH_BASE		0xff000000	/* start of FLASH 16M */
#define CONFIG_SYS_BR0_PRELIM		0xff001801	/* port size 32bit */

#define CONFIG_SYS_OR0_PRELIM		0xff006ff7	/* 16MB Flash */
#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	64		/* sectors per device */
#undef	CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */

#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */

#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#else
#undef  CONFIG_SYS_RAMBOOT
#endif

#define CONFIG_SYS_FLASH_EMPTY_INFO

#undef CONFIG_CLOCKS_IN_MHZ

/*
 * Local Bus Definitions
 */

/*
 * Base Register 2 and Option Register 2 configure SDRAM.
 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 *
 * For BR2, need:
 *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 *    port-size = 32-bits = BR2[19:20] = 11
 *    no parity checking = BR2[21:22] = 00
 *    SDRAM for MSEL = BR2[24:26] = 011
 *    Valid = BR[31] = 1
 *
 * 0    4    8    12   16   20   24   28
 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
 *
 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
 * FIXME: the top 17 bits of BR2.
 */

#define CONFIG_SYS_BR2_PRELIM		0xf0001861

/*
 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 *
 * For OR2, need:
 *    64MB mask for AM, OR2[0:7] = 1111 1100
 *		   XAM, OR2[17:18] = 11
 *    9 columns OR2[19-21] = 010
 *    13 rows   OR2[23-25] = 100
 *    EAD set for extra time OR[31] = 1
 *
 * 0    4    8    12   16   20   24   28
 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
 */

#define CONFIG_SYS_OR2_PRELIM		0xfc006901

#define CONFIG_SYS_LBC_LCRR		0x00030004    /* LB clock ratio reg */
#define CONFIG_SYS_LBC_LBCR		0x00000000    /* LB config reg */
#define CONFIG_SYS_LBC_LSRT		0x20000000    /* LB sdram refresh timer */
#define CONFIG_SYS_LBC_MRTPR		0x20000000    /* LB refresh timer prescal*/

#define CONFIG_SYS_LBC_LSDMR_COMMON	( LSDMR_BSMA1516	\
				| LSDMR_RFCR5		\
				| LSDMR_PRETOACT3	\
				| LSDMR_ACTTORW3	\
				| LSDMR_BL8		\
				| LSDMR_WRC2		\
				| LSDMR_CL3		\
				| LSDMR_RFEN		\
				)

/*
 * SDRAM Controller configuration sequence.
 */
#define CONFIG_SYS_LBC_LSDMR_1	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
#define CONFIG_SYS_LBC_LSDMR_2	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
#define CONFIG_SYS_LBC_LSDMR_3	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
#define CONFIG_SYS_LBC_LSDMR_4	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
#define CONFIG_SYS_LBC_LSDMR_5	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)

/*
 * 32KB, 8-bit wide for ADS config reg
 */
#define CONFIG_SYS_BR4_PRELIM          0xf8000801
#define CONFIG_SYS_OR4_PRELIM		0xffffe1f1
#define CONFIG_SYS_BCSR		(CONFIG_SYS_BR4_PRELIM & 0xffff8000)

#define CONFIG_SYS_INIT_RAM_LOCK	1
#define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in RAM */

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)    /* Reserve 256 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)    /* Reserved for malloc */

/* Serial Port */
#define CONFIG_CONS_ON_SCC	/* define if console on SCC */
#undef  CONFIG_CONS_NONE	/* define if console on something else */

#define CONFIG_SYS_BAUDRATE_TABLE  \
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}

/*
 * I2C
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	400000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }

/* RapidIO MMU */
#define CONFIG_SYS_RIO_MEM_VIRT	0xc0000000	/* base address */
#define CONFIG_SYS_RIO_MEM_BUS	0xc0000000	/* base address */
#define CONFIG_SYS_RIO_MEM_PHYS	0xc0000000
#define CONFIG_SYS_RIO_MEM_SIZE	0x20000000	/* 128M */

/*
 * General PCI
 * Memory space is mapped 1-1, but I/O space must start from 0.
 */
#define CONFIG_SYS_PCI1_MEM_VIRT	0x80000000
#define CONFIG_SYS_PCI1_MEM_BUS	0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS	0x80000000
#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
#define CONFIG_SYS_PCI1_IO_VIRT	0xe2000000
#define CONFIG_SYS_PCI1_IO_BUS	0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS	0xe2000000
#define CONFIG_SYS_PCI1_IO_SIZE	0x100000	/* 1M */

#if defined(CONFIG_PCI)
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP

#if !defined(CONFIG_PCI_PNP)
    #define PCI_ENET0_IOADDR	0xe0000000
    #define PCI_ENET0_MEMADDR	0xe0000000
    #define PCI_IDSEL_NUMBER	0x0c	/* slot0->3(IDSEL)=12->15 */
#endif

#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */

#endif	/* CONFIG_PCI */

#ifdef CONFIG_TSEC_ENET

#define CONFIG_TSEC1	1
#define CONFIG_TSEC1_NAME	"TSEC0"
#define CONFIG_TSEC2	1
#define CONFIG_TSEC2_NAME	"TSEC1"
#define TSEC1_PHY_ADDR		0
#define TSEC2_PHY_ADDR		1
#define TSEC1_PHYIDX		0
#define TSEC2_PHYIDX		0
#define TSEC1_FLAGS		TSEC_GIGABIT
#define TSEC2_FLAGS		TSEC_GIGABIT

/* Options are: TSEC[0-1] */
#define CONFIG_ETHPRIME		"TSEC0"

#endif /* CONFIG_TSEC_ENET */

#ifdef CONFIG_ETHER_ON_FCC		/* CPM FCC Ethernet */

#undef  CONFIG_ETHER_NONE		/* define if ether on something else */
#define CONFIG_ETHER_INDEX      2       /* which channel for ether */

#if (CONFIG_ETHER_INDEX == 2)
  /*
   * - Rx-CLK is CLK13
   * - Tx-CLK is CLK14
   * - Select bus for bd/buffers
   * - Full duplex
   */
  #define CONFIG_SYS_CMXFCR_MASK2      (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
  #define CONFIG_SYS_CMXFCR_VALUE2     (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
  #define CONFIG_SYS_CPMFCR_RAMTYPE    0
  #define CONFIG_SYS_FCC_PSMR          (FCC_PSMR_FDE)
  #define FETH2_RST		0x01
#elif (CONFIG_ETHER_INDEX == 3)
  /* need more definitions here for FE3 */
  #define FETH3_RST		0x80
#endif					/* CONFIG_ETHER_INDEX */

/*
 * GPIO pins used for bit-banged MII communications
 */
#define MDIO_PORT	2		/* Port C */
#define MDIO_DECLARE	volatile ioport_t *iop = ioport_addr ( \
				(immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
#define MDC_DECLARE	MDIO_DECLARE

#define MDIO_ACTIVE	(iop->pdir |=  0x00400000)
#define MDIO_TRISTATE	(iop->pdir &= ~0x00400000)
#define MDIO_READ	((iop->pdat &  0x00400000) != 0)

#define MDIO(bit)	if(bit) iop->pdat |=  0x00400000; \
			else	iop->pdat &= ~0x00400000

#define MDC(bit)	if(bit) iop->pdat |=  0x00200000; \
			else	iop->pdat &= ~0x00200000

#define MIIDELAY	udelay(1)

#endif

/*
 * Environment
 */

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE

#undef CONFIG_WATCHDOG			/* watchdog disabled */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LOAD_ADDR	0x1000000	/* default load address */

#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 64 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#endif

/*
 * Environment Configuration
 */
#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#define CONFIG_HAS_ETH2
#define CONFIG_HAS_ETH3
#endif

#define CONFIG_IPADDR    192.168.1.253

#define CONFIG_HOSTNAME		"unknown"
#define CONFIG_ROOTPATH		"/nfsroot"
#define CONFIG_BOOTFILE		"your.uImage"

#define CONFIG_SERVERIP  192.168.1.1
#define CONFIG_GATEWAYIP 192.168.1.1
#define CONFIG_NETMASK   255.255.255.0

#define CONFIG_LOADADDR  200000	/* default location for tftp and bootm */

#define	CONFIG_EXTRA_ENV_SETTINGS				        \
	"netdev=eth0\0"							\
	"consoledev=ttyCPM\0"						\
	"ramdiskaddr=1000000\0"						\
	"ramdiskfile=your.ramdisk.u-boot\0"				\
	"fdtaddr=400000\0"						\
	"fdtfile=mpc8560ads.dtb\0"

#define CONFIG_NFSBOOTCOMMAND	                                        \
	"setenv bootargs root=/dev/nfs rw "				\
		"nfsroot=$serverip:$rootpath "				\
		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
		"console=$consoledev,$baudrate $othbootargs;"		\
	"tftp $loadaddr $bootfile;"					\
	"tftp $fdtaddr $fdtfile;"					\
	"bootm $loadaddr - $fdtaddr"

#define CONFIG_RAMBOOTCOMMAND \
	"setenv bootargs root=/dev/ram rw "				\
		"console=$consoledev,$baudrate $othbootargs;"		\
	"tftp $ramdiskaddr $ramdiskfile;"				\
	"tftp $loadaddr $bootfile;"					\
	"tftp $fdtaddr $fdtfile;"					\
	"bootm $loadaddr $ramdiskaddr $fdtaddr"

#define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND

#endif	/* __CONFIG_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
42d1f039	2	/*
7c57f3e8	3	* Copyright 2004, 2011 Freescale Semiconductor.
42d1f039 WD	4	* (C) Copyright 2002,2003 Motorola,Inc.
42d1f039 WD	5	* Xianghua Xiao <[email protected]>
42d1f039 WD	6	*/
42d1f039 WD	7
0ac6f8b7 WD	8	/*
	9	* mpc8560ads board configuration file
	10	*
	11	* Please refer to doc/README.mpc85xx for more info.
	12	*
	13	* Make sure you change the MAC address and other network params first,
92ac5208	14	* search for CONFIG_SERVERIP, etc. in this file.
42d1f039 WD	15	*/
	16
	17	#ifndef __CONFIG_H
	18	#define __CONFIG_H
	19
	20	/* High Level Configuration Options */
9c4c5ae3	21	#define CONFIG_CPM2 1 /* has CPM2 */
0ac6f8b7	22
2ae18241 WD	23	/*
	24	* default CCARBAR is at 0xff700000
	25	* assume U-Boot is less than 0.5MB
	26	*/
2ae18241	27
842033e6	28	#define CONFIG_PCI_INDIRECT_BRIDGE
0151cbac	29	#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
ccc091aa	30	#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
42d1f039	31	#define CONFIG_ENV_OVERWRITE
004eca0c	32	#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
42d1f039	33
0ac6f8b7 WD	34	/*
	35	* sysclk for MPC85xx
	36	*
	37	* Two valid values are:
	38	* 33000000
	39	* 66000000
	40	*
	41	* Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
9aea9530 WD	42	* is likely the desired value here, so that is now the default.
	43	* The board, however, can run at 66MHz. In any event, this value
	44	* must match the settings of some switches. Details can be found
	45	* in the README.mpc85xxads.
0ac6f8b7 WD	46	*/
0ac6f8b7 WD	47
9aea9530 WD	48	#ifndef CONFIG_SYS_CLK_FREQ
9aea9530 WD	49	#define CONFIG_SYS_CLK_FREQ 33000000
42d1f039 WD	50	#endif
42d1f039 WD	51
0ac6f8b7 WD	52	/*
	53	* These can be toggled for performance analysis, otherwise use default.
	54	*/
	55	#define CONFIG_L2_CACHE /* toggle L2 cache */
	56	#define CONFIG_BTB /* toggle branch predition */
42d1f039	57
6d0f6bcf	58	#define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
0ac6f8b7	59
6d0f6bcf JCPV	60	#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
6d0f6bcf JCPV	61	#define CONFIG_SYS_MEMTEST_END 0x00400000
42d1f039	62
e46fedfe TT	63	#define CONFIG_SYS_CCSRBAR 0xe0000000
e46fedfe TT	64	#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
42d1f039	65
8b625114	66	/* DDR Setup */
8b625114 JL	67	#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
8b625114 JL	68	#define CONFIG_DDR_SPD
8b625114 JL	69
8b625114 JL	70	#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
9aea9530	71
6d0f6bcf JCPV	72	#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
6d0f6bcf JCPV	73	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
9aea9530	74
8b625114 JL	75	#define CONFIG_DIMM_SLOTS_PER_CTLR 1
8b625114 JL	76	#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
9aea9530	77
8b625114 JL	78	/* I2C addresses of SPD EEPROMs */
8b625114 JL	79	#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
9aea9530	80
8b625114	81	/* These are used when DDR doesn't use SPD. */
6d0f6bcf JCPV	82	#define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */
	83	#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
	84	#define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002
	85	#define CONFIG_SYS_DDR_TIMING_1 0x37344321
	86	#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
	87	#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
	88	#define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
	89	#define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */
42d1f039	90
0ac6f8b7 WD	91	/*
	92	* SDRAM on the Local Bus
	93	*/
6d0f6bcf JCPV	94	#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
6d0f6bcf JCPV	95	#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
42d1f039	96
6d0f6bcf JCPV	97	#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
6d0f6bcf JCPV	98	#define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */
42d1f039	99
6d0f6bcf JCPV	100	#define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */
	101	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
	102	#define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */
	103	#undef CONFIG_SYS_FLASH_CHECKSUM
	104	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	105	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
0ac6f8b7	106
14d0a02a	107	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
42d1f039	108
6d0f6bcf JCPV	109	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
6d0f6bcf JCPV	110	#define CONFIG_SYS_RAMBOOT
42d1f039	111	#else
6d0f6bcf	112	#undef CONFIG_SYS_RAMBOOT
42d1f039 WD	113	#endif
42d1f039 WD	114
6d0f6bcf	115	#define CONFIG_SYS_FLASH_EMPTY_INFO
0ac6f8b7 WD	116
0ac6f8b7 WD	117	#undef CONFIG_CLOCKS_IN_MHZ
42d1f039	118
0ac6f8b7 WD	119	/*
	120	* Local Bus Definitions
	121	*/
	122
	123	/*
	124	* Base Register 2 and Option Register 2 configure SDRAM.
6d0f6bcf	125	* The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
0ac6f8b7 WD	126	*
	127	* For BR2, need:
	128	* Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
	129	* port-size = 32-bits = BR2[19:20] = 11
	130	* no parity checking = BR2[21:22] = 00
	131	* SDRAM for MSEL = BR2[24:26] = 011
	132	* Valid = BR[31] = 1
	133	*
	134	* 0 4 8 12 16 20 24 28
	135	* 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
	136	*
6d0f6bcf	137	* FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
0ac6f8b7 WD	138	* FIXME: the top 17 bits of BR2.
	139	*/
	140
6d0f6bcf	141	#define CONFIG_SYS_BR2_PRELIM 0xf0001861
0ac6f8b7 WD	142
0ac6f8b7 WD	143	/*
6d0f6bcf	144	* The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
0ac6f8b7 WD	145	*
	146	* For OR2, need:
	147	* 64MB mask for AM, OR2[0:7] = 1111 1100
	148	* XAM, OR2[17:18] = 11
	149	* 9 columns OR2[19-21] = 010
	150	* 13 rows OR2[23-25] = 100
	151	* EAD set for extra time OR[31] = 1
	152	*
	153	* 0 4 8 12 16 20 24 28
	154	* 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
	155	*/
	156
6d0f6bcf	157	#define CONFIG_SYS_OR2_PRELIM 0xfc006901
0ac6f8b7	158
6d0f6bcf JCPV	159	#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
	160	#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
	161	#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
	162	#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
0ac6f8b7	163
b0fe93ed KG	164	#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \
	165	\| LSDMR_RFCR5 \
	166	\| LSDMR_PRETOACT3 \
	167	\| LSDMR_ACTTORW3 \
	168	\| LSDMR_BL8 \
	169	\| LSDMR_WRC2 \
	170	\| LSDMR_CL3 \
	171	\| LSDMR_RFEN \
0ac6f8b7 WD	172	)
	173
	174	/*
	175	* SDRAM Controller configuration sequence.
	176	*/
b0fe93ed KG	177	#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON \| LSDMR_OP_PCHALL)
	178	#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON \| LSDMR_OP_ARFRSH)
	179	#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON \| LSDMR_OP_ARFRSH)
	180	#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON \| LSDMR_OP_MRW)
	181	#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON \| LSDMR_OP_NORMAL)
0ac6f8b7	182
9aea9530 WD	183	/*
	184	* 32KB, 8-bit wide for ADS config reg
	185	*/
6d0f6bcf JCPV	186	#define CONFIG_SYS_BR4_PRELIM 0xf8000801
	187	#define CONFIG_SYS_OR4_PRELIM 0xffffe1f1
	188	#define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
42d1f039	189
6d0f6bcf JCPV	190	#define CONFIG_SYS_INIT_RAM_LOCK 1
6d0f6bcf JCPV	191	#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
553f0982	192	#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
42d1f039	193
25ddd1fb	194	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	195	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
42d1f039	196
6d0f6bcf JCPV	197	#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
6d0f6bcf JCPV	198	#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
42d1f039 WD	199
42d1f039 WD	200	/* Serial Port */
0ac6f8b7 WD	201	#define CONFIG_CONS_ON_SCC /* define if console on SCC */
0ac6f8b7 WD	202	#undef CONFIG_CONS_NONE /* define if console on something else */
42d1f039	203
6d0f6bcf	204	#define CONFIG_SYS_BAUDRATE_TABLE \
42d1f039 WD	205	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
42d1f039 WD	206
20476726 JL	207	/*
	208	* I2C
	209	*/
00f792e0 HS	210	#define CONFIG_SYS_I2C
	211	#define CONFIG_SYS_I2C_FSL
	212	#define CONFIG_SYS_FSL_I2C_SPEED 400000
	213	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	214	#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
	215	#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
42d1f039	216
0ac6f8b7	217	/* RapidIO MMU */
5af0fdd8	218	#define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */
10795f42	219	#define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */
5af0fdd8	220	#define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000
6d0f6bcf	221	#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */
0ac6f8b7 WD	222
	223	/*
	224	* General PCI
362dd830	225	* Memory space is mapped 1-1, but I/O space must start from 0.
0ac6f8b7	226	*/
5af0fdd8	227	#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
10795f42	228	#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
5af0fdd8	229	#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
6d0f6bcf	230	#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
aca5f018	231	#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
5f91ef6a	232	#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
6d0f6bcf JCPV	233	#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
6d0f6bcf JCPV	234	#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
0ac6f8b7 WD	235
0ac6f8b7 WD	236	#if defined(CONFIG_PCI)
0ac6f8b7	237	#undef CONFIG_EEPRO100
42d1f039	238	#undef CONFIG_TULIP
0ac6f8b7 WD	239
	240	#if !defined(CONFIG_PCI_PNP)
	241	#define PCI_ENET0_IOADDR 0xe0000000
	242	#define PCI_ENET0_MEMADDR 0xe0000000
53677ef1	243	#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
42d1f039	244	#endif
0ac6f8b7 WD	245
0ac6f8b7 WD	246	#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
6d0f6bcf	247	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
0ac6f8b7 WD	248
	249	#endif /* CONFIG_PCI */
	250
ccc091aa	251	#ifdef CONFIG_TSEC_ENET
0ac6f8b7	252
255a3577 KP	253	#define CONFIG_TSEC1 1
	254	#define CONFIG_TSEC1_NAME "TSEC0"
	255	#define CONFIG_TSEC2 1
	256	#define CONFIG_TSEC2_NAME "TSEC1"
0ac6f8b7 WD	257	#define TSEC1_PHY_ADDR 0
	258	#define TSEC2_PHY_ADDR 1
	259	#define TSEC1_PHYIDX 0
	260	#define TSEC2_PHYIDX 0
3a79013e AF	261	#define TSEC1_FLAGS TSEC_GIGABIT
3a79013e AF	262	#define TSEC2_FLAGS TSEC_GIGABIT
d9b94f28 JL	263
	264	/* Options are: TSEC[0-1] */
	265	#define CONFIG_ETHPRIME "TSEC0"
0ac6f8b7	266
ccc091aa AF	267	#endif /* CONFIG_TSEC_ENET */
ccc091aa AF	268
53677ef1	269	#ifdef CONFIG_ETHER_ON_FCC /* CPM FCC Ethernet */
0ac6f8b7	270
53677ef1	271	#undef CONFIG_ETHER_NONE /* define if ether on something else */
0ac6f8b7 WD	272	#define CONFIG_ETHER_INDEX 2 /* which channel for ether */
	273
	274	#if (CONFIG_ETHER_INDEX == 2)
42d1f039 WD	275	/*
	276	* - Rx-CLK is CLK13
	277	* - Tx-CLK is CLK14
	278	* - Select bus for bd/buffers
	279	* - Full duplex
	280	*/
d4590da4 MF	281	#define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 \| CMXFCR_RF2CS_MSK \| CMXFCR_TF2CS_MSK)
d4590da4 MF	282	#define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 \| CMXFCR_TF2CS_CLK14)
6d0f6bcf JCPV	283	#define CONFIG_SYS_CPMFCR_RAMTYPE 0
6d0f6bcf JCPV	284	#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE)
42d1f039	285	#define FETH2_RST 0x01
0ac6f8b7	286	#elif (CONFIG_ETHER_INDEX == 3)
42d1f039 WD	287	/* need more definitions here for FE3 */
42d1f039 WD	288	#define FETH3_RST 0x80
53677ef1	289	#endif /* CONFIG_ETHER_INDEX */
0ac6f8b7	290
42d1f039 WD	291	/*
	292	* GPIO pins used for bit-banged MII communications
	293	*/
	294	#define MDIO_PORT 2 /* Port C */
be225442 LCM	295	#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
	296	(immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
	297	#define MDC_DECLARE MDIO_DECLARE
	298
42d1f039 WD	299	#define MDIO_ACTIVE (iop->pdir \|= 0x00400000)
	300	#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
	301	#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
	302
	303	#define MDIO(bit) if(bit) iop->pdat \|= 0x00400000; \
	304	else iop->pdat &= ~0x00400000
	305
	306	#define MDC(bit) if(bit) iop->pdat \|= 0x00200000; \
	307	else iop->pdat &= ~0x00200000
	308
	309	#define MIIDELAY udelay(1)
0ac6f8b7	310
42d1f039 WD	311	#endif
42d1f039 WD	312
0ac6f8b7 WD	313	/*
	314	* Environment
	315	*/
42d1f039	316
0ac6f8b7	317	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	318	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
42d1f039	319
659e2f67 JL	320	/*
	321	* BOOTP options
	322	*/
	323	#define CONFIG_BOOTP_BOOTFILESIZE
659e2f67	324
0ac6f8b7	325	#undef CONFIG_WATCHDOG /* watchdog disabled */
42d1f039 WD	326
	327	/*
	328	* Miscellaneous configurable options
	329	*/
6d0f6bcf	330	#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */
0ac6f8b7	331
6d0f6bcf	332	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
42d1f039 WD	333
	334	/*
	335	* For booting Linux, the board info and command line data
a832ac41	336	* have to be in the first 64 MB of memory, since this is
42d1f039 WD	337	* the maximum mapped by the Linux kernel during initialization.
42d1f039 WD	338	*/
a832ac41 KG	339	#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
a832ac41 KG	340	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
42d1f039	341
2835e518	342	#if defined(CONFIG_CMD_KGDB)
42d1f039	343	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
42d1f039 WD	344	#endif
42d1f039 WD	345
9aea9530 WD	346	/*
	347	* Environment Configuration
	348	*/
42d1f039	349	#if defined(CONFIG_TSEC_ENET) \|\| defined(CONFIG_ETHER_ON_FCC)
10327dc5	350	#define CONFIG_HAS_ETH0
e2ffd59b	351	#define CONFIG_HAS_ETH1
e2ffd59b	352	#define CONFIG_HAS_ETH2
5ce71580	353	#define CONFIG_HAS_ETH3
42d1f039 WD	354	#endif
42d1f039 WD	355
0ac6f8b7 WD	356	#define CONFIG_IPADDR 192.168.1.253
0ac6f8b7 WD	357
5bc0543d	358	#define CONFIG_HOSTNAME "unknown"
8b3637c6	359	#define CONFIG_ROOTPATH "/nfsroot"
b3f44c21	360	#define CONFIG_BOOTFILE "your.uImage"
0ac6f8b7 WD	361
	362	#define CONFIG_SERVERIP 192.168.1.1
	363	#define CONFIG_GATEWAYIP 192.168.1.1
	364	#define CONFIG_NETMASK 255.255.255.0
	365
	366	#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
	367
9aea9530	368	#define CONFIG_EXTRA_ENV_SETTINGS \
6b44a44e AF	369	"netdev=eth0\0" \
	370	"consoledev=ttyCPM\0" \
	371	"ramdiskaddr=1000000\0" \
	372	"ramdiskfile=your.ramdisk.u-boot\0" \
	373	"fdtaddr=400000\0" \
	374	"fdtfile=mpc8560ads.dtb\0"
0ac6f8b7	375
9aea9530	376	#define CONFIG_NFSBOOTCOMMAND \
6b44a44e AF	377	"setenv bootargs root=/dev/nfs rw " \
	378	"nfsroot=$serverip:$rootpath " \
	379	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
	380	"console=$consoledev,$baudrate $othbootargs;" \
	381	"tftp $loadaddr $bootfile;" \
	382	"tftp $fdtaddr $fdtfile;" \
	383	"bootm $loadaddr - $fdtaddr"
0ac6f8b7 WD	384
0ac6f8b7 WD	385	#define CONFIG_RAMBOOTCOMMAND \
6b44a44e AF	386	"setenv bootargs root=/dev/ram rw " \
	387	"console=$consoledev,$baudrate $othbootargs;" \
	388	"tftp $ramdiskaddr $ramdiskfile;" \
	389	"tftp $loadaddr $bootfile;" \
	390	"tftp $fdtaddr $fdtfile;" \
	391	"bootm $loadaddr $ramdiskaddr $fdtaddr"
0ac6f8b7 WD	392
0ac6f8b7 WD	393	#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
42d1f039 WD	394
42d1f039 WD	395	#endif /* __CONFIG_H */