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Commit | Line | Data |
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83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
c133c1fb YG |
2 | /* |
3 | * Configuation settings for the Renesas R7780MP board | |
4 | * | |
ec39d479 | 5 | * Copyright (C) 2007,2008 Nobuhiro Iwamatsu <[email protected]> |
c133c1fb | 6 | * Copyright (C) 2008 Yusuke Goda <[email protected]> |
c133c1fb YG |
7 | */ |
8 | ||
9 | #ifndef __R7780RP_H | |
10 | #define __R7780RP_H | |
11 | ||
c133c1fb YG |
12 | #define CONFIG_CPU_SH7780 1 |
13 | #define CONFIG_R7780MP 1 | |
6d0f6bcf | 14 | #define CONFIG_SYS_R7780MP_OLD_FLASH 1 |
ec39d479 | 15 | #define __LITTLE_ENDIAN__ 1 |
c133c1fb | 16 | |
18a40e84 VZ |
17 | #define CONFIG_DISPLAY_BOARDINFO |
18 | ||
c133c1fb YG |
19 | #define CONFIG_CONS_SCIF0 1 |
20 | ||
c133c1fb YG |
21 | #define CONFIG_ENV_OVERWRITE 1 |
22 | ||
6d0f6bcf JCPV |
23 | #define CONFIG_SYS_SDRAM_BASE (0x08000000) |
24 | #define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024) | |
c133c1fb | 25 | |
6d0f6bcf | 26 | #define CONFIG_SYS_PBSIZE 256 |
c133c1fb | 27 | |
6d0f6bcf | 28 | #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE) |
14d0a02a | 29 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000) |
c133c1fb | 30 | |
ec39d479 | 31 | /* Flash board support */ |
6d0f6bcf JCPV |
32 | #define CONFIG_SYS_FLASH_BASE (0xA0000000) |
33 | #ifdef CONFIG_SYS_R7780MP_OLD_FLASH | |
ec39d479 | 34 | /* NOR Flash (S29PL127J60TFI130) */ |
6d0f6bcf JCPV |
35 | # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT |
36 | # define CONFIG_SYS_MAX_FLASH_BANKS (2) | |
37 | # define CONFIG_SYS_MAX_FLASH_SECT 270 | |
38 | # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ | |
39 | CONFIG_SYS_FLASH_BASE + 0x100000,\ | |
40 | CONFIG_SYS_FLASH_BASE + 0x400000,\ | |
41 | CONFIG_SYS_FLASH_BASE + 0x700000, } | |
42 | #else /* CONFIG_SYS_R7780MP_OLD_FLASH */ | |
ec39d479 | 43 | /* NOR Flash (Spantion S29GL256P) */ |
6d0f6bcf JCPV |
44 | # define CONFIG_SYS_MAX_FLASH_BANKS (1) |
45 | # define CONFIG_SYS_MAX_FLASH_SECT 256 | |
46 | # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } | |
47 | #endif /* CONFIG_SYS_R7780MP_OLD_FLASH */ | |
c133c1fb | 48 | |
6d0f6bcf | 49 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024) |
c133c1fb | 50 | /* Address of u-boot image in Flash */ |
6d0f6bcf JCPV |
51 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) |
52 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) | |
c133c1fb | 53 | /* Size of DRAM reserved for malloc() use */ |
6d0f6bcf | 54 | #define CONFIG_SYS_MALLOC_LEN (1204 * 1024) |
c133c1fb | 55 | |
6d0f6bcf JCPV |
56 | #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) |
57 | #define CONFIG_SYS_RX_ETH_BUFFER (8) | |
c133c1fb | 58 | |
6d0f6bcf JCPV |
59 | #undef CONFIG_SYS_FLASH_CFI_BROKEN_TABLE |
60 | #undef CONFIG_SYS_FLASH_QUIET_TEST | |
c133c1fb | 61 | /* print 'E' for empty sector on flinfo */ |
6d0f6bcf | 62 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
c133c1fb | 63 | |
0e8d1586 JCPV |
64 | #define CONFIG_ENV_SECT_SIZE (256 * 1024) |
65 | #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) | |
6d0f6bcf JCPV |
66 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) |
67 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 | |
68 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 | |
c133c1fb YG |
69 | |
70 | /* Board Clock */ | |
71 | #define CONFIG_SYS_CLK_FREQ 33333333 | |
684a501e | 72 | #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ |
c133c1fb YG |
73 | |
74 | /* PCI Controller */ | |
75 | #if defined(CONFIG_CMD_PCI) | |
c133c1fb | 76 | #define CONFIG_SH4_PCI |
ab8f4d40 | 77 | #define CONFIG_SH7780_PCI |
06b18163 YS |
78 | #define CONFIG_SH7780_PCI_LSR 0x07f00001 |
79 | #define CONFIG_SH7780_PCI_LAR CONFIG_SYS_SDRAM_SIZE | |
80 | #define CONFIG_SH7780_PCI_BAR CONFIG_SYS_SDRAM_SIZE | |
c133c1fb | 81 | #define CONFIG_PCI_SCAN_SHOW 1 |
c133c1fb YG |
82 | #define __mem_pci |
83 | ||
84 | #define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */ | |
85 | #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS | |
86 | #define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */ | |
87 | ||
88 | #define CONFIG_PCI_IO_BUS 0xFE200000 /* IO space base address */ | |
89 | #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS | |
90 | #define CONFIG_PCI_IO_SIZE 0x00200000 /* Size of IO window */ | |
04366d07 NI |
91 | #define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE |
92 | #define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE | |
93 | #define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE | |
c133c1fb YG |
94 | #endif /* CONFIG_CMD_PCI */ |
95 | ||
96 | #if defined(CONFIG_CMD_NET) | |
c7c1dbbf | 97 | /* AX88796L Support(NE2000 base chip) */ |
c133c1fb YG |
98 | #define CONFIG_DRIVER_AX88796L |
99 | #define CONFIG_DRIVER_NE2000_BASE 0xA4100000 | |
100 | #endif | |
101 | ||
102 | /* Compact flash Support */ | |
fc843a02 | 103 | #if defined(CONFIG_IDE) |
c133c1fb | 104 | #define CONFIG_IDE_RESET 1 |
6d0f6bcf JCPV |
105 | #define CONFIG_SYS_PIO_MODE 1 |
106 | #define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */ | |
107 | #define CONFIG_SYS_IDE_MAXDEVICE 1 | |
108 | #define CONFIG_SYS_ATA_BASE_ADDR 0xb4000000 | |
109 | #define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */ | |
110 | #define CONFIG_SYS_ATA_DATA_OFFSET 0x1000 /* data reg offset */ | |
111 | #define CONFIG_SYS_ATA_REG_OFFSET 0x1000 /* reg offset */ | |
112 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x800 /* alternate register offset */ | |
f2a37fcd | 113 | #define CONFIG_IDE_SWAP_IO |
fc843a02 | 114 | #endif /* CONFIG_IDE */ |
c133c1fb YG |
115 | |
116 | #endif /* __R7780RP_H */ |