[J-u-boot.git] / arch / arm / dts / exynos4.dtsi

/*
 * Samsung's Exynos4 SoC common device tree source
 *
 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include "skeleton.dtsi"

/ {
	serial@13800000 {
		compatible = "samsung,exynos4210-uart";
		reg = <0x13800000 0x3c>;
		id = <0>;
	};

	serial@13810000 {
		compatible = "samsung,exynos4210-uart";
		reg = <0x13810000 0x3c>;
		id = <1>;
	};

	serial@13820000 {
		compatible = "samsung,exynos4210-uart";
		reg = <0x13820000 0x3c>;
		id = <2>;
	};

	serial@13830000 {
		compatible = "samsung,exynos4210-uart";
		reg = <0x13830000 0x3c>;
		id = <3>;
	};

	serial@13840000 {
		compatible = "samsung,exynos4210-uart";
		reg = <0x13840000 0x3c>;
		id = <4>;
	};

	i2c@13860000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "samsung,s3c2440-i2c";
		interrupts = <0 0 0>;
	};

	i2c@13870000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "samsung,s3c2440-i2c";
		interrupts = <1 1 0>;
	};

	i2c@13880000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "samsung,s3c2440-i2c";
		interrupts = <2 2 0>;
	};

	i2c@13890000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "samsung,s3c2440-i2c";
		interrupts = <3 3 0>;
	};

	i2c@138a0000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "samsung,s3c2440-i2c";
		interrupts = <4 4 0>;
	};

	i2c@138b0000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "samsung,s3c2440-i2c";
		interrupts = <5 5 0>;
	};

	i2c@138c0000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "samsung,s3c2440-i2c";
		interrupts = <6 6 0>;
	};

	i2c@138d0000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "samsung,s3c2440-i2c";
		interrupts = <7 7 0>;
	};

	sdhci@12510000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "samsung,exynos-mmc";
		reg = <0x12510000 0x1000>;
		interrupts = <0 75 0>;
	};

	sdhci@12520000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "samsung,exynos-mmc";
		reg = <0x12520000 0x1000>;
		interrupts = <0 76 0>;
	};

	sdhci@12530000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "samsung,exynos-mmc";
		reg = <0x12530000 0x1000>;
		interrupts = <0 77 0>;
	};

	sdhci@12540000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "samsung,exynos-mmc";
		reg = <0x12540000 0x1000>;
		interrupts = <0 78 0>;
	};

	dwmmc@12550000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "samsung,exynos-dwmmc";
		reg = <0x12550000 0x1000>;
		interrupts = <0 131 0>;
	};

	gpio: gpio {
		gpio-controller;
		#gpio-cells = <2>;

		interrupt-controller;
		#interrupt-cells = <2>;
	};
};
Commit	Line	Data
8e5e1e6a PW	1	/*
	2	* Samsung's Exynos4 SoC common device tree source
	3	*
	4	* Copyright (c) 2014 Samsung Electronics Co., Ltd.
	5	* http://www.samsung.com
	6	*
	7	* SPDX-License-Identifier: GPL-2.0+
	8	*/
	9
2fdd7d9e	10	#include "skeleton.dtsi"
8e5e1e6a PW	11
	12	/ {
	13	serial@13800000 {
	14	compatible = "samsung,exynos4210-uart";
	15	reg = <0x13800000 0x3c>;
	16	id = <0>;
	17	};
	18
	19	serial@13810000 {
	20	compatible = "samsung,exynos4210-uart";
	21	reg = <0x13810000 0x3c>;
	22	id = <1>;
	23	};
	24
	25	serial@13820000 {
	26	compatible = "samsung,exynos4210-uart";
	27	reg = <0x13820000 0x3c>;
	28	id = <2>;
	29	};
	30
	31	serial@13830000 {
	32	compatible = "samsung,exynos4210-uart";
	33	reg = <0x13830000 0x3c>;
	34	id = <3>;
	35	};
	36
	37	serial@13840000 {
	38	compatible = "samsung,exynos4210-uart";
	39	reg = <0x13840000 0x3c>;
	40	id = <4>;
	41	};
	42
	43	i2c@13860000 {
	44	#address-cells = <1>;
	45	#size-cells = <0>;
	46	compatible = "samsung,s3c2440-i2c";
	47	interrupts = <0 0 0>;
	48	};
	49
	50	i2c@13870000 {
	51	#address-cells = <1>;
	52	#size-cells = <0>;
	53	compatible = "samsung,s3c2440-i2c";
	54	interrupts = <1 1 0>;
	55	};
	56
	57	i2c@13880000 {
	58	#address-cells = <1>;
	59	#size-cells = <0>;
	60	compatible = "samsung,s3c2440-i2c";
	61	interrupts = <2 2 0>;
	62	};
	63
	64	i2c@13890000 {
	65	#address-cells = <1>;
	66	#size-cells = <0>;
	67	compatible = "samsung,s3c2440-i2c";
	68	interrupts = <3 3 0>;
	69	};
	70
	71	i2c@138a0000 {
	72	#address-cells = <1>;
	73	#size-cells = <0>;
	74	compatible = "samsung,s3c2440-i2c";
75	interrupts = <4 4 0>;
76	};
77
78	i2c@138b0000 {
79	#address-cells = <1>;
80	#size-cells = <0>;
81	compatible = "samsung,s3c2440-i2c";
82	interrupts = <5 5 0>;
83	};
84
85	i2c@138c0000 {
86	#address-cells = <1>;
87	#size-cells = <0>;
88	compatible = "samsung,s3c2440-i2c";
89	interrupts = <6 6 0>;
90	};
91
92	i2c@138d0000 {
93	#address-cells = <1>;
94	#size-cells = <0>;
95	compatible = "samsung,s3c2440-i2c";
96	interrupts = <7 7 0>;
97	};
98
99	sdhci@12510000 {
100	#address-cells = <1>;
101	#size-cells = <0>;
102	compatible = "samsung,exynos-mmc";
103	reg = <0x12510000 0x1000>;
104	interrupts = <0 75 0>;
105	};
106
107	sdhci@12520000 {
108	#address-cells = <1>;
109	#size-cells = <0>;
110	compatible = "samsung,exynos-mmc";
111	reg = <0x12520000 0x1000>;
112	interrupts = <0 76 0>;
113	};
114
115	sdhci@12530000 {
116	#address-cells = <1>;
117	#size-cells = <0>;
118	compatible = "samsung,exynos-mmc";
119	reg = <0x12530000 0x1000>;
120	interrupts = <0 77 0>;
121	};
122
123	sdhci@12540000 {
124	#address-cells = <1>;
125	#size-cells = <0>;
126	compatible = "samsung,exynos-mmc";
127	reg = <0x12540000 0x1000>;
128	interrupts = <0 78 0>;
129	};
130
cd0ae61c BS	131	dwmmc@12550000 {
	132	#address-cells = <1>;
	133	#size-cells = <0>;
	134	compatible = "samsung,exynos-dwmmc";
	135	reg = <0x12550000 0x1000>;
	136	interrupts = <0 131 0>;
	137	};
	138
8e5e1e6a PW	139	gpio: gpio {
	140	gpio-controller;
	141	#gpio-cells = <2>;
	142
	143	interrupt-controller;
	144	#interrupt-cells = <2>;
	145	};
	146	};