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1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
2 | /* | |
3 | * Configuration settings for the Renesas GRPEACH board | |
4 | * | |
5 | * Copyright (C) 2017-2019 Renesas Electronics | |
6 | */ | |
7 | ||
8 | #ifndef __GRPEACH_H | |
9 | #define __GRPEACH_H | |
10 | ||
11 | /* Board Clock , P1 clock frequency (XTAL=13.33MHz) */ | |
ba932bc8 | 12 | |
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13 | /* Miscellaneous */ |
14 | #define CONFIG_SYS_PBSIZE 256 | |
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15 | |
16 | /* Internal RAM Size (RZ/A1=3M, RZ/A1M=5M, RZ/A1H=10M) */ | |
17 | #define CONFIG_SYS_SDRAM_BASE 0x20000000 | |
18 | #define CONFIG_SYS_SDRAM_SIZE (10 * 1024 * 1024) | |
19 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
20 | (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - 1024 * 1024) | |
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22 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) |
23 | ||
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24 | /* Network interface */ |
25 | #define CONFIG_SH_ETHER_USE_PORT 0 | |
26 | #define CONFIG_SH_ETHER_PHY_ADDR 0 | |
27 | #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII | |
28 | #define CONFIG_SH_ETHER_CACHE_WRITEBACK | |
29 | #define CONFIG_SH_ETHER_CACHE_INVALIDATE | |
30 | #define CONFIG_SH_ETHER_ALIGNE_SIZE 64 | |
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31 | #define CONFIG_BITBANGMII_MULTI |
32 | ||
33 | #endif /* __GRPEACH_H */ |