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Commit | Line | Data |
---|---|---|
ba1ed5b0 | 1 | config ARCH_MAP_SYSMEM |
11232139 | 2 | depends on SANDBOX |
ba1ed5b0 TR |
3 | def_bool y |
4 | ||
a350c6a6 MY |
5 | config CREATE_ARCH_SYMLINK |
6 | bool | |
7 | ||
9a387128 MY |
8 | config HAVE_ARCH_IOREMAP |
9 | bool | |
10 | ||
e6b937f3 HS |
11 | config HAVE_SETJMP |
12 | bool | |
13 | help | |
14 | The architecture supports setjmp() and longjmp(). | |
15 | ||
cbef2954 JY |
16 | config SUPPORT_BIG_ENDIAN |
17 | bool | |
18 | ||
19 | config SUPPORT_LITTLE_ENDIAN | |
20 | bool | |
21 | default y if !SUPPORT_BIG_ENDIAN | |
22 | ||
ab92b38a TR |
23 | config SYS_CACHE_SHIFT_4 |
24 | bool | |
25 | ||
26 | config SYS_CACHE_SHIFT_5 | |
27 | bool | |
28 | ||
29 | config SYS_CACHE_SHIFT_6 | |
30 | bool | |
31 | ||
32 | config SYS_CACHE_SHIFT_7 | |
33 | bool | |
34 | ||
24c4ac84 DC |
35 | config 32BIT |
36 | bool | |
37 | ||
38 | config 64BIT | |
39 | bool | |
40 | ||
ab92b38a TR |
41 | config SYS_CACHELINE_SIZE |
42 | int | |
43 | default 128 if SYS_CACHE_SHIFT_7 | |
44 | default 64 if SYS_CACHE_SHIFT_6 | |
45 | default 32 if SYS_CACHE_SHIFT_5 | |
46 | default 16 if SYS_CACHE_SHIFT_4 | |
47 | # Fall-back for MIPS | |
48 | default 32 if MIPS | |
49 | ||
0b2fa98a SG |
50 | config LINKER_LIST_ALIGN |
51 | int | |
52 | default 32 if SANDBOX | |
53 | default 8 if ARM64 || X86 | |
54 | default 4 | |
55 | help | |
56 | Force the each linker list to be aligned to this boundary. This | |
57 | is required if ll_entry_get() is used, since otherwise the linker | |
58 | may add padding into the table, thus breaking it. | |
59 | See linker_lists.rst for full details. | |
60 | ||
51631259 MY |
61 | choice |
62 | prompt "Architecture select" | |
63 | default SANDBOX | |
64 | ||
65 | config ARC | |
66 | bool "ARC architecture" | |
5ed063d1 | 67 | select ARC_TIMER |
3daa7c7b | 68 | select CLK |
7b56432c | 69 | select DM |
5ed063d1 MS |
70 | select HAVE_PRIVATE_LIBGCC |
71 | select SUPPORT_OF_CONTROL | |
ab92b38a | 72 | select SYS_CACHE_SHIFT_7 |
3daa7c7b | 73 | select TIMER |
cbef2954 JY |
74 | select SUPPORT_BIG_ENDIAN |
75 | select SUPPORT_LITTLE_ENDIAN | |
83505a7e TR |
76 | select SYS_BIG_ENDIAN if CPU_BIG_ENDIAN |
77 | select SYS_LITTLE_ENDIAN if !CPU_BIG_ENDIAN | |
51631259 MY |
78 | |
79 | config ARM | |
80 | bool "ARM architecture" | |
e6b937f3 | 81 | select HAVE_SETJMP |
8f969651 | 82 | select ARCH_SUPPORTS_LTO |
a350c6a6 | 83 | select CREATE_ARCH_SYMLINK |
64b77ed2 | 84 | select HAVE_PRIVATE_LIBGCC if !ARM64 |
01537235 | 85 | select SUPPORT_ACPI |
cbef2954 | 86 | select SUPPORT_LITTLE_ENDIAN |
783e6a72 | 87 | select SUPPORT_OF_CONTROL |
51631259 | 88 | |
51631259 MY |
89 | config M68K |
90 | bool "M68000 architecture" | |
6463fd8f | 91 | select HAVE_PRIVATE_LIBGCC |
1e48392e | 92 | select USE_PRIVATE_LIBGCC |
405fc830 DW |
93 | select SYS_BOOT_GET_CMDLINE |
94 | select SYS_BOOT_GET_KBD | |
ab92b38a | 95 | select SYS_CACHE_SHIFT_4 |
cbef2954 | 96 | select SUPPORT_BIG_ENDIAN |
abe0f879 | 97 | select SUPPORT_OF_CONTROL |
51631259 MY |
98 | |
99 | config MICROBLAZE | |
100 | bool "MicroBlaze architecture" | |
cbef2954 JY |
101 | select SUPPORT_BIG_ENDIAN |
102 | select SUPPORT_LITTLE_ENDIAN | |
783e6a72 | 103 | select SUPPORT_OF_CONTROL |
a36d8672 MS |
104 | imply CMD_TIMER |
105 | imply SPL_REGMAP if SPL | |
106 | imply SPL_TIMER if SPL | |
107 | imply TIMER | |
108 | imply XILINX_TIMER | |
51631259 MY |
109 | |
110 | config MIPS | |
111 | bool "MIPS architecture" | |
9a387128 | 112 | select HAVE_ARCH_IOREMAP |
45ccec8f | 113 | select HAVE_PRIVATE_LIBGCC |
0fc13a90 | 114 | select SUPPORT_OF_CONTROL |
1dd56db5 | 115 | select SPL_SEPARATE_BSS if SPL |
51631259 | 116 | |
51631259 MY |
117 | config NIOS2 |
118 | bool "Nios II architecture" | |
bcae80e9 | 119 | select CPU |
5ed063d1 | 120 | select DM |
448e2b63 | 121 | select DM_EVENT |
5ed063d1 | 122 | select OF_CONTROL |
cbef2954 | 123 | select SUPPORT_LITTLE_ENDIAN |
5ed063d1 | 124 | select SUPPORT_OF_CONTROL |
08a00cba | 125 | imply CMD_DM |
51631259 | 126 | |
51631259 MY |
127 | config PPC |
128 | bool "PowerPC architecture" | |
45ccec8f | 129 | select HAVE_PRIVATE_LIBGCC |
cbef2954 | 130 | select SUPPORT_BIG_ENDIAN |
c1c61573 | 131 | select SUPPORT_OF_CONTROL |
405fc830 DW |
132 | select SYS_BOOT_GET_CMDLINE |
133 | select SYS_BOOT_GET_KBD | |
51631259 | 134 | |
068feb9b | 135 | config RISCV |
117a433d | 136 | bool "RISC-V architecture" |
7c8d210b | 137 | select CREATE_ARCH_SYMLINK |
e6b937f3 | 138 | select HAVE_SETJMP |
b17e280b | 139 | select SUPPORT_ACPI |
cbef2954 | 140 | select SUPPORT_LITTLE_ENDIAN |
068feb9b | 141 | select SUPPORT_OF_CONTROL |
bf6cc82c BM |
142 | select OF_CONTROL |
143 | select DM | |
448e2b63 | 144 | select DM_EVENT |
57b9900c | 145 | imply SPL_SEPARATE_BSS if SPL |
cd1f45c2 | 146 | imply DM_SERIAL |
cd1f45c2 BM |
147 | imply DM_MMC |
148 | imply DM_SPI | |
149 | imply DM_SPI_FLASH | |
150 | imply BLK | |
151 | imply CLK | |
152 | imply MTD | |
153 | imply TIMER | |
bf6cc82c | 154 | imply CMD_DM |
8c59f202 LA |
155 | imply SPL_DM |
156 | imply SPL_OF_CONTROL | |
157 | imply SPL_LIBCOMMON_SUPPORT | |
158 | imply SPL_LIBGENERIC_SUPPORT | |
2a736066 | 159 | imply SPL_SERIAL |
8c59f202 | 160 | imply SPL_TIMER |
068feb9b | 161 | |
51631259 MY |
162 | config SANDBOX |
163 | bool "Sandbox" | |
e6b937f3 | 164 | select HAVE_SETJMP |
94bb891e | 165 | select ARCH_SUPPORTS_LTO |
e5ec4815 | 166 | select BOARD_LATE_INIT |
efc06448 | 167 | select BZIP2 |
512369a7 | 168 | select CMD_POWEROFF if CMDLINE |
58d423b8 | 169 | select DM |
448e2b63 | 170 | select DM_EVENT |
0518e7a2 | 171 | select DM_FUZZING_ENGINE |
5ed063d1 MS |
172 | select DM_GPIO |
173 | select DM_I2C | |
558e1257 | 174 | select DM_KEYBOARD |
5ed063d1 | 175 | select DM_MMC |
58d423b8 | 176 | select DM_SERIAL |
58d423b8 | 177 | select DM_SPI |
5ed063d1 | 178 | select DM_SPI_FLASH |
efc06448 | 179 | select GZIP_COMPRESSED |
68e54040 | 180 | select IO_TRACE |
d56b4b19 | 181 | select LZO |
db04ff42 | 182 | select MTD |
1c0bc80a | 183 | select OF_BOARD_SETUP |
bb413337 | 184 | select PCI_ENDPOINT |
5ed063d1 MS |
185 | select SPI |
186 | select SUPPORT_OF_CONTROL | |
cbef2954 JY |
187 | select SUPPORT_BIG_ENDIAN |
188 | select SUPPORT_LITTLE_ENDIAN | |
512369a7 | 189 | select SYSRESET_CMD_POWEROFF if CMD_POWEROFF |
ab92b38a | 190 | select SYS_CACHE_SHIFT_4 |
57c675d6 | 191 | select IRQ |
512369a7 | 192 | select SUPPORT_EXTENSION_SCAN if CMDLINE |
e1722fcb | 193 | select SUPPORT_ACPI |
0f1caa98 | 194 | imply BITREVERSE |
919e7a8f | 195 | select BLOBLIST |
1b457e75 | 196 | imply LTO |
08a00cba | 197 | imply CMD_DM |
6ca5ff3f | 198 | imply CMD_EXCEPTION |
ded48cdc | 199 | imply CMD_GETTIME |
551c3934 | 200 | imply CMD_HASH |
594e8d1c | 201 | imply CMD_IO |
7d0f5c13 | 202 | imply CMD_IOTRACE |
ee7c0e71 | 203 | imply CMD_LZMADEC |
a4298dda | 204 | imply CMD_SF |
5ed063d1 | 205 | imply CMD_SF_TEST |
91d27a17 TR |
206 | imply CRC32_VERIFY |
207 | imply FAT_WRITE | |
31b8217e | 208 | imply FIRMWARE |
0518e7a2 | 209 | imply FUZZING_ENGINE_SANDBOX |
221a949e | 210 | imply HASH_VERIFY |
91d27a17 | 211 | imply LZMA |
fe39e8e0 | 212 | imply TEE |
0a60a81b JW |
213 | imply AVB_VERIFY |
214 | imply LIBAVB | |
215 | imply CMD_AVB | |
d3adee1d | 216 | imply PARTITION_TYPE_GUID |
7c591a84 IO |
217 | imply SCP03 |
218 | imply CMD_SCP03 | |
0a60a81b | 219 | imply UDP_FUNCTION_FASTBOOT |
4f89d494 BM |
220 | imply VIRTIO_MMIO |
221 | imply VIRTIO_PCI | |
222 | imply VIRTIO_SANDBOX | |
ade8b300 SG |
223 | # Re-enable this when fully implemented |
224 | # imply VIRTIO_BLK | |
4f89d494 | 225 | imply VIRTIO_NET |
2a049572 | 226 | imply DM_SOUND |
bb413337 | 227 | imply PCI_SANDBOX_EP |
c882163b | 228 | imply PCH |
ec9594a5 AM |
229 | imply PHYLIB |
230 | imply DM_MDIO | |
c3d9f3f8 | 231 | imply DM_MDIO_MUX |
0992a90d | 232 | imply ACPI |
3b65ee34 SG |
233 | imply ACPI_PMC |
234 | imply ACPI_PMC_SANDBOX | |
235 | imply CMD_PMC | |
4a4830cf | 236 | imply CMD_CLONE |
f158ba15 | 237 | imply SILENT_CONSOLE |
51bb3384 | 238 | imply BOOTARGS_SUBST |
ff98da06 CM |
239 | imply PHY_FIXED |
240 | imply DM_DSA | |
95300f20 | 241 | imply CMD_EXTENSION |
93e1edff | 242 | imply KEYBOARD |
6405ab7a | 243 | imply PHYSMEM |
437992d3 | 244 | imply GENERATE_ACPI_TABLE |
059df562 | 245 | imply BINMAN |
04291ee0 AG |
246 | imply CMD_MBR |
247 | imply CMD_MMC | |
909b15ca SG |
248 | imply BOOTSTD_DEFAULTS if BOOTSTD_FULL && CMDLINE |
249 | imply BOOTMETH_DISTRO if BOOTSTD_FULL && CMDLINE | |
250 | imply CMD_SYSBOOT if BOOTSTD_FULL | |
51631259 MY |
251 | |
252 | config SH | |
253 | bool "SuperH architecture" | |
cbef2954 | 254 | select SUPPORT_LITTLE_ENDIAN |
45ccec8f | 255 | select HAVE_PRIVATE_LIBGCC |
8c2c4635 | 256 | select SUPPORT_OF_CONTROL |
51631259 | 257 | |
51631259 MY |
258 | config X86 |
259 | bool "x86 architecture" | |
e6b937f3 | 260 | select HAVE_SETJMP |
98987902 SG |
261 | select SUPPORT_SPL |
262 | select SUPPORT_TPL | |
cbef2954 | 263 | select SUPPORT_LITTLE_ENDIAN |
a350c6a6 | 264 | select CREATE_ARCH_SYMLINK |
58d423b8 | 265 | select DM |
3bf9a8e8 | 266 | select HAVE_ARCH_IOMAP |
5ed063d1 MS |
267 | select HAVE_PRIVATE_LIBGCC |
268 | select OF_CONTROL | |
4f0faacb | 269 | select PCI |
e1722fcb | 270 | select SUPPORT_ACPI |
5ed063d1 | 271 | select SUPPORT_OF_CONTROL |
ab92b38a | 272 | select SYS_CACHE_SHIFT_6 |
0ce9c576 | 273 | select TIMER |
5ed063d1 | 274 | select USE_PRIVATE_LIBGCC |
0ce9c576 | 275 | select X86_TSC_TIMER |
543d091e | 276 | select IRQ |
bcd4e6f3 | 277 | imply HAS_ROM if X86_RESET_VECTOR |
24357dfd | 278 | imply BLK |
08a00cba | 279 | imply CMD_DM |
5ed063d1 MS |
280 | imply CMD_FPGA_LOADMK |
281 | imply CMD_GETTIME | |
282 | imply CMD_IO | |
283 | imply CMD_IRQ | |
284 | imply CMD_PCI | |
a4298dda | 285 | imply CMD_SF |
5ed063d1 | 286 | imply CMD_SF_TEST |
4f0faacb BM |
287 | imply DM_GPIO |
288 | imply DM_KEYBOARD | |
b7c6baef | 289 | imply DM_MMC |
4f0faacb | 290 | imply DM_RTC |
b630f8b3 | 291 | imply SCSI |
5ed063d1 | 292 | imply DM_SERIAL |
db04ff42 | 293 | imply MTD |
4f0faacb BM |
294 | imply DM_SPI |
295 | imply DM_SPI_FLASH | |
296 | imply DM_USB | |
91caa3bb | 297 | imply LAST_STAGE_INIT |
b86986c7 | 298 | imply VIDEO |
b37b7b20 | 299 | imply SYSRESET |
09259fce | 300 | imply SPL_SYSRESET |
b37b7b20 | 301 | imply SYSRESET_X86 |
f58ad98a CP |
302 | imply USB_ETHER_ASIX |
303 | imply USB_ETHER_SMSC95XX | |
5ed063d1 | 304 | imply USB_HOST_ETHER |
c882163b | 305 | imply PCH |
6405ab7a | 306 | imply PHYSMEM |
31d5261d | 307 | imply RTC_MC146818 |
0992a90d | 308 | imply ACPI |
27ba6289 | 309 | imply ACPIGEN if !QEMU && !EFI_APP |
839d66cd SG |
310 | imply SYSINFO if GENERATE_SMBIOS_TABLE |
311 | imply SYSINFO_SMBIOS if GENERATE_SMBIOS_TABLE | |
d6b318de | 312 | imply TIMESTAMP |
51631259 | 313 | |
98987902 SG |
314 | # Thing to enable for when SPL/TPL are enabled: SPL |
315 | imply SPL_DM | |
316 | imply SPL_OF_LIBFDT | |
9ca00684 | 317 | imply SPL_DRIVERS_MISC |
83061dbd | 318 | imply SPL_GPIO |
e556d3d6 | 319 | imply SPL_PINCTRL |
98987902 SG |
320 | imply SPL_LIBCOMMON_SUPPORT |
321 | imply SPL_LIBGENERIC_SUPPORT | |
2a736066 | 322 | imply SPL_SERIAL |
98987902 | 323 | imply SPL_SPI_FLASH_SUPPORT |
ea2ca7e1 | 324 | imply SPL_SPI |
98987902 SG |
325 | imply SPL_OF_CONTROL |
326 | imply SPL_TIMER | |
327 | imply SPL_REGMAP | |
328 | imply SPL_SYSCON | |
329 | # TPL | |
330 | imply TPL_DM | |
9ca00684 | 331 | imply TPL_DRIVERS_MISC |
83061dbd | 332 | imply TPL_GPIO |
e556d3d6 | 333 | imply TPL_PINCTRL |
98987902 SG |
334 | imply TPL_LIBCOMMON_SUPPORT |
335 | imply TPL_LIBGENERIC_SUPPORT | |
2a736066 | 336 | imply TPL_SERIAL |
98987902 SG |
337 | imply TPL_OF_CONTROL |
338 | imply TPL_TIMER | |
339 | imply TPL_REGMAP | |
340 | imply TPL_SYSCON | |
341 | ||
c978b524 CZ |
342 | config XTENSA |
343 | bool "Xtensa architecture" | |
344 | select CREATE_ARCH_SYMLINK | |
cbef2954 | 345 | select SUPPORT_LITTLE_ENDIAN |
c978b524 CZ |
346 | select SUPPORT_OF_CONTROL |
347 | ||
51631259 MY |
348 | endchoice |
349 | ||
3174e4e8 MY |
350 | config SYS_ARCH |
351 | string | |
352 | help | |
353 | This option should contain the architecture name to build the | |
354 | appropriate arch/<CONFIG_SYS_ARCH> directory. | |
355 | All the architectures should specify this option correctly. | |
356 | ||
357 | config SYS_CPU | |
358 | string | |
359 | help | |
360 | This option should contain the CPU name to build the correct | |
361 | arch/<CONFIG_SYS_ARCH>/cpu/<CONFIG_SYS_CPU> directory. | |
362 | ||
363 | This is optional. For those targets without the CPU directory, | |
364 | leave this option empty. | |
365 | ||
366 | config SYS_SOC | |
367 | string | |
368 | help | |
369 | This option should contain the SoC name to build the directory | |
370 | arch/<CONFIG_SYS_ARCH>/cpu/<CONFIG_SYS_CPU>/<CONFIG_SYS_SOC>. | |
371 | ||
372 | This is optional. For those targets without the SoC directory, | |
373 | leave this option empty. | |
374 | ||
375 | config SYS_VENDOR | |
376 | string | |
377 | help | |
378 | This option should contain the vendor name of the target board. | |
379 | If it is set and | |
380 | board/<CONFIG_SYS_VENDOR>/common/Makefile exists, the vendor common | |
381 | directory is compiled. | |
382 | If CONFIG_SYS_BOARD is also set, the sources under | |
383 | board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD> directory are compiled. | |
384 | ||
385 | This is optional. For those targets without the vendor directory, | |
386 | leave this option empty. | |
387 | ||
388 | config SYS_BOARD | |
389 | string | |
390 | help | |
391 | This option should contain the name of the target board. | |
392 | If it is set, either board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD> | |
393 | or board/<CONFIG_SYS_BOARD> directory is compiled depending on | |
394 | whether CONFIG_SYS_VENDOR is set or not. | |
395 | ||
396 | This is optional. For those targets without the board directory, | |
397 | leave this option empty. | |
398 | ||
399 | config SYS_CONFIG_NAME | |
3dd14868 TR |
400 | string "Board header file" if ARCH_MESON || ARCH_VERSAL || \ |
401 | ARCH_VERSAL_NET || ARCH_ZYNQ || ARCH_ZYNQMP || \ | |
402 | ARCH_ZYNQMP_R5 || MICROBLAZE || NIOS2 | |
403 | default "meson64" if ARCH_MESON | |
404 | default "microblaze-generic" if MICROBLAZE | |
405 | default "xilinx_versal" if ARCH_VERSAL | |
406 | default "xilinx_versal_net" if ARCH_VERSAL_NET | |
407 | default "xilinx_zynqmp" if ARCH_ZYNQMP | |
408 | default "xilinx_zynqmp_r5" if ARCH_ZYNQMP_R5 | |
409 | default "zynq-common" if ARCH_ZYNQ | |
3174e4e8 MY |
410 | help |
411 | This option should contain the base name of board header file. | |
412 | The header file include/configs/<CONFIG_SYS_CONFIG_NAME>.h | |
413 | should be included from include/config.h. | |
414 | ||
add49671 VR |
415 | config SYS_DISABLE_DCACHE_OPS |
416 | bool | |
417 | help | |
418 | This option disables dcache flush and dcache invalidation | |
419 | operations. For example, on coherent systems where cache | |
420 | operatios are not required, enable this option to avoid them. | |
421 | Note that, its up to the individual architectures to implement | |
422 | this functionality. | |
423 | ||
be7dbb60 | 424 | config SYS_IMMR |
dd2986ac | 425 | hex "Address for the Internal Memory-Mapped Registers (IMMR) window" |
be7dbb60 TR |
426 | depends on PPC || FSL_LSCH2 || FSL_LSCH3 || ARCH_LS1021A |
427 | default 0xFF000000 if MPC8xx | |
428 | default 0xF0000000 if ARCH_MPC8313 | |
429 | default 0xE0000000 if MPC83xx && !ARCH_MPC8313 | |
430 | default 0x01000000 if ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3 | |
39f42fe2 T |
431 | default 0xFFE00000 if ARCH_P1010 || ARCH_P1011 || ARCH_P1020 || \ |
432 | ARCH_P1021 || ARCH_P1024 || ARCH_P1025 || \ | |
433 | ARCH_P2020 | |
be7dbb60 TR |
434 | default SYS_CCSRBAR_DEFAULT |
435 | help | |
436 | Address for the Internal Memory-Mapped Registers (IMMR) window used | |
437 | to configure the features of many Freescale / NXP SoCs. | |
438 | ||
e52fca22 TR |
439 | config MONITOR_IS_IN_RAM |
440 | bool "U-Boot is loaded in to RAM by a pre-loader" | |
441 | depends on M68K || NIOS2 | |
442 | ||
c394e8d0 | 443 | menu "Skipping low level initialization functions" |
11232139 | 444 | depends on ARM || MIPS || RISCV |
c394e8d0 HS |
445 | |
446 | config SKIP_LOWLEVEL_INIT | |
447 | bool "Skip calls to certain low level initialization functions" | |
a2ac2b96 TR |
448 | help |
449 | If enabled, then certain low level initializations (like setting up | |
450 | the memory controller) are omitted and/or U-Boot does not relocate | |
451 | itself into RAM. | |
452 | Normally this variable MUST NOT be defined. The only exception is | |
453 | when U-Boot is loaded (to RAM) by some other boot loader or by a | |
454 | debugger which performs these initializations itself. | |
455 | ||
456 | config SPL_SKIP_LOWLEVEL_INIT | |
c394e8d0 HS |
457 | bool "Skip calls to certain low level initialization functions in SPL" |
458 | depends on SPL | |
a2ac2b96 TR |
459 | help |
460 | If enabled, then certain low level initializations (like setting up | |
461 | the memory controller) are omitted and/or U-Boot does not relocate | |
462 | itself into RAM. | |
463 | Normally this variable MUST NOT be defined. The only exception is | |
464 | when U-Boot is loaded (to RAM) by some other boot loader or by a | |
465 | debugger which performs these initializations itself. | |
466 | ||
467 | config TPL_SKIP_LOWLEVEL_INIT | |
c394e8d0 | 468 | bool "Skip calls to certain low level initialization functions in TPL" |
a2ac2b96 TR |
469 | depends on SPL && ARM |
470 | help | |
471 | If enabled, then certain low level initializations (like setting up | |
472 | the memory controller) are omitted and/or U-Boot does not relocate | |
473 | itself into RAM. | |
474 | Normally this variable MUST NOT be defined. The only exception is | |
475 | when U-Boot is loaded (to RAM) by some other boot loader or by a | |
476 | debugger which performs these initializations itself. | |
477 | ||
478 | config SKIP_LOWLEVEL_INIT_ONLY | |
c394e8d0 | 479 | bool "Skip call to lowlevel_init during early boot ONLY" |
a2ac2b96 TR |
480 | depends on ARM |
481 | help | |
482 | This allows just the call to lowlevel_init() to be skipped. The | |
483 | normal CP15 init (such as enabling the instruction cache) is still | |
484 | performed. | |
485 | ||
486 | config SPL_SKIP_LOWLEVEL_INIT_ONLY | |
c394e8d0 | 487 | bool "Skip call to lowlevel_init during early SPL boot ONLY" |
a2ac2b96 TR |
488 | depends on SPL && ARM |
489 | help | |
490 | This allows just the call to lowlevel_init() to be skipped. The | |
491 | normal CP15 init (such as enabling the instruction cache) is still | |
492 | performed. | |
493 | ||
494 | config TPL_SKIP_LOWLEVEL_INIT_ONLY | |
c394e8d0 | 495 | bool "Skip call to lowlevel_init during early TPL boot ONLY" |
a2ac2b96 TR |
496 | depends on TPL && ARM |
497 | help | |
498 | This allows just the call to lowlevel_init() to be skipped. The | |
499 | normal CP15 init (such as enabling the instruction cache) is still | |
500 | performed. | |
501 | ||
c394e8d0 HS |
502 | endmenu |
503 | ||
8c778f78 TR |
504 | config SYS_HAS_NONCACHED_MEMORY |
505 | bool "Enable reserving a non-cached memory area for drivers" | |
506 | depends on (ARM || MIPS) && (RTL8169 || MEDIATEK_ETH) | |
507 | help | |
508 | This is useful for drivers that would otherwise require a lot of | |
509 | explicit cache maintenance. For some drivers it's also impossible to | |
510 | properly maintain the cache. For example if the regions that need to | |
511 | be flushed are not a multiple of the cache-line size, *and* padding | |
512 | cannot be allocated between the regions to align them (i.e. if the | |
513 | HW requires a contiguous array of regions, and the size of each | |
514 | region is not cache-aligned), then a flush of one region may result | |
515 | in overwriting data that hardware has written to another region in | |
516 | the same cache-line. This can happen for example in network drivers | |
517 | where descriptors for buffers are typically smaller than the CPU | |
518 | cache-line (e.g. 16 bytes vs. 32 or 64 bytes). | |
519 | ||
520 | config SYS_NONCACHED_MEMORY | |
521 | hex "Size in bytes of the non-cached memory area" | |
522 | depends on SYS_HAS_NONCACHED_MEMORY | |
523 | default 0x100000 | |
524 | help | |
525 | Size of non-cached memory area. This area of memory will be typically | |
526 | located right below the malloc() area and mapped uncached in the MMU. | |
527 | ||
51631259 MY |
528 | source "arch/arc/Kconfig" |
529 | source "arch/arm/Kconfig" | |
51631259 MY |
530 | source "arch/m68k/Kconfig" |
531 | source "arch/microblaze/Kconfig" | |
532 | source "arch/mips/Kconfig" | |
51631259 | 533 | source "arch/nios2/Kconfig" |
51631259 MY |
534 | source "arch/powerpc/Kconfig" |
535 | source "arch/sandbox/Kconfig" | |
536 | source "arch/sh/Kconfig" | |
51631259 | 537 | source "arch/x86/Kconfig" |
c978b524 | 538 | source "arch/xtensa/Kconfig" |
068feb9b | 539 | source "arch/riscv/Kconfig" |
c6c0e56f | 540 | |
d622b089 TR |
541 | if ARM || M68K || PPC |
542 | ||
543 | source "arch/Kconfig.nxp" | |
544 | ||
545 | endif | |
546 | ||
c6c0e56f | 547 | source "board/keymile/Kconfig" |
89e81e6c | 548 | |
89e81e6c MS |
549 | choice |
550 | prompt "Endianness selection" | |
cbef2954 JY |
551 | default SYS_BIG_ENDIAN if MIPS || MICROBLAZE |
552 | default SYS_LITTLE_ENDIAN | |
89e81e6c | 553 | help |
cbef2954 | 554 | Some boards can be configured for either little or big endian |
89e81e6c MS |
555 | byte order. These modes require different U-Boot images. In general there |
556 | is one preferred byteorder for a particular system but some systems are | |
557 | just as commonly used in the one or the other endianness. | |
558 | ||
559 | config SYS_BIG_ENDIAN | |
560 | bool "Big endian" | |
cbef2954 | 561 | depends on SUPPORT_BIG_ENDIAN |
89e81e6c MS |
562 | |
563 | config SYS_LITTLE_ENDIAN | |
564 | bool "Little endian" | |
cbef2954 | 565 | depends on SUPPORT_LITTLE_ENDIAN |
89e81e6c | 566 | endchoice |